From 37eb821e2e84b29f65a186ea14534b8ff6de499c Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 28 Apr 2023 12:08:42 +0800 Subject: [PATCH] ddr: imx93: Add 625M bypass clock support Add 625M bypass clock that may be used DRAM 625M bypass mode support. Signed-off-by: Jacky Bai Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx9/clock.c | 3 +++ drivers/ddr/imx/phy/ddrphy_utils.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 957f80fce2..a7ecccaf87 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -648,6 +648,9 @@ void dram_pll_init(ulong pll_val) void dram_enable_bypass(ulong clk_val) { switch (clk_val) { + case MHZ(625): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD2, 1); + break; case MHZ(400): ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2); break; diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index 6a8b6be42b..fd8b4113b7 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -148,6 +148,9 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(167)); dram_disable_bypass(); break; + case 625: + dram_enable_bypass(MHZ(625)); + break; case 400: dram_enable_bypass(MHZ(400)); break;