Merge branch 'master' of git://git.denx.de/u-boot-mips

Please pull another update for Broadcom MIPS.
This contains new SoC's, new boards and new drivers and some bugfixes.

arch/mips/dts/Makefile

@@ -9,8 +9,11 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
 dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
+dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
 dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
 dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
+dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
+dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 
 targets += $(dtb-y)

arch/mips/dts/brcm,bcm3380.dtsi

@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm3380-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm3380-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm3380";
+
+	cpus {
+		reg = <0x14e00000 0x4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu@0 {
+			compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu@1 {
+			compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <1>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <48000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_clk0: periph-clk@14e00004 {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0x14e00004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		periph_clk1: periph-clk@14e00008 {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0x14e00008 0x4>;
+			#clock-cells = <1>;
+		};
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		memory-controller@12000000 {
+			compatible = "brcm,bcm6328-mc";
+			reg = <0x12000000 0x1000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_rst0: reset-controller@14e0008c {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x14e0008c 0x4>;
+			#reset-cells = <1>;
+		};
+
+		periph_rst1: reset-controller@14e00090 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x14e00090 0x4>;
+			#reset-cells = <1>;
+		};
+
+		pll_cntl: syscon@14e00094 {
+			compatible = "syscon";
+			reg = <0x14e00094 0x4>;
+		};
+
+		syscon-reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pll_cntl>;
+			offset = <0x0>;
+			mask = <0x1>;
+		};
+
+		wdt: watchdog@14e000dc {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x14e000dc 0xc>;
+
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
+		gpio0: gpio-controller@14e00100 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x14e00100 0x4>, <0x14e00108 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			status = "disabled";
+		};
+
+		gpio1: gpio-controller@14e00104 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x14e00104 0x4>, <0x14e0010c 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <3>;
+
+			status = "disabled";
+		};
+
+		uart0: serial@14e00200 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x14e00200 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		uart1: serial@14e00220 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x14e00220 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		leds: led-controller@14e00f00 {
+			compatible = "brcm,bcm6328-leds";
+			reg = <0x14e00f00 0x1c>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+	};
+};

arch/mips/dts/brcm,bcm63268.dtsi

@@ -84,6 +84,17 @@
 			#reset-cells = <1>;
 		};
 
+		wdt: watchdog@1000009c {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x1000009c 0xc>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
 		gpio1: gpio-controller@100000c0 {
 			compatible = "brcm,bcm6345-gpio";
 			reg = <0x100000c0 0x4>, <0x100000c8 0x4>;

arch/mips/dts/brcm,bcm6328.dtsi

@@ -78,6 +78,17 @@
 			mask = <0x1>;
 		};
 
+		wdt: watchdog@1000005c {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x1000005c 0xc>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
 		gpio: gpio-controller@10000084 {
 			compatible = "brcm,bcm6345-gpio";
 			reg = <0x10000084 0x4>, <0x1000008c 0x4>;

arch/mips/dts/brcm,bcm6338.dtsi

@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6338-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6338-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm6338";
+
+	cpus {
+		reg = <0xfffe0000 0x4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu@0 {
+			compatible = "brcm,bcm6338-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_clk: periph-clk {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0xfffe0004 0x4>;
+			#clock-cells = <1>;
+		};
+	};
+
+	pflash: nor@1fc00000 {
+		compatible = "cfi-flash";
+		reg = <0x1fc00000 0x400000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		status = "disabled";
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		pll_cntl: syscon@fffe0008 {
+			compatible = "syscon";
+			reg = <0xfffe0008 0x4>;
+		};
+
+		syscon-reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pll_cntl>;
+			offset = <0x0>;
+			mask = <0x1>;
+		};
+
+		periph_rst: reset-controller@fffe0028 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0xfffe0028 0x4>;
+			#reset-cells = <1>;
+		};
+
+		wdt: watchdog@fffe021c {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xfffe021c 0xc>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
+		uart0: serial@fffe0300 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0xfffe0300 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		gpio: gpio-controller@fffe0404 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+
+			status = "disabled";
+		};
+
+		memory-controller@fffe3100 {
+			compatible = "brcm,bcm6338-mc";
+			reg = <0xfffe3100 0x38>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};

arch/mips/dts/brcm,bcm6348.dtsi

@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6348-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6348-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm6348";
+
+	cpus {
+		reg = <0xfffe0000 0x4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu@0 {
+			compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_clk: periph-clk {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0xfffe0004 0x4>;
+			#clock-cells = <1>;
+		};
+	};
+
+	pflash: nor@1fc00000 {
+		compatible = "cfi-flash";
+		reg = <0x1fc00000 0x2000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		status = "disabled";
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		pll_cntl: syscon@fffe0008 {
+			compatible = "syscon";
+			reg = <0xfffe0008 0x4>;
+		};
+
+		syscon-reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pll_cntl>;
+			offset = <0x0>;
+			mask = <0x1>;
+		};
+
+		periph_rst: reset-controller@fffe0028 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0xfffe0028 0x4>;
+			#reset-cells = <1>;
+		};
+
+		wdt: watchdog@fffe021c {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xfffe021c 0xc>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
+		uart0: serial@fffe0300 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0xfffe0300 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		gpio1: gpio-controller@fffe0400 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <5>;
+
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller@fffe0404 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			status = "disabled";
+		};
+
+		memory-controller@fffe2300 {
+			compatible = "brcm,bcm6338-mc";
+			reg = <0xfffe2300 0x38>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};

arch/mips/dts/brcm,bcm6358.dtsi

@@ -87,6 +87,17 @@
 			#reset-cells = <1>;
 		};
 
+		wdt: watchdog@fffe005c {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xfffe005c 0xc>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
 		gpio1: gpio-controller@fffe0080 {
 			compatible = "brcm,bcm6345-gpio";
 			reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>;

arch/mips/dts/comtrend,ct-5361.dts

@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6348.dtsi"
+
+/ {
+	model = "Comtrend CT-5361";
+	compatible = "comtrend,ct-5361", "brcm,bcm6348";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power_green {
+			label = "CT-5361:green:power";
+			gpios = <&gpio0 0 1>;
+		};
+
+		alarm_red {
+			label = "CT-5361:red:alarm";
+			gpios = <&gpio0 2 1>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&pflash {
+	status = "okay";
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};

arch/mips/dts/netgear,cg3100d.dts

@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm3380.dtsi"
+
+/ {
+	model = "Netgear CG3100D";
+	compatible = "netgear,cg3100d", "brcm,bcm3380";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		wifi_green {
+			label = "CG3100D:green:wifi";
+			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+		};
+
+		wps_green {
+			label = "CG3100D:green:wps";
+			gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
+		};
+
+		power_red {
+			label = "CG3100D:red:power";
+			gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&leds {
+	status = "okay";
+
+	led@0 {
+		reg = <0>;
+		active-low;
+		label = "CG3100D:green:power";
+	};
+
+	led@1 {
+		reg = <1>;
+		active-low;
+		label = "CG3100D:green:downlink";
+	};
+
+	led@2 {
+		reg = <2>;
+		active-low;
+		label = "CG3100D:orange:downlink";
+	};
+
+	led@3 {
+		reg = <3>;
+		active-low;
+		label = "CG3100D:green:uplink";
+	};
+
+	led@4 {
+		reg = <4>;
+		active-low;
+		label = "CG3100D:orange:uplink";
+	};
+
+	led@6 {
+		reg = <6>;
+		active-low;
+		label = "CG3100D:green:inet";
+	};
+
+	led@7 {
+		reg = <7>;
+		active-low;
+		label = "CG3100D:green:stby";
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};

arch/mips/dts/sagem,f@st1704.dts

@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6338.dtsi"
+
+/ {
+	model = "Sagem F@ST1704";
+	compatible = "sagem,f@st1704", "brcm,bcm6338";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		inet_green {
+			label = "F@ST1704:green:inet";
+			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+		};
+
+		power_green {
+			label = "F@ST1704:green:power";
+			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+		};
+
+		inet_red {
+			label = "F@ST1704:red:inet";
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};

arch/mips/mach-bmips/Kconfig

@@ -2,13 +2,27 @@ menu "Broadcom MIPS platforms"
 	depends on ARCH_BMIPS
 
 config SYS_SOC
+	default "bcm3380" if SOC_BMIPS_BCM3380
 	default "bcm6328" if SOC_BMIPS_BCM6328
+	default "bcm6338" if SOC_BMIPS_BCM6338
+	default "bcm6348" if SOC_BMIPS_BCM6348
 	default "bcm6358" if SOC_BMIPS_BCM6358
 	default "bcm63268" if SOC_BMIPS_BCM63268
 
 choice
 	prompt "Broadcom MIPS SoC select"
 
+config SOC_BMIPS_BCM3380
+	bool "BMIPS BCM3380 family"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select MIPS_TUNE_4KC
+	select MIPS_L1_CACHE_SHIFT_4
+	select SWAP_IO_SPACE
+	select SYSRESET_WATCHDOG
+	help
+	  This supports BMIPS BCM3380 family.
+
 config SOC_BMIPS_BCM6328
 	bool "BMIPS BCM6328 family"
 	select SUPPORTS_BIG_ENDIAN
@@ -20,6 +34,28 @@ config SOC_BMIPS_BCM6328
 	help
 	  This supports BMIPS BCM6328 family including BCM63281 and BCM63283.
 
+config SOC_BMIPS_BCM6338
+	bool "BMIPS BCM6338 family"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select MIPS_TUNE_4KC
+	select MIPS_L1_CACHE_SHIFT_4
+	select SWAP_IO_SPACE
+	select SYSRESET_SYSCON
+	help
+	  This supports BMIPS BCM6338 family.
+
+config SOC_BMIPS_BCM6348
+	bool "BMIPS BCM6348 family"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select MIPS_TUNE_4KC
+	select MIPS_L1_CACHE_SHIFT_4
+	select SWAP_IO_SPACE
+	select SYSRESET_WATCHDOG
+	help
+	  This supports BMIPS BCM6348 family.
+
 config SOC_BMIPS_BCM6358
 	bool "BMIPS BCM6358 family"
 	select SUPPORTS_BIG_ENDIAN
@@ -52,21 +88,78 @@ config BOARD_COMTREND_AR5387UN
 	bool "Comtrend AR-5387un"
 	depends on SOC_BMIPS_BCM6328
 	select BMIPS_SUPPORTS_BOOT_RAM
+	help
+	  Comtrend AR-5387un boards have a BCM6328 SoC with 64 MB of RAM and 16
+	  MB of flash (SPI).
+	  Between its different peripherals there's an integrated switch with 4
+	  ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
+	  a BCM43225 (PCIe).
+
+config BOARD_COMTREND_CT5361
+	bool "Comtrend CT-5361"
+	depends on SOC_BMIPS_BCM6348
+	select BMIPS_SUPPORTS_BOOT_RAM
+	help
+	  Comtrend CT-5361 boards have a BCM6348 SoC with 16 MB of RAM and 4 MB
+	  of flash (CFI).
+	  Between its different peripherals there's a BCM5325 switch with 4
+	  ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and a
+	  BCM4312 (miniPCI).
 
 config BOARD_COMTREND_VR3032U
 	bool "Comtrend VR-3032u board"
 	depends on SOC_BMIPS_BCM63268
 	select BMIPS_SUPPORTS_BOOT_RAM
+	help
+	  Comtrend VR-3032u boards have a BCM63268 SoC with 64 MB of RAM and
+	  128 MB of flash (NAND).
+	  Between its different peripherals there's an integrated switch with 4
+	  ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs,
+	  and a BCM6362 (integrated).
 
 config BOARD_HUAWEI_HG556A
 	bool "Huawei EchoLife HG556a"
 	depends on SOC_BMIPS_BCM6358
 	select BMIPS_SUPPORTS_BOOT_RAM
+	help
+	  Huawei EchoLife HG556a boards have a BCM6358 SoC with 64 MB of RAM
+	  and 16 MB of flash (CFI).
+	  Between its different peripherals there's a BCM5325 switch with 4
+	  ethernet ports, 3 USB ports, 1 UART, GPIO buttons and LEDs, and
+	  a RT3062F/AR9223 (PCI).
+
+config BOARD_NETGEAR_CG3100D
+	bool "Netgear CG3100D"
+	depends on SOC_BMIPS_BCM3380
+	select BMIPS_SUPPORTS_BOOT_RAM
+	help
+	  Netgear CG3100D boards have a BCM3380 SoC with 64 MB of RAM and 8 MB
+	  of flash (SPI).
+	  Between its different peripherals there's a BCM53115 switch with 4
+	  ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225
+	  (miniPCIe).
+
+config BOARD_SAGEM_FAST1704
+	bool "Sagem F@ST1704"
+	depends on SOC_BMIPS_BCM6338
+	select BMIPS_SUPPORTS_BOOT_RAM
+	help
+	  Sagem F@ST1704 boards have a BCM6338 SoC with 16 MB of RAM and 4 MB
+	  of flash (SPI).
+	  Between its different peripherals there's a BCM5325 switch with 4
+	  ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM4312
+	  (miniPCI).
 
 config BOARD_SFR_NB4_SER
 	bool "SFR NeufBox 4 (Sercomm)"
 	depends on SOC_BMIPS_BCM6358
 	select BMIPS_SUPPORTS_BOOT_RAM
+	help
+	  SFR NeufBox 4 (Sercomm) boards have a BCM6358 SoC with 32 MB of RAM
+	  and 8 MB of flash (CFI).
+	  Between its different peripherals there's a BCM5325 switch with 4
+	  ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and
+	  a BCM4318 (PCI).
 
 endchoice
 
@@ -87,8 +180,11 @@ config BMIPS_SUPPORTS_BOOT_RAM
 	bool
 
 source "board/comtrend/ar5387un/Kconfig"
+source "board/comtrend/ct5361/Kconfig"
 source "board/comtrend/vr3032u/Kconfig"
 source "board/huawei/hg556a/Kconfig"
+source "board/netgear/cg3100d/Kconfig"
+source "board/sagem/f@st1704/Kconfig"
 source "board/sfr/nb4_ser/Kconfig"
 
 endmenu

arch/mips/mach-bmips/include/ioremap.h

@@ -18,7 +18,9 @@ static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
 
 static inline int is_bmips_internal_registers(phys_addr_t offset)
 {
-#if defined(CONFIG_SOC_BMIPS_BCM6358)
+#if defined(CONFIG_SOC_BMIPS_BCM6338) || \
+	defined(CONFIG_SOC_BMIPS_BCM6348) || \
+	defined(CONFIG_SOC_BMIPS_BCM6358)
 	if (offset >= 0xfffe0000)
 		return 1;
 #endif

board/comtrend/ct5361/Kconfig

@@ -0,0 +1,12 @@
+if BOARD_COMTREND_CT5361
+
+config SYS_BOARD
+	default "ct5361"
+
+config SYS_VENDOR
+	default "comtrend"
+
+config SYS_CONFIG_NAME
+	default "comtrend_ct5361"
+
+endif

board/comtrend/ct5361/MAINTAINERS

@@ -0,0 +1,6 @@
+COMTREND CT-5361 BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/comtrend/ct-5361/
+F:	include/configs/comtrend_ct5361.h
+F:	configs/comtrend_ct5361_ram_defconfig

board/comtrend/ct5361/Makefile

@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ct-5361.o

board/comtrend/ct5361/ct-5361.c

@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>

board/netgear/cg3100d/Kconfig

@@ -0,0 +1,12 @@
+if BOARD_NETGEAR_CG3100D
+
+config SYS_BOARD
+	default "cg3100d"
+
+config SYS_VENDOR
+	default "netgear"
+
+config SYS_CONFIG_NAME
+	default "netgear_cg3100d"
+
+endif

board/netgear/cg3100d/MAINTAINERS

@@ -0,0 +1,6 @@
+NETGEAR CG3100D BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/netgear/cg3100d/
+F:	include/configs/netgear_cg3100d.h
+F:	configs/netgear_cg3100d_ram_defconfig

board/netgear/cg3100d/Makefile

@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cg3100d.o

board/netgear/cg3100d/cg3100d.c

@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>

board/sagem/f@st1704/Kconfig

@@ -0,0 +1,12 @@
+if BOARD_SAGEM_FAST1704
+
+config SYS_BOARD
+	default "f@st1704"
+
+config SYS_VENDOR
+	default "sagem"
+
+config SYS_CONFIG_NAME
+	default "sagem_f@st1704"
+
+endif

board/sagem/f@st1704/MAINTAINERS

@@ -0,0 +1,6 @@
+SAGEM F@ST1704 BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/sagem/f@st1704/
+F:	include/configs/sagem_f@st1704.h
+F:	configs/sagem_f@st1704_ram_defconfig

board/sagem/f@st1704/Makefile

@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += f@st1704.o

board/sagem/f@st1704/f@st1704.c

@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>

configs/comtrend_ct5361_ram_defconfig

@@ -0,0 +1,57 @@
+CONFIG_ARCH_BMIPS=y
+CONFIG_BAUDRATE=115200
+CONFIG_BCM6345_CLK=y
+CONFIG_BCM6345_GPIO=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_BMIPS_BOOT_RAM=y
+CONFIG_BOARD_COMTREND_CT5361=y
+CONFIG_CFI_FLASH=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_FLASH=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LOADB=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361"
+CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_MTD=y
+CONFIG_MTD_DEVICE=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
+CONFIG_SOC_BMIPS_BCM6348=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_PROMPT="CT-5361 # "
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_WDT=y
+CONFIG_WDT_BCM6345=y

configs/netgear_cg3100d_ram_defconfig

@@ -0,0 +1,56 @@
+CONFIG_ARCH_BMIPS=y
+CONFIG_BAUDRATE=115200
+CONFIG_BCM6345_CLK=y
+CONFIG_BCM6345_GPIO=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_BMIPS_BOOT_RAM=y
+CONFIG_BOARD_NETGEAR_CG3100D=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LOADB=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d"
+CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_LED=y
+CONFIG_LED_BCM6328=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
+CONFIG_SOC_BMIPS_BCM3380=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_NO_FLASH=y
+CONFIG_SYS_PROMPT="CG3100D # "
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_WDT=y
+CONFIG_WDT_BCM6345=y

configs/sagem_f@st1704_ram_defconfig

@@ -0,0 +1,52 @@
+CONFIG_ARCH_BMIPS=y
+CONFIG_BAUDRATE=115200
+CONFIG_BCM6345_CLK=y
+CONFIG_BCM6345_GPIO=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_BMIPS_BOOT_RAM=y
+CONFIG_BOARD_SAGEM_FAST1704=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LOADB=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704"
+CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
+CONFIG_SOC_BMIPS_BCM6338=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_NO_FLASH=y
+CONFIG_SYS_PROMPT="F@ST1704 # "
+CONFIG_SYS_TEXT_BASE=0x80010000

drivers/cpu/bmips_cpu.c

@@ -30,6 +30,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define STRAPBUS_6328_FCVO_SHIFT	7
 #define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
 
+#define REG_BCM6348_PERF_MIPSPLLCFG	0x34
+#define MIPSPLLCFG_6348_M1CPU_SHIFT	6
+#define MIPSPLLCFG_6348_M1CPU_MASK	(0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
+#define MIPSPLLCFG_6348_N2_SHIFT	15
+#define MIPSPLLCFG_6348_N2_MASK		(0x1F << MIPSPLLCFG_6348_N2_SHIFT)
+#define MIPSPLLCFG_6348_N1_SHIFT	20
+#define MIPSPLLCFG_6348_N1_MASK		(0x7 << MIPSPLLCFG_6348_N1_SHIFT)
+
 #define REG_BCM6358_DDR_DMIPSPLLCFG	0x12b8
 #define DMIPSPLLCFG_6358_M1_SHIFT	0
 #define DMIPSPLLCFG_6358_M1_MASK	(0xff << DMIPSPLLCFG_6358_M1_SHIFT)
@@ -56,7 +64,7 @@ struct bmips_cpu_priv {
 };
 
 /* Specific CPU Ops */
-static int bcm6358_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
+static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 				int size)
 {
 	unsigned short cpu_id;
@@ -72,7 +80,7 @@ static int bcm6358_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 	return 0;
 }
 
-static int bcm6328_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
+static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 				int size)
 {
 	unsigned int cpu_id;
@@ -88,6 +96,11 @@ static int bcm6328_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 	return 0;
 }
 
+static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+	return 333000000;
+}
+
 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
 {
 	unsigned int mips_pll_fcvo;
@@ -115,6 +128,23 @@ static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
 	}
 }
 
+static ulong bcm6338_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+	return 240000000;
+}
+
+static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+	unsigned int tmp, n1, n2, m1;
+
+	tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
+	n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
+	n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
+	m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
+
+	return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
+}
+
 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
 {
 	unsigned int tmp, n1, n2, m1;
@@ -160,25 +190,48 @@ static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
 		return 2;
 }
 
+static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
+{
+	return 1;
+}
+
 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 {
 	return 2;
 }
 
+static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
+	.get_cpu_desc = bmips_short_cpu_desc,
+	.get_cpu_freq = bcm3380_get_cpu_freq,
+	.get_cpu_count = bcm6358_get_cpu_count,
+};
+
 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
-	.get_cpu_desc = bcm6328_get_cpu_desc,
+	.get_cpu_desc = bmips_long_cpu_desc,
 	.get_cpu_freq = bcm6328_get_cpu_freq,
 	.get_cpu_count = bcm6328_get_cpu_count,
 };
 
+static const struct bmips_cpu_hw bmips_cpu_bcm6338 = {
+	.get_cpu_desc = bmips_short_cpu_desc,
+	.get_cpu_freq = bcm6338_get_cpu_freq,
+	.get_cpu_count = bcm6345_get_cpu_count,
+};
+
+static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
+	.get_cpu_desc = bmips_short_cpu_desc,
+	.get_cpu_freq = bcm6348_get_cpu_freq,
+	.get_cpu_count = bcm6345_get_cpu_count,
+};
+
 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
-	.get_cpu_desc = bcm6358_get_cpu_desc,
+	.get_cpu_desc = bmips_short_cpu_desc,
 	.get_cpu_freq = bcm6358_get_cpu_freq,
 	.get_cpu_count = bcm6358_get_cpu_count,
 };
 
 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
-	.get_cpu_desc = bcm6328_get_cpu_desc,
+	.get_cpu_desc = bmips_long_cpu_desc,
 	.get_cpu_freq = bcm63268_get_cpu_freq,
 	.get_cpu_count = bcm6358_get_cpu_count,
 };
@@ -259,8 +312,17 @@ int bmips_cpu_probe(struct udevice *dev)
 
 static const struct udevice_id bmips_cpu_ids[] = {
 	{
+		.compatible = "brcm,bcm3380-cpu",
+		.data = (ulong)&bmips_cpu_bcm3380,
+	}, {
 		.compatible = "brcm,bcm6328-cpu",
 		.data = (ulong)&bmips_cpu_bcm6328,
+	}, {
+		.compatible = "brcm,bcm6338-cpu",
+		.data = (ulong)&bmips_cpu_bcm6338,
+	}, {
+		.compatible = "brcm,bcm6348-cpu",
+		.data = (ulong)&bmips_cpu_bcm6348,
 	}, {
 		.compatible = "brcm,bcm6358-cpu",
 		.data = (ulong)&bmips_cpu_bcm6358,

drivers/ram/bmips_ram.c

@@ -14,6 +14,16 @@
 #include <asm/io.h>
 #include <dm/device.h>
 
+#define SDRAM_CFG_REG		0x0
+#define SDRAM_CFG_COL_SHIFT	4
+#define SDRAM_CFG_COL_MASK	(0x3 << SDRAM_CFG_COL_SHIFT)
+#define SDRAM_CFG_ROW_SHIFT	6
+#define SDRAM_CFG_ROW_MASK	(0x3 << SDRAM_CFG_ROW_SHIFT)
+#define SDRAM_CFG_32B_SHIFT	10
+#define SDRAM_CFG_32B_MASK	(1 << SDRAM_CFG_32B_SHIFT)
+#define SDRAM_CFG_BANK_SHIFT	13
+#define SDRAM_CFG_BANK_MASK	(1 << SDRAM_CFG_BANK_SHIFT)
+
 #define MEMC_CFG_REG		0x4
 #define MEMC_CFG_32B_SHIFT	1
 #define MEMC_CFG_32B_MASK	(1 << MEMC_CFG_32B_SHIFT)
@@ -40,24 +50,41 @@ static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
 	return readl_be(priv->regs + DDR_CSEND_REG) << 24;
 }
 
+static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
+			     unsigned int is_32b, unsigned int banks)
+{
+	rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */
+	cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */
+	is_32b += 1;
+
+	return 1 << (cols + rows + is_32b + banks);
+}
+
+static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv)
+{
+	unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0;
+	u32 val;
+
+	val = readl_be(priv->regs + SDRAM_CFG_REG);
+	rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
+	cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
+	is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
+	banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
+
+	return bmips_dram_size(cols, rows, is_32b, banks);
+}
+
 static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
 {
-	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+	unsigned int cols = 0, rows = 0, is_32b = 0;
 	u32 val;
 
 	val = readl_be(priv->regs + MEMC_CFG_REG);
 	rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 	cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
-	is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
-	banks = 2;
+	is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 
-	/* 0 => 11 address bits ... 2 => 13 address bits */
-	rows += 11;
-
-	/* 0 => 8 address bits ... 2 => 10 address bits */
-	cols += 8;
-
-	return 1 << (cols + rows + (is_32bits + 1) + banks);
+	return bmips_dram_size(cols, rows, is_32b, 2);
 }
 
 static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
@@ -79,6 +106,10 @@ static const struct bmips_ram_hw bmips_ram_bcm6328 = {
 	.get_ram_size = bcm6328_get_ram_size,
 };
 
+static const struct bmips_ram_hw bmips_ram_bcm6338 = {
+	.get_ram_size = bcm6338_get_ram_size,
+};
+
 static const struct bmips_ram_hw bmips_ram_bcm6358 = {
 	.get_ram_size = bcm6358_get_ram_size,
 };
@@ -87,6 +118,9 @@ static const struct udevice_id bmips_ram_ids[] = {
 	{
 		.compatible = "brcm,bcm6328-mc",
 		.data = (ulong)&bmips_ram_bcm6328,
+	}, {
+		.compatible = "brcm,bcm6338-mc",
+		.data = (ulong)&bmips_ram_bcm6338,
 	}, {
 		.compatible = "brcm,bcm6358-mc",
 		.data = (ulong)&bmips_ram_bcm6358,

drivers/serial/serial_bcm6345.c

@@ -141,6 +141,8 @@ static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
 			UART_CTL_RXTIMEOUT_5 |
 			/* set 8 bits/symbol */
 			UART_CTL_BITSPERSYM_8 |
+			/* set 1 stop bit */
+			UART_CTL_STOPBITS_1 |
 			/* set parity to even */
 			UART_CTL_RXPAREVEN_MASK |
 			UART_CTL_TXPAREVEN_MASK);
@@ -155,11 +157,11 @@ static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
 			UART_FIFO_CFG_TX_4);
 
 	/* set baud rate */
-	val = (clk / baudrate) / 16;
+	val = ((clk / baudrate) >> 4);
 	if (val & 0x1)
-		val = val;
+		val = (val >> 1);
 	else
-		val = val / 2 - 1;
+		val = (val >> 1) - 1;
 	writel_be(val, base + UART_BAUD_REG);
 
 	/* clear interrupts */
@@ -241,7 +243,7 @@ static int bcm6345_serial_probe(struct udevice *dev)
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret < 0)
 		return ret;
-	priv->uartclk = clk_get_rate(&clk) / 2;
+	priv->uartclk = clk_get_rate(&clk);
 	clk_free(&clk);
 
 	/* initialize serial */

drivers/sysreset/Kconfig

@@ -31,4 +31,10 @@ config SYSRESET_SYSCON
 	help
 	  Reboot support for generic SYSCON mapped register reset.
 
+config SYSRESET_WATCHDOG
+	bool "Enable support for watchdog reboot driver"
+	select WDT
+	help
+	  Reboot support for generic watchdog reset.
+
 endmenu

drivers/sysreset/Makefile

@@ -7,6 +7,7 @@
 obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
 obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
 obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
+obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o

drivers/sysreset/sysreset_watchdog.c

@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <wdt.h>
+
+struct wdt_reboot_priv {
+	struct udevice *wdt;
+};
+
+static int wdt_reboot_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct wdt_reboot_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = wdt_expire_now(priv->wdt, 0);
+	if (ret)
+		return ret;
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops wdt_reboot_ops = {
+	.request = wdt_reboot_request,
+};
+
+int wdt_reboot_probe(struct udevice *dev)
+{
+	struct wdt_reboot_priv *priv = dev_get_priv(dev);
+	int err;
+
+	err = uclass_get_device_by_phandle(UCLASS_WDT, dev,
+					   "wdt", &priv->wdt);
+	if (err) {
+		error("unable to find wdt device\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id wdt_reboot_ids[] = {
+	{ .compatible = "wdt-reboot" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(wdt_reboot) = {
+	.name = "wdt_reboot",
+	.id = UCLASS_SYSRESET,
+	.of_match = wdt_reboot_ids,
+	.ops = &wdt_reboot_ops,
+	.priv_auto_alloc_size = sizeof(struct wdt_reboot_priv),
+	.probe = wdt_reboot_probe,
+};

drivers/watchdog/Kconfig

@@ -54,4 +54,12 @@ config WDT_ASPEED
 	  It currently does not support Boot Flash Addressing Mode Detection or
 	  Second Boot.
 
+config WDT_BCM6345
+	bool "BCM6345 watchdog timer support"
+	depends on WDT && ARCH_BMIPS
+	help
+	  Select this to enable watchdog timer for BCM6345 SoCs.
+	  The watchdog timer is stopped when initialized.
+	  It performs full SoC reset.
+
 endmenu

drivers/watchdog/Makefile

@@ -18,4 +18,5 @@ obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o
 obj-$(CONFIG_WDT) += wdt-uclass.o
 obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
 obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
+obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
 obj-$(CONFIG_BCM2835_WDT)       += bcm2835_wdt.o

drivers/watchdog/bcm6345_wdt.c

@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/watchdog/bcm63xx_wdt.c:
+ *	Copyright (C) 2007 Miguel Gaio <miguel.gaio@efixo.com>
+ *	Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <wdt.h>
+#include <asm/io.h>
+
+/* WDT Value register */
+#define WDT_VAL_REG		0x0
+#define WDT_VAL_MIN		0x00000002
+#define WDT_VAL_MAX		0xfffffffe
+
+/* WDT Control register */
+#define WDT_CTL_REG		0x4
+#define WDT_CTL_START1_MASK	0x0000ff00
+#define WDT_CTL_START2_MASK	0x000000ff
+#define WDT_CTL_STOP1_MASK	0x0000ee00
+#define WDT_CTL_STOP2_MASK	0x000000ee
+
+struct bcm6345_wdt_priv {
+	void __iomem *regs;
+};
+
+static int bcm6345_wdt_reset(struct udevice *dev)
+{
+	struct bcm6345_wdt_priv *priv = dev_get_priv(dev);
+
+	writel_be(WDT_CTL_START1_MASK, priv->regs + WDT_CTL_REG);
+	writel_be(WDT_CTL_START2_MASK, priv->regs + WDT_CTL_REG);
+
+	return 0;
+}
+
+static int bcm6345_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+	struct bcm6345_wdt_priv *priv = dev_get_priv(dev);
+
+	if (timeout < WDT_VAL_MIN) {
+		debug("watchdog won't fire with less than 2 ticks\n");
+		timeout = WDT_VAL_MIN;
+	} else if (timeout > WDT_VAL_MAX) {
+		debug("maximum watchdog timeout exceeded\n");
+		timeout = WDT_VAL_MAX;
+	}
+
+	writel_be(timeout, priv->regs + WDT_VAL_REG);
+
+	return bcm6345_wdt_reset(dev);
+}
+
+static int bcm6345_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+	return bcm6345_wdt_start(dev, WDT_VAL_MIN, flags);
+}
+
+static int bcm6345_wdt_stop(struct udevice *dev)
+{
+	struct bcm6345_wdt_priv *priv = dev_get_priv(dev);
+
+	writel_be(WDT_CTL_STOP1_MASK, priv->regs + WDT_CTL_REG);
+	writel_be(WDT_CTL_STOP2_MASK, priv->regs + WDT_CTL_REG);
+
+	return 0;
+}
+
+static const struct wdt_ops bcm6345_wdt_ops = {
+	.expire_now = bcm6345_wdt_expire_now,
+	.reset = bcm6345_wdt_reset,
+	.start = bcm6345_wdt_start,
+	.stop = bcm6345_wdt_stop,
+};
+
+static const struct udevice_id bcm6345_wdt_ids[] = {
+	{ .compatible = "brcm,bcm6345-wdt" },
+	{ /* sentinel */ }
+};
+
+static int bcm6345_wdt_probe(struct udevice *dev)
+{
+	struct bcm6345_wdt_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+	fdt_size_t size;
+
+	addr = dev_get_addr_size_index(dev, 0, &size);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = ioremap(addr, size);
+
+	bcm6345_wdt_stop(dev);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(wdt_bcm6345) = {
+	.name = "wdt_bcm6345",
+	.id = UCLASS_WDT,
+	.of_match = bcm6345_wdt_ids,
+	.ops = &bcm6345_wdt_ops,
+	.priv_auto_alloc_size = sizeof(struct bcm6345_wdt_priv),
+	.probe = bcm6345_wdt_probe,
+};

include/configs/bmips_bcm3380.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM3380_H
+#define __CONFIG_BMIPS_BCM3380_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	166500000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	0x2000
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM3380_H */

include/configs/bmips_bcm6338.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6338_H
+#define __CONFIG_BMIPS_BCM6338_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	120000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	0x2000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0xbfc00000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#endif /* __CONFIG_BMIPS_BCM6338_H */

include/configs/bmips_bcm6348.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6348_H
+#define __CONFIG_BMIPS_BCM6348_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	128000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	0x2000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0xbfc00000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#endif /* __CONFIG_BMIPS_BCM6348_H */

include/configs/bmips_common.h

@@ -7,6 +7,10 @@
 #ifndef __CONFIG_BMIPS_COMMON_H
 #define __CONFIG_BMIPS_COMMON_H
 
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+
 /* RAM */
 #define CONFIG_SYS_MEMTEST_START	0xa0000000
 #define CONFIG_SYS_MEMTEST_END		0xa2000000

include/configs/comtrend_ct5361.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6348.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1

include/configs/netgear_cg3100d.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm3380.h>
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP

include/configs/sagem_f@st1704.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6338.h>
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP

include/dt-bindings/clock/bcm3380-clock.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from Broadcom GPL Source Code:
+ *	Copyright (C) Broadcom Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM3380_H
+#define __DT_BINDINGS_CLOCK_BCM3380_H
+
+#define BCM3380_CLK0_DDR	0
+#define BCM3380_CLK0_FPM	1
+#define BCM3380_CLK0_CRYPTO	2
+#define BCM3380_CLK0_EPHY	3
+#define BCM3380_CLK0_PCIE	16
+#define BCM3380_CLK0_SPI	17
+#define BCM3380_CLK0_ENET0	18
+#define BCM3380_CLK0_ENET1	19
+#define BCM3380_CLK0_PCM	27
+
+#endif /* __DT_BINDINGS_CLOCK_BCM3380_H */

include/dt-bindings/clock/bcm6338-clock.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6338_H
+#define __DT_BINDINGS_CLOCK_BCM6338_H
+
+#define BCM6338_CLK_ADSL	0
+#define BCM6338_CLK_MPI		1
+#define BCM6338_CLK_SDRAM	2
+#define BCM6338_CLK_ENET	4
+#define BCM6338_CLK_SAR		5
+#define BCM6338_CLK_SPI		9
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6338_H */

include/dt-bindings/clock/bcm6348-clock.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6348_H
+#define __DT_BINDINGS_CLOCK_BCM6348_H
+
+#define BCM6348_CLK_ADSL	0
+#define BCM6348_CLK_MPI		1
+#define BCM6348_CLK_SDRAM	2
+#define BCM6348_CLK_M2M		3
+#define BCM6348_CLK_ENET	4
+#define BCM6348_CLK_SAR		5
+#define BCM6348_CLK_USBS	6
+#define BCM6348_CLK_USBH	8
+#define BCM6348_CLK_SPI		9
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */

include/dt-bindings/reset/bcm3380-reset.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from Broadcom GPL Source Code:
+ *	Copyright (C) Broadcom Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM3380_H
+#define __DT_BINDINGS_RESET_BCM3380_H
+
+#define BCM3380_RST0_SPI	0
+#define BCM3380_RST0_PCM	13
+
+#endif /* __DT_BINDINGS_RESET_BCM3380_H */

include/dt-bindings/reset/bcm6338-reset.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6338_H
+#define __DT_BINDINGS_RESET_BCM6338_H
+
+#define BCM6338_RST_SPI		0
+#define BCM6338_RST_ENET	2
+#define BCM6338_RST_USBH	3
+#define BCM6338_RST_USBS	4
+#define BCM6338_RST_ADSL	5
+#define BCM6338_RST_DMAMEM	6
+#define BCM6338_RST_SAR		7
+#define BCM6338_RST_ACLC	8
+#define BCM6338_RST_ADSL_MIPS	10
+
+#endif /* __DT_BINDINGS_RESET_BCM6338_H */

include/dt-bindings/reset/bcm6348-reset.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6348_H
+#define __DT_BINDINGS_RESET_BCM6348_H
+
+#define BCM6348_RST_SPI		0
+#define BCM6348_RST_ENET	2
+#define BCM6348_RST_USBH	3
+#define BCM6348_RST_USBS	4
+#define BCM6348_RST_ADSL	5
+#define BCM6348_RST_DMAMEM	6
+#define BCM6348_RST_SAR		7
+#define BCM6348_RST_ACLC	8
+#define BCM6348_RST_ADSL_MIPS	10
+
+#endif /* __DT_BINDINGS_RESET_BCM6348_H */