From a1932ece70e1441b169650d475d7814920a94c27 Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Thu, 19 Aug 2021 11:39:01 +0530 Subject: [PATCH 01/62] drivers: ddr: util.c: Fix divide by zero issue Fix possible divide by zero issue in get_memory_clk_period_ps by adding a check Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- drivers/ddr/fsl/util.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index ac4f8d2732..43cb01804b 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -75,10 +76,13 @@ unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num) /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ unsigned long long rem, mclk_ps = ULL_2E12; - - /* Now perform the big divide, the result fits in 32-bits */ - rem = do_div(mclk_ps, data_rate); - result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; + if (data_rate) { + /* Now perform the big divide, the result fits in 32-bits */ + rem = do_div(mclk_ps, data_rate); + result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; + } else { + result = 0; + } return result; } From f5a37b02b0830f984518f2348ad6f3784516f130 Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Thu, 19 Aug 2021 11:39:02 +0530 Subject: [PATCH 02/62] drivers: ddr: fsl_ddr_gen4.c: Fix divide by zero issue Fix possible divide by zero issue in fsl_ddr_set_memctl_regs by adding an if check Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- drivers/ddr/fsl/fsl_ddr_gen4.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index e43c680154..89cb4d352e 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2020 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -57,7 +58,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, struct ccsr_ddr __iomem *ddr; u32 temp32; u32 total_gb_size_per_controller; - int timeout; + int timeout = 0; + int ddr_freq_for_timeout = 0; int mod_bnds = 0; #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 @@ -511,8 +513,14 @@ step2: */ bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) >> SDRAM_CFG_DBW_SHIFT); - timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / - (get_ddr_freq(ctrl_num) >> 20)) << 2; + ddr_freq_for_timeout = (get_ddr_freq(ctrl_num) >> 20) << 2; + if (ddr_freq_for_timeout) { + timeout = ((total_gb_size_per_controller << + (6 - bus_width)) * 100 / + ddr_freq_for_timeout); + } else { + debug("Error in getting timeout.\n"); + } total_gb_size_per_controller >>= 4; /* shift down to gb size */ debug("total %d GB\n", total_gb_size_per_controller); debug("Need to wait up to %d * 10ms\n", timeout); From 71b255b6575b8e859ffddc880cce3c7606c7abca Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Thu, 19 Aug 2021 11:39:03 +0530 Subject: [PATCH 03/62] drivers: ddr: main.c: Fix Bad Shift operator issue Fix Bad Shift operator issue in step_to_string function by adding an if check Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- drivers/ddr/fsl/main.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 8e147160b9..f389e5ef95 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ /* @@ -297,9 +298,13 @@ const char * step_to_string(unsigned int step) { unsigned int s = __ilog2(step); - if ((1 << s) != step) - return step_string_tbl[7]; - + if (s <= 31) { + if ((1 << s) != step) + return step_string_tbl[7]; + } else { + if ((1 << (s - 32)) != step) + return step_string_tbl[7]; + } if (s >= ARRAY_SIZE(step_string_tbl)) { printf("Error for the step in %s\n", __func__); s = 0; From 3c922ce99cc0c7b1f2f5615a2e4216dfdbb175c4 Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Thu, 19 Aug 2021 12:37:31 +0530 Subject: [PATCH 04/62] board: freescale: t104xrdb: Set popts->cpo_sample to 0x54 for DDR3 Set popts->cpo_sample to 0x54 in t104xrdb/ddr.c to optimize cpo Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- board/freescale/t104xrdb/ddr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 8351f7ce9d..539a36d2a9 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -83,6 +84,7 @@ found: /* optimize cpo for erratum A-009942 */ popts->cpo_sample = 0x59; #else + popts->cpo_sample = 0x54; popts->half_strength_driver_enable = 0; #endif /* From b2a6ccd4dd5c48201fdc2aeb88ceda34e1be36c0 Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Thu, 26 Aug 2021 16:09:24 +0530 Subject: [PATCH 05/62] lx2162a : Rename emmc boot command variable Rename emmc_bootcmd environment variable to sd2_bootcmd to fix emmc boot on lx2162aqds board. Signed-off-by: Meenakshi Aggarwal Reviewed-by: Priyanka Jain --- include/configs/lx2162aqds.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index 7fa3c25630..f1b4e1cc4d 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ #ifndef __LX2162_QDS_H @@ -60,7 +60,7 @@ u8 qixis_esdhc_detect_quirk(void); "$kernelhdr_addr_sd $kernelhdr_size_sd " \ " && esbc_validate ${kernelheader_addr_r};" \ "bootm $load_addr#$BOARD\0" \ - "emmc_bootcmd=echo Trying load from emmc card..;" \ + "sd2_bootcmd=echo Trying load from emmc card..;" \ "mmc dev 1; mmcinfo; mmc read $load_addr " \ "$kernel_addr_sd $kernel_size_sd ;" \ "env exists secureboot && mmc read $kernelheader_addr_r "\ From 2a98944b4347bb48cc378c1fc620c919b0769ec9 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Mon, 6 Sep 2021 16:32:56 +0200 Subject: [PATCH 06/62] armv8: fsl-layerscape: Erratum A010315 needs PCIE support Disabling PCIE support currently lead to a crash because the code for erratum A010315 is still run. Add a conditional to only select CONFIG_SYS_FSL_ERRATUM_A010315 when CONFIG_PCIE_LAYERSCAPE is enabled. Signed-off-by: Alban Bedel Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 1e166c73e4..c0223d2dbc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -10,7 +10,7 @@ config ARCH_LS1012A select SYS_HAS_SERDES select SYS_FSL_DDR_BE select SYS_FSL_MMDC - select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 @@ -77,7 +77,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009942 if !TFABOOT - select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 From c0e0cf4989d1de847c4b2ce1927ea7a121351801 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Wed, 15 Sep 2021 15:34:12 +0530 Subject: [PATCH 07/62] configs: lx2162a: Enable CONFIG_SPI_FLASH_MT35XU for lx2162a-qds LX2162A-QDS has micron mt35xu512aba flash which requires flag CONFIG_SPI_FLASH_MT35XU on to probe flash successfully. Signed-off-by: Kuldeep Singh Reviewed-by: Wasim Khan Tested-by: Wasim Khan Reviewed-by: Priyanka Jain --- configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2162aqds_tfa_defconfig | 1 + configs/lx2162aqds_tfa_verified_boot_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index 3d5182a846..6c5abc82a2 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -62,6 +62,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y CONFIG_SPI_FLASH_SST=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index 377f4f5698..feaea633a7 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -70,6 +70,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y CONFIG_SPI_FLASH_SST=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index 7d7a955ec1..930018540b 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -71,6 +71,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y CONFIG_SPI_FLASH_SST=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y From bd2a4eb977232c7062489251cdb5a36a99757fc1 Mon Sep 17 00:00:00 2001 From: Kshitiz Varshney Date: Sun, 19 Sep 2021 17:09:53 +0200 Subject: [PATCH 08/62] board: fsl_validate: Fix Double free Issue Remove Double free issue from calc_img_key_hash() and calc_esbchdr_esbc_hash() function. Verified the secure boot changes using lx2162aqds board. Signed-off-by: Kshitiz Varshney Reviewed-by: Priyanka Jain --- board/freescale/common/fsl_validate.c | 28 ++++++--------------------- drivers/crypto/fsl/fsl_hash.c | 14 +++++++------- 2 files changed, 13 insertions(+), 29 deletions(-) diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index c90afe2e21..34875d0b8f 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -499,12 +499,8 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img) return ret; ret = algo->hash_init(algo, &ctx); - if (ret) { - if (ctx) - free(ctx); + if (ret) return ret; - } - /* Update hash for ESBC key */ #ifdef CONFIG_KEY_REVOCATION if (check_srk(img)) { @@ -519,15 +515,12 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img) img->img_key, img->key_len, 1); if (ret) return ret; - /* Copy hash at destination buffer */ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); if (ret) { - if (ctx) - free(ctx); + free(ctx); return ret; } - for (i = 0; i < SHA256_BYTES; i++) img->img_key_hash[i] = hash_val[i]; @@ -554,18 +547,14 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) ret = algo->hash_init(algo, &ctx); /* Copy hash at destination buffer */ - if (ret) { - free(ctx); + if (ret) return ret; - } /* Update hash for CSF Header */ ret = algo->hash_update(algo, ctx, (u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0); - if (ret) { - free(ctx); + if (ret) return ret; - } /* Update the hash with that of srk table if srk flag is 1 * If IE Table is selected, key is not added in the hash @@ -592,22 +581,17 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) key_hash = 1; } #endif - if (ret) { - free(ctx); + if (ret) return ret; - } if (!key_hash) { free(ctx); return ERROR_KEY_TABLE_NOT_FOUND; } - /* Update hash for actual Image */ ret = algo->hash_update(algo, ctx, (u8 *)(*(img->img_addr_ptr)), img->img_size, 1); - if (ret) { - free(ctx); + if (ret) return ret; - } /* Copy hash at destination buffer */ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index 8b5c26db07..8039473012 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. - * + * Copyright 2021 NXP */ #include @@ -120,8 +120,8 @@ static int caam_hash_update(void *hash_ctx, const void *buf, * Perform progressive hashing on the given buffer and copy hash at * destination buffer * - * The context is freed after completion of hash operation. - * + * The context is freed after successful completion of hash operation. + * In case of failure, context is not freed. * @hash_ctx: Pointer to the context for hashing * @dest_buf: Pointer to the destination buffer where hash is to be copied * @size: Size of the buffer being hashed @@ -136,7 +136,6 @@ static int caam_hash_finish(void *hash_ctx, void *dest_buf, int i = 0, ret = 0; if (size < driver_hash[caam_algo].digestsize) { - free(ctx); return -EINVAL; } @@ -152,11 +151,12 @@ static int caam_hash_finish(void *hash_ctx, void *dest_buf, ret = run_descriptor_jr(ctx->sha_desc); - if (ret) + if (ret) { debug("Error %x\n", ret); - else + return ret; + } else { memcpy(dest_buf, ctx->hash, sizeof(ctx->hash)); - + } free(ctx); return ret; } From 0ecf45f5bd038a2610e81491d4f9fb47c2b5c71d Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 20 Sep 2021 15:45:33 +0200 Subject: [PATCH 09/62] board: freescale: lx216x : increase fdt blob size Increase fdt blob size for lx2160 and lx2162 series to fix below errors/warnings during device tree fixup. Unable to update property /soc/spi@2100000:status, err=FDT_ERR_NOSPACE Unable to update property /soc/spi@2110000:status, err=FDT_ERR_NOSPACE Unable to update property /soc/spi@2120000:status, err=FDT_ERR_NOSPACE WARNING: could not set reg FDT_ERR_NOSPACE. WARNING unable to set iommus: FDT_ERR_NOSPACE Signed-off-by: Wasim Khan Reviewed-by: Tom Rini Reviewed-by: Priyanka Jain --- board/freescale/lx2160a/lx2160a.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index bd5abb677a..bda665624d 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -825,10 +825,18 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 mc_memory_base = 0; u64 mc_memory_size = 0; u16 total_memory_banks; + int err; #if CONFIG_IS_ENABLED(TARGET_LX2160ARDB) u8 board_rev; #endif + err = fdt_increase_size(blob, 512); + if (err) { + printf("%s fdt_increase_size: err=%s\n", __func__, + fdt_strerror(err)); + return err; + } + ft_cpu_setup(blob, bd); fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); From 9e91bb036743e57b5fcb467c72ea426bb8776296 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 29 Sep 2021 13:39:09 +0200 Subject: [PATCH 10/62] board: sl28: enable EFI_SET_TIME support Allow EFI to actually set the time before ExitBootServices(). Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- configs/kontron_sl28_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 90e595f145..f24051ac64 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -94,3 +94,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_SET_TIME=y From d8ffd938f1903cbf5cf03d75e2306e0da8ce4ffb Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 29 Sep 2021 13:39:10 +0200 Subject: [PATCH 11/62] board: sl28: generate FIT update image Generate a FIT update image during build. The image will be called "u-boot.update" and can be used to build an EFI UpdateCapsule or during DFU mode. Although, the latter isn't supported because there is no USB OTG driver yet. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- .../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 35 +++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index b3861ed98c..a501cece69 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -15,6 +15,12 @@ }; binman: binman { + multiple-images; + }; +}; + +&binman { + u_boot_rom: u-boot-rom { filename = "u-boot.rom"; pad-byte = <0xff>; @@ -133,6 +139,31 @@ }; }; +&binman { + u-boot-update { + filename = "u-boot.update"; + + fit { + description = "FIT update image"; + + images { + u-boot-bin { + description = "U-Boot"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = <0>; /* unused */ + + blob { + filename = "u-boot.rom"; + }; + }; + }; + }; + }; +}; + #ifdef CONFIG_SL28_ENABLE_SER0_CONSOLE / { chosen { @@ -142,7 +173,7 @@ #endif #ifdef CONFIG_SL28_SPL_LOADS_ATF_BL31 -&binman { +&u_boot_rom { fit { images { bl31 { @@ -191,7 +222,7 @@ #endif #ifdef CONFIG_SL28_SPL_LOADS_OPTEE_BL32 -&binman { +&u_boot_rom { fit { images { bl32 { From ed30254ef62d1a9066a32cd3af71078646368501 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 9 Nov 2021 14:48:51 +0530 Subject: [PATCH 12/62] board: sl28: enable EFI UpdateCapsule support Enable support for update over EFI UpdateCapsule mechanism. This board doesn't support setting EFI variables after ExitBootservices(). Therefore, we are also enabling EFI_IGNORE_OSINDICATIONS. Signed-off-by: Michael Walle [Rebased] Signed-off-by: Priyanka Jain --- configs/kontron_sl28_defconfig | 6 ++++++ include/configs/kontron_sl28.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index f24051ac64..4689d44b68 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -64,6 +64,8 @@ CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_MUX=y CONFIG_MMC_HS400_SUPPORT=y @@ -95,3 +97,7 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_IGNORE_OSINDICATIONS=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 6769592101..4152851ba4 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -88,6 +88,8 @@ "envload=env import -d -b ${env_addr}\0" \ "install_rcw=source 20200000\0" \ "fdtfile=freescale/fsl-ls1028a-kontron-sl28.dtb\0" \ + "dfu_alt_info=sf 0:0=u-boot-bin raw 0x210000 0x1d0000;" \ + "u-boot-env raw 0x3e0000 0x20000\0" \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV From f06add11f073b0a6cffff6c4c3aa4c91378c035b Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Wed, 29 Sep 2021 13:39:12 +0200 Subject: [PATCH 13/62] doc: board: kontron: sl28: Reduce section levels and change title In order to add other Kontron boards to the docs alongside the existing sl28 board, we need to reduce the levels of the sections and change the title. Cc: Fabio Estevam Signed-off-by: Frieder Schrempf Acked-by: Michael Walle Reviewed-by: Priyanka Jain --- doc/board/kontron/sl28.rst | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/doc/board/kontron/sl28.rst b/doc/board/kontron/sl28.rst index e458fbc607..07431986d8 100644 --- a/doc/board/kontron/sl28.rst +++ b/doc/board/kontron/sl28.rst @@ -1,17 +1,17 @@ .. SPDX-License-Identifier: GPL-2.0+ -Summary -======= +Kontron SMARC-sAL28 +=================== The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72 processor module with an on-chip 6-port TSN switch and a 3D GPU. Quickstart -========== +---------- Compile U-Boot --------------- +^^^^^^^^^^^^^^ Configure and compile the binary:: @@ -21,7 +21,7 @@ Configure and compile the binary:: Copy u-boot.rom to a TFTP server. Install the bootloader on the board ------------------------------------ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Please note, this bootloader doesn't support the builtin watchdog (yet), therefore you have to disable it, see below. Otherwise you'll end up in @@ -36,7 +36,7 @@ disabled the builtin watchdog you might have to manually enter failsafe mode by asserting the ``FORCE_RECOV#`` line during board reset. Disable the builtin watchdog ----------------------------- +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - boot into the failsafe bootloader, either by asserting the ``FORCE_RECOV#`` line or if you still have the original bootloader @@ -53,7 +53,7 @@ Disable the builtin watchdog Useful I2C tricks -================= +----------------- The board has a board management controller which is not supported in u-boot (yet). But you can use the i2c command to access it. @@ -68,7 +68,7 @@ u-boot (yet). But you can use the i2c command to access it. Non-volatile Board Configuration Bits -===================================== +------------------------------------- The board has 16 configuration bits which are stored in the CPLD and are non-volatile. These can be changed by the `sl28 nvm` command. @@ -98,21 +98,21 @@ Please note, that if the board is in failsafe mode, the bits will have the factory defaults, ie. all bits are off. Power-On Inhibit ----------------- +^^^^^^^^^^^^^^^^ If this is set, the board doesn't automatically turn on when power is applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or use any other wake-up source such as RTC alarm or Wake-on-LAN. eMMC Boot ---------- +^^^^^^^^^ If this is set, the RCW will be fetched from the on-board eMMC at offset 1MiB. For further details, have a look at the `Reset Configuration Word Documentation`_. Watchdog --------- +^^^^^^^^ By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and 3, the user can change its mode or disable it altogether. @@ -127,21 +127,21 @@ Bit 2 Bit 3 Description ===== ===== =============================== Clock Generator Select ----------------------- +^^^^^^^^^^^^^^^^^^^^^^ The board is prepared to supply different SerDes clock speeds. But for now, only setting 0 is supported, otherwise the CPU will hang because the PLL will not lock. Clock Output Disable And Keep Devices In Reset ----------------------------------------------- +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ To safe power, the user might disable different devices and clock output of the board. It is not supported to disable the "CPU SerDes clock #2" for now, otherwise the CPU will hang because the PLL will not lock. Automatic reset of the onboard PHYs ------------------------------------ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ By default, there is no hardware reset of the onboard PHY. This is because for Wake-on-LAN, some registers have to retain their values. If you don't @@ -151,7 +151,7 @@ power-on reset. Further documentation -===================== +--------------------- - `Vendor Documentation`_ - `Reset Configuration Word Documentation`_ From cbdc4c974fbd884c40b7923d9f5f9d0d165d4268 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 29 Sep 2021 13:39:13 +0200 Subject: [PATCH 14/62] board: sl28: add update image documentation Document the update image and how to use the EFI UpdateCapsule. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- doc/board/kontron/sl28.rst | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/doc/board/kontron/sl28.rst b/doc/board/kontron/sl28.rst index 07431986d8..c7b18bed10 100644 --- a/doc/board/kontron/sl28.rst +++ b/doc/board/kontron/sl28.rst @@ -52,6 +52,21 @@ Disable the builtin watchdog - power-cycle the board +Update image +------------ + +After the build finished, there will be an update image called +u-boot.update. This can either be used in the DFU mode (which isn't +supported yet) or encapsulated in an EFI UpdateCapsule. + +To build the capsule use the following command + + $ tools/mkeficapsule -f u-boot.update -i 1 UpdateUboot + +Afterward you can copy this file to your ESP into the /EFI/UpdateCapsule/ +folder. On the next EFI boot this will automatically update your +bootloader. + Useful I2C tricks ----------------- From f5402117ade90d136349bc227a544771e112c981 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Fri, 1 Oct 2021 16:24:24 +0530 Subject: [PATCH 15/62] arm: dts: ls1088a: Update qspi node properties Remove "num-cs" property from device-tree as it is no longer used by qspi driver anymore. Also, specify status as "disabled" and enable qspi support in respective board dts files. This will also help in aligning node properties with other board properties. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1088a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 3a5a50fb83..0db02b1c23 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -99,7 +99,7 @@ reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - num-cs = <4>; + status = "disabled"; }; esdhc: esdhc@2140000 { From a48492679cb7c1ab4465af457defc3ba6dc7d4ec Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 4 Oct 2021 14:01:34 -0400 Subject: [PATCH 16/62] ppc: mpc8xx: Drop -mstring from PLATFORM_CPPFLAGS This has not been supported by toolchains for some time and has been putting out a warning. Drop this. Signed-off-by: Tom Rini Reviewed-by: Thomas Huth Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc8xx/config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc8xx/config.mk b/arch/powerpc/cpu/mpc8xx/config.mk index 00b7ed50a9..5a64665a61 100644 --- a/arch/powerpc/cpu/mpc8xx/config.mk +++ b/arch/powerpc/cpu/mpc8xx/config.mk @@ -3,4 +3,4 @@ # (C) Copyright 2000-2010 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -PLATFORM_CPPFLAGS += -mstring -mcpu=860 -msoft-float +PLATFORM_CPPFLAGS += -mcpu=860 -msoft-float From ed06772a605db6a3eb87941fa0aacc57ac879598 Mon Sep 17 00:00:00 2001 From: Cosmin-Florin Aluchenesei Date: Thu, 7 Oct 2021 13:07:44 +0300 Subject: [PATCH 17/62] drivers: net: fsl-mc: add a command which dumps the MC log Extended fsl_mc command adding an extra option dump_log Signed-off-by: Cosmin-Florin Aluchenesei Reviewed-by: Priyanka Jain --- drivers/net/fsl-mc/mc.c | 89 ++++++++++++++++++++++++++++++++++++++++- include/fsl-mc/fsl_mc.h | 9 +++++ 2 files changed, 97 insertions(+), 1 deletion(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index d52c986d4b..bc1c31d467 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -38,6 +39,16 @@ #define MC_BOOT_ENV_VAR "mcinitcmd" #define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024) +#define MC_BUFFER_SIZE (1024 * 1024 * 16) +#define MAGIC_MC 0x4d430100 +#define MC_FW_ADDR_MASK_LOW 0xE0000000 +#define MC_FW_ADDR_MASK_HIGH 0X1FFFF +#define MC_STRUCT_BUFFER_OFFSET 0x01000000 +#define MC_OFFSET_DELTA MC_STRUCT_BUFFER_OFFSET + +#define LOG_HEADER_FLAG_BUFFER_WRAPAROUND 0x80000000 +#define LAST_BYTE(a) ((a) & ~(LOG_HEADER_FLAG_BUFFER_WRAPAROUND)) + DECLARE_GLOBAL_DATA_PTR; static int mc_memset_resv_ram; static struct mc_version mc_ver_info; @@ -1773,11 +1784,78 @@ err: return err; } +static void print_k_bytes(const void *buf, ssize_t *size) +{ + while (*size > 0) { + int count = printf("%s", (char *)buf); + + buf += count; + *size -= count; + } +} + +static void mc_dump_log(void) +{ + struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; + u64 high = in_le64(&mc_ccsr_regs->reg_mcfbahr) & MC_FW_ADDR_MASK_HIGH; + u64 low = in_le64(&mc_ccsr_regs->reg_mcfbalr) & MC_FW_ADDR_MASK_LOW; + u32 buf_len, wrapped, last_byte, magic, buf_start; + u64 mc_addr = (high << 32) | low; + struct log_header *header; + ssize_t size, bytes_end; + const void *end_of_data; + const void *map_addr; + const void *end_addr; + const void *cur_ptr; + const void *buf; + + map_addr = map_sysmem(mc_addr + MC_STRUCT_BUFFER_OFFSET, + MC_BUFFER_SIZE); + header = (struct log_header *)map_addr; + last_byte = in_le32(&header->last_byte); + buf_len = in_le32(&header->buf_length); + magic = in_le32(&header->magic_word); + buf_start = in_le32(&header->buf_start); + buf = map_addr + buf_start - MC_OFFSET_DELTA; + end_addr = buf + buf_len; + wrapped = last_byte & LOG_HEADER_FLAG_BUFFER_WRAPAROUND; + end_of_data = buf + LAST_BYTE(last_byte); + + if (magic != MAGIC_MC) { + puts("Magic number is not valid\n"); + printf("expected = %08x, received = %08x\n", MAGIC_MC, magic); + goto err_magic; + } + + if (wrapped && end_of_data != end_addr) + cur_ptr = end_of_data + 1; + else + cur_ptr = buf; + + if (cur_ptr <= end_of_data) + size = end_of_data - cur_ptr; + else + size = (end_addr - cur_ptr) + (end_of_data - buf); + + bytes_end = end_addr - cur_ptr; + if (size > bytes_end) { + print_k_bytes(cur_ptr, &bytes_end); + + cur_ptr = buf; + size -= bytes_end; + } + + print_k_bytes(buf, &size); + +err_magic: + unmap_sysmem(map_addr); +} + static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { int err = 0; - if (argc < 3) + if (argc < 2) goto usage; switch (argv[1][0]) { @@ -1787,6 +1865,8 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET u64 aiop_fw_addr; #endif + if (argc < 3) + goto usage; sub_cmd = argv[2][0]; @@ -1918,6 +1998,12 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, } break; } + case 'd': + if (argc > 2) + goto usage; + + mc_dump_log(); + break; default: printf("Invalid option: %s\n", argv[1]); goto usage; @@ -1936,6 +2022,7 @@ U_BOOT_CMD( "fsl_mc lazyapply DPL [DPL_addr] - Apply DPL file on exit\n" "fsl_mc apply spb [spb_addr] - Apply SPB Soft Parser Blob\n" "fsl_mc start aiop [FW_addr] - Start AIOP\n" + "fsl_mc dump_log - Dump MC Log\n" ); void mc_env_boot(void) diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index a8b072ad7c..07a46a4a1b 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2014 Freescale Semiconductor + * Copyright 2021 NXP */ #ifndef __FSL_MC_H__ @@ -52,6 +53,14 @@ struct mc_ccsr_registers { u32 reg_error[]; }; +struct log_header { + u32 magic_word; + char reserved[4]; + u32 buf_start; + u32 buf_length; + u32 last_byte; +}; + void fdt_fsl_mc_fixup_iommu_map_entry(void *blob); int get_mc_boot_status(void); int get_dpl_apply_status(void); From 38ce95a1c6fdc7a2a8cc177202cd421beef56427 Mon Sep 17 00:00:00 2001 From: Maninder Singh Date: Sun, 10 Oct 2021 09:12:16 -0700 Subject: [PATCH 18/62] drivers: ddr: lc_common_dimm_params.c : Fix Divison by zero issue Adds check for memory clock variable before calculating caslat_actual. Set mclk_ps to slowest DIMM supported if mclk_ps is found zero. Signed-off-by: Maninder Singh Reviewed-by: Priyanka Jain --- drivers/ddr/fsl/lc_common_dimm_params.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index d299d763db..d738ae3a7c 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright 2008-2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP Semiconductor + * Copyright 2017-2021 NXP Semiconductor */ #include @@ -23,7 +23,7 @@ compute_cas_latency(const unsigned int ctrl_num, unsigned int caslat_actual; unsigned int retry = 16; unsigned int tmp = ~0; - const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); + unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); #ifdef CONFIG_SYS_FSL_DDR3 const unsigned int taamax = 20000; #else @@ -37,6 +37,12 @@ compute_cas_latency(const unsigned int ctrl_num, } common_caslat = tmp; + if (!mclk_ps) { + printf("DDR clock (MCLK cycle was 0 ps), So setting it to slowest DIMM(s) (tCKmin %u ps).\n", + outpdimm->tckmin_x_ps); + mclk_ps = outpdimm->tckmin_x_ps; + } + /* validate if the memory clk is in the range of dimms */ if (mclk_ps < outpdimm->tckmin_x_ps) { printf("DDR clock (MCLK cycle %u ps) is faster than " From fb5ff321d0083c49c4cd80b4abf647248bb0426a Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:00 +0200 Subject: [PATCH 19/62] armv8: ls1028a: use the official compatible string for the GPU There is no "fsl,ls1028a-gpu" compatible string. It is solely for the proprietary driver which will never be open source. Lately, linux gained support for the open source etnaviv driver for the GPU (although there is still support for the DisplayPort PHY missing to get actual graphics output). Thus, instead of supporting some proprietary driver, switch over to the open source one, which also have an official device tree binding. Cc: Andy Tang Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 6eb7f9c214..4ec0dbf516 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -427,7 +427,7 @@ static void fdt_disable_multimedia(void *blob, unsigned int svr) fdt_status_disabled(blob, off); /* Disable GPU node */ - off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu"); + off = fdt_node_offset_by_compatible(blob, -1, "vivante,gc"); if (off != -FDT_ERR_NOTFOUND) fdt_status_disabled(blob, off); } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c index 49df8b3790..86a49b152e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -18,7 +18,7 @@ struct icid_id_table icid_tbl[] = { SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID), SET_EDMA_ICID(FSL_EDMA_STREAM_ID), SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID), - SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID), + SET_GPU_ICID("vivante,gc", FSL_GPU_STREAM_ID), SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID), #ifdef CONFIG_FSL_CAAM SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), From d89fa39227896507e2e8f89e8742cdab22d7c965 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:01 +0200 Subject: [PATCH 20/62] arm: dts: ls1028a: remove /memory node This node is some hodgepodge between the ddr controller node at SoC offset 0x1080000 and some static memory size of 2GiB. Remove this bogus node because it doesn't seem to be used at all. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Tested-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 53b052ed32..48f70c10d9 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -28,12 +28,6 @@ clocks = <&sysclk>; }; - memory@01080000 { - device_type = "memory"; - reg = <0x00000000 0x01080000 0 0x80000000>; - /* DRAM space - 1, size : 2 GB DRAM */ - }; - gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ From 541deeea59c38333ac99646103b7a7a1718a2ef8 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:02 +0200 Subject: [PATCH 21/62] arm: dts: ls1028a-{rdb, qds}: remove dm-pre-reloc property Nowadays, both boards boot using the TF-A BL1/BL2 and SPL isn't used at all. The property is not needed, remove it. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a-qds.dtsi | 1 - arch/arm/dts/fsl-ls1028a-rdb.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index 69632fa796..335d7b1e4c 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -130,7 +130,6 @@ &i2c0 { status = "okay"; - u-boot,dm-pre-reloc; fpga@66 { #address-cells = <1>; diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index 82a8c0a0cd..708182f65c 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -61,7 +61,6 @@ &i2c0 { status = "okay"; - u-boot,dm-pre-reloc; i2c-mux@77 { From cd80d5d924cf070b1ae35a43ed78d1054eedef00 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:03 +0200 Subject: [PATCH 22/62] arm: dts: ls1028a: add an empty /soc To keep the device tree similar to the linux kernel one, we need to move all CCSR related devices into the /soc node. To keep the patches easy to review, we initially add an empty /soc node and populate it piece by piece. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 4 ++++ arch/arm/dts/fsl-ls1028a.dtsi | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index a501cece69..0b1afe37e9 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -297,6 +297,10 @@ u-boot,dm-pre-reloc; }; +&soc { + u-boot,dm-pre-reloc; +}; + &sysclk { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 48f70c10d9..1f562cfdad 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -478,4 +478,11 @@ compatible = "arm,sp805-wdt"; reg = <0x0 0xc000000 0x0 0x1000>; }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; }; From 9b38ba584670325a255d7f227a78e323d80c647b Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:04 +0200 Subject: [PATCH 23/62] arm: dts: ls1028a: move the clockgen node into /soc Populate the /soc node with the first device node. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 1f562cfdad..54f97014be 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -21,13 +21,6 @@ clock-output-names = "sysclk"; }; - clockgen: clocking@1300000 { - compatible = "fsl,ls1028a-clockgen"; - reg = <0x0 0x1300000 0x0 0xa0000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ @@ -484,5 +477,12 @@ #address-cells = <2>; #size-cells = <2>; ranges; + + clockgen: clocking@1300000 { + compatible = "fsl,ls1028a-clockgen"; + reg = <0x0 0x1300000 0x0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; }; }; From fb19c6b15999cc9a2278fe1eaf62dc0fcae6d4b9 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:05 +0200 Subject: [PATCH 24/62] arm: dts: ls1028a: move I2C controller nodes into /soc While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- .../dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi | 2 +- .../dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi | 2 +- .../dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 8 +- .../dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 4 +- .../dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi | 2 +- .../fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi | 8 +- .../dts/fsl-ls1028a-qds-9999-sch-24801.dtsi | 8 +- .../fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi | 8 +- .../fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi | 8 +- .../dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 2 +- .../dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 2 +- arch/arm/dts/fsl-ls1028a.dtsi | 176 +++++++++--------- 12 files changed, 115 insertions(+), 115 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi index 4063d9a114..1f13cf80e6 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi @@ -16,5 +16,5 @@ &enetc0 { status = "okay"; phy-mode = "usxgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi index 548ab2ba65..10375b2751 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi @@ -15,5 +15,5 @@ &enetc0 { status = "okay"; phy-mode = "2500base-x"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi index 3991fb793f..f18cb39f21 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi @@ -31,25 +31,25 @@ &mscc_felix_port0 { status = "okay"; phy-mode = "2500base-x"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>; }; &mscc_felix_port1 { status = "okay"; phy-mode = "2500base-x"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>; }; &mscc_felix_port2 { status = "okay"; phy-mode = "2500base-x"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; }; &mscc_felix_port3 { status = "okay"; phy-mode = "2500base-x"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; }; &mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi index d68c8c2be0..f6561a89eb 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi @@ -20,13 +20,13 @@ &mscc_felix_port0 { status = "okay"; phy-mode = "2500base-x"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; }; &mscc_felix_port3 { status = "okay"; phy-mode = "2500base-x"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; }; &mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi index 94b5081d61..d9ccd8353b 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi @@ -15,5 +15,5 @@ &enetc0 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi index 3b850268e6..0630f12069 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi @@ -45,25 +45,25 @@ &mscc_felix_port0 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; }; &mscc_felix_port1 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>; }; &mscc_felix_port2 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; }; &mscc_felix_port3 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; }; &mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi index eb632143e0..170aacf8c0 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi @@ -30,25 +30,25 @@ &mscc_felix_port0 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; }; &mscc_felix_port1 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>; }; &mscc_felix_port2 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; }; &mscc_felix_port3 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; }; &mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi index ed86da6b26..1a9288a037 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi @@ -30,25 +30,25 @@ &mscc_felix_port0 { status = "okay"; phy-mode = "usxgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>; }; &mscc_felix_port1 { status = "okay"; phy-mode = "usxgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>; }; &mscc_felix_port2 { status = "okay"; phy-mode = "usxgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; }; &mscc_felix_port3 { status = "okay"; phy-mode = "usxgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>; }; &mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi index c9de4ecc43..544f548b1a 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi @@ -24,25 +24,25 @@ &mscc_felix_port0 { status = "okay"; phy-mode = "qsgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>; }; &mscc_felix_port1 { status = "okay"; phy-mode = "qsgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>; }; &mscc_felix_port2 { status = "okay"; phy-mode = "qsgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>; }; &mscc_felix_port3 { status = "okay"; phy-mode = "qsgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>; }; &mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi index 7f785507bf..639796263c 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi @@ -20,7 +20,7 @@ &mscc_felix_port1 { status = "okay"; phy-mode = "2500base-x"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; }; &mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi index 0fbe7721c8..62c5513c2c 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi @@ -20,7 +20,7 @@ &mscc_felix_port2 { status = "okay"; phy-mode = "2500base-x"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>; }; &mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 54f97014be..de85fdd045 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -203,94 +203,6 @@ }; }; - i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - i2c1: i2c@2010000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - i2c2: i2c@2020000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - i2c3: i2c@2030000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - i2c4: i2c@2040000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2040000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - i2c5: i2c@2050000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2050000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - i2c6: i2c@2060000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2060000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - i2c7: i2c@2070000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2070000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - lpuart0: serial@2260000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2260000 0x0 0x1000>; @@ -484,5 +396,93 @@ #clock-cells = <2>; clocks = <&sysclk>; }; + + i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c4: i2c@2040000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2040000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c5: i2c@2050000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2050000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c6: i2c@2060000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2060000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c7: i2c@2070000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2070000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; }; }; From f02f2f93a543d96c09bf5ce159c90f608202218b Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:06 +0200 Subject: [PATCH 25/62] arm: dts: ls1028a: move the FlexSPI controller node While inserting it into the new location, keep it sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index de85fdd045..6d80b32816 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -43,19 +43,6 @@ IRQ_TYPE_LEVEL_LOW)>; }; - fspi: flexspi@20c0000 { - compatible = "nxp,lx2160a-fspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "fspi_en", "fspi"; - interrupts = ; - status = "disabled"; - }; - serial0: serial@21c0500 { device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; @@ -484,5 +471,18 @@ clocks = <&clockgen 4 0>; status = "disabled"; }; + + fspi: flexspi@20c0000 { + compatible = "nxp,lx2160a-fspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "fspi_en", "fspi"; + interrupts = ; + status = "disabled"; + }; }; }; From fbddc2701d2e0faea8193c7bfc1d2c810f0f73a6 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:07 +0200 Subject: [PATCH 26/62] arm: dts: ls1028a: move the SPI and eSDHC controller nodes into /soc While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 116 +++++++++++++++++----------------- 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 6d80b32816..ecafa67d08 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -266,64 +266,6 @@ status = "disabled"; }; - dspi0: dspi@2100000 { - compatible = "fsl,vf610-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - num-cs = <5>; - litte-endian; - status = "disabled"; - }; - - dspi1: dspi@2110000 { - compatible = "fsl,vf610-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - num-cs = <5>; - little-endian; - status = "disabled"; - }; - - dspi2: dspi@2120000 { - compatible = "fsl,vf610-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2120000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - num-cs = <5>; - little-endian; - status = "disabled"; - }; - - esdhc0: esdhc@2140000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = ; - big-endian; - bus-width = <4>; - status = "disabled"; - }; - - esdhc1: esdhc@2150000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2150000 0x0 0x10000>; - interrupts = ; - big-endian; - non-removable; - bus-width = <4>; - status = "disabled"; - }; - gpio0: gpio@2300000 { compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; @@ -484,5 +426,63 @@ interrupts = ; status = "disabled"; }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = ; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + litte-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = ; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + little-endian; + status = "disabled"; + }; + + dspi2: dspi@2120000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = ; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + little-endian; + status = "disabled"; + }; + + esdhc0: esdhc@2140000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = ; + big-endian; + bus-width = <4>; + status = "disabled"; + }; + + esdhc1: esdhc@2150000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2150000 0x0 0x10000>; + interrupts = ; + big-endian; + non-removable; + bus-width = <4>; + status = "disabled"; + }; }; }; From 44800f2b4f7fb49520b9142037d6eacce18a32ce Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:08 +0200 Subject: [PATCH 27/62] arm: dts: ls1028a: move the UART controller nodes into /soc While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index ecafa67d08..07aeb380ef 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -43,22 +43,6 @@ IRQ_TYPE_LEVEL_LOW)>; }; - serial0: serial@21c0500 { - device_type = "serial"; - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - interrupts = ; - status = "disabled"; - }; - - serial1: serial@21c0600 { - device_type = "serial"; - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; - interrupts = ; - status = "disabled"; - }; - pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 @@ -484,5 +468,21 @@ bus-width = <4>; status = "disabled"; }; + + serial0: serial@21c0500 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + interrupts = ; + status = "disabled"; + }; + + serial1: serial@21c0600 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0600 0x0 0x100>; + interrupts = ; + status = "disabled"; + }; }; }; From ebcd6d77ca842df798a77b372f7019a0b8fe30b4 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:09 +0200 Subject: [PATCH 28/62] arm: dts: ls1028a: move the low-power UART nodes into /soc While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 120 +++++++++++++++++----------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 07aeb380ef..349c4bf862 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -174,66 +174,6 @@ }; }; - lpuart0: serial@2260000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2260000 0x0 0x1000>; - interrupts = <0 232 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; - - lpuart1: serial@2270000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2270000 0x0 0x1000>; - interrupts = <0 233 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; - - lpuart2: serial@2280000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2280000 0x0 0x1000>; - interrupts = <0 234 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; - - lpuart3: serial@2290000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2290000 0x0 0x1000>; - interrupts = <0 235 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; - - lpuart4: serial@22a0000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x22a0000 0x0 0x1000>; - interrupts = <0 236 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; - - lpuart5: serial@22b0000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x22b0000 0x0 0x1000>; - interrupts = <0 237 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; - usb1: usb3@3100000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; @@ -484,5 +424,65 @@ interrupts = ; status = "disabled"; }; + + lpuart0: serial@2260000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2260000 0x0 0x1000>; + interrupts = <0 232 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + }; + + lpuart1: serial@2270000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2270000 0x0 0x1000>; + interrupts = <0 233 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + }; + + lpuart2: serial@2280000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2280000 0x0 0x1000>; + interrupts = <0 234 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + }; + + lpuart3: serial@2290000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2290000 0x0 0x1000>; + interrupts = <0 235 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + }; + + lpuart4: serial@22a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x22a0000 0x0 0x1000>; + interrupts = <0 236 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + }; + + lpuart5: serial@22b0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x22b0000 0x0 0x1000>; + interrupts = <0 237 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + }; }; }; From 65da65f6e26410075ed0cb3e91bee6c9b5672728 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:10 +0200 Subject: [PATCH 29/62] arm: dts: ls1028a: move the GPIO controller nodes into /soc While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 66 +++++++++++++++++------------------ 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 349c4bf862..9f466554e9 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -190,39 +190,6 @@ status = "disabled"; }; - gpio0: gpio@2300000 { - compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; - }; - sata: sata@3200000 { compatible = "fsl,ls1028a-ahci"; reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ @@ -484,5 +451,38 @@ little-endian; status = "disabled"; }; + + gpio0: gpio@2300000 { + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + little-endian; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + little-endian; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + little-endian; + }; }; }; From 659fafc3fda52425bec55133b07adb7b888eaa59 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:11 +0200 Subject: [PATCH 30/62] arm: dts: ls1028a: move SATA and USB controller nodes into /soc While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 50 +++++++++++++++++------------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 9f466554e9..7d18085615 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -174,31 +174,6 @@ }; }; - usb1: usb3@3100000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - status = "disabled"; - }; - - usb2: usb3@3110000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - status = "disabled"; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1028a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ - 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ - reg-names = "sata-base", "ecc-addr"; - interrupts = ; - status = "disabled"; - }; - cluster1_core0_watchdog: wdt@c000000 { compatible = "arm,sp805-wdt"; reg = <0x0 0xc000000 0x0 0x1000>; @@ -484,5 +459,30 @@ #interrupt-cells = <2>; little-endian; }; + + usb1: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = ; + dr_mode = "host"; + status = "disabled"; + }; + + usb2: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = ; + dr_mode = "host"; + status = "disabled"; + }; + + sata: sata@3200000 { + compatible = "fsl,ls1028a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; + interrupts = ; + status = "disabled"; + }; }; }; From 3c5c47777c0a5250f07dd63e079be7ed8c174218 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:12 +0200 Subject: [PATCH 31/62] arm: dts: ls1028a: move the PCIe controller nodes into /soc While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. While at it fix the indentation. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 64 +++++++++++++++++------------------ 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 7d18085615..d0f90941b9 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -43,38 +43,6 @@ IRQ_TYPE_LEVEL_LOW)>; }; - pcie1: pcie@3400000 { - compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; - reg = <0x00 0x03400000 0x0 0x80000 - 0x00 0x03480000 0x0 0x40000 /* lut registers */ - 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ - 0x80 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; - - pcie2: pcie@3500000 { - compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; - reg = <0x00 0x03500000 0x0 0x80000 - 0x00 0x03580000 0x0 0x40000 /* lut registers */ - 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ - 0x88 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; - pcie@1f0000000 { compatible = "pci-host-ecam-generic"; /* ECAM bus 0, HW has more space reserved but not populated */ @@ -484,5 +452,37 @@ interrupts = ; status = "disabled"; }; + + pcie1: pcie@3400000 { + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 + 0x00 0x03480000 0x0 0x40000 /* lut registers */ + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ + 0x80 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie2: pcie@3500000 { + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x80000 + 0x00 0x03580000 0x0 0x40000 /* lut registers */ + 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ + 0x88 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; }; }; From 575205c9cc91e5914aa8b2ec884c78dc7d359b7c Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:13 +0200 Subject: [PATCH 32/62] arm: dts: ls1028a: move the watchdog node into /soc While inserting it into the new location, keep it sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index d0f90941b9..c289009ca1 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -142,11 +142,6 @@ }; }; - cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805-wdt"; - reg = <0x0 0xc000000 0x0 0x1000>; - }; - soc: soc { compatible = "simple-bus"; #address-cells = <2>; @@ -484,5 +479,10 @@ ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + cluster1_core0_watchdog: wdt@c000000 { + compatible = "arm,sp805-wdt"; + reg = <0x0 0xc000000 0x0 0x1000>; + }; }; }; From f3f41f6c5c68a4c79676a86dfa79c9e07cffc7e8 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:14 +0200 Subject: [PATCH 33/62] arm: dts: ls1028a: move the iRC node and its devices into /soc While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. While at it fix the indentation. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 202 +++++++++++++++++----------------- 1 file changed, 103 insertions(+), 99 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index c289009ca1..ca593c7218 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -43,105 +43,6 @@ IRQ_TYPE_LEVEL_LOW)>; }; - pcie@1f0000000 { - compatible = "pci-host-ecam-generic"; - /* ECAM bus 0, HW has more space reserved but not populated */ - bus-range = <0x0 0x0>; - reg = <0x01 0xf0000000 0x0 0x100000>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>; - enetc0: pci@0,0 { - reg = <0x000000 0 0 0 0>; - status = "disabled"; - }; - enetc1: pci@0,1 { - reg = <0x000100 0 0 0 0>; - status = "disabled"; - }; - enetc2: pci@0,2 { - reg = <0x000200 0 0 0 0>; - status = "disabled"; - phy-mode = "internal"; - - fixed-link { - speed = <2500>; - full-duplex; - }; - }; - mdio0: pci@0,3 { - #address-cells=<0>; - #size-cells=<1>; - reg = <0x000300 0 0 0 0>; - status = "disabled"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - mscc_felix: pci@0,5 { - reg = <0x000500 0 0 0 0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mscc_felix_port0: port@0 { - reg = <0>; - status = "disabled"; - }; - - mscc_felix_port1: port@1 { - reg = <1>; - status = "disabled"; - }; - - mscc_felix_port2: port@2 { - reg = <2>; - status = "disabled"; - }; - - mscc_felix_port3: port@3 { - reg = <3>; - status = "disabled"; - }; - - mscc_felix_port4: port@4 { - reg = <4>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <2500>; - full-duplex; - }; - }; - - mscc_felix_port5: port@5 { - reg = <5>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - - }; - }; - }; - - enetc6: pci@0,6 { - reg = <0x000600 0 0 0 0>; - status = "disabled"; - phy-mode = "internal"; - }; - }; - soc: soc { compatible = "simple-bus"; #address-cells = <2>; @@ -484,5 +385,108 @@ compatible = "arm,sp805-wdt"; reg = <0x0 0xc000000 0x0 0x1000>; }; + + pcie@1f0000000 { + compatible = "pci-host-ecam-generic"; + /* ECAM bus 0, HW has more space reserved but not populated */ + bus-range = <0x0 0x0>; + reg = <0x01 0xf0000000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>; + + enetc0: pci@0,0 { + reg = <0x000000 0 0 0 0>; + status = "disabled"; + }; + + enetc1: pci@0,1 { + reg = <0x000100 0 0 0 0>; + status = "disabled"; + }; + + enetc2: pci@0,2 { + reg = <0x000200 0 0 0 0>; + status = "disabled"; + phy-mode = "internal"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + mdio0: pci@0,3 { + #address-cells=<0>; + #size-cells=<1>; + reg = <0x000300 0 0 0 0>; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + mscc_felix: pci@0,5 { + reg = <0x000500 0 0 0 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mscc_felix_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + mscc_felix_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + mscc_felix_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + mscc_felix_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + mscc_felix_port4: port@4 { + reg = <4>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + mscc_felix_port5: port@5 { + reg = <5>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + }; + }; + }; + + enetc6: pci@0,6 { + reg = <0x000600 0 0 0 0>; + status = "disabled"; + phy-mode = "internal"; + }; + }; }; }; From c816dd03247576bb3eb5ac694d98b3ea0c0a1e5d Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:15 +0200 Subject: [PATCH 34/62] arm: dts: ls1028a: update the labels Update the labels of the nodes to match the kernel ones. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Tested-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- .../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 10 +++---- .../fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi | 2 +- .../arm/dts/fsl-ls1028a-kontron-sl28-var1.dts | 6 ++--- .../arm/dts/fsl-ls1028a-kontron-sl28-var2.dts | 8 +++--- .../fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi | 2 +- .../fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi | 4 +-- .../arm/dts/fsl-ls1028a-kontron-sl28-var4.dts | 4 +-- arch/arm/dts/fsl-ls1028a-kontron-sl28.dts | 26 +++++++++---------- .../dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi | 2 +- .../dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi | 2 +- .../dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 4 +-- .../dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 4 +-- .../dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi | 2 +- .../fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi | 4 +-- .../dts/fsl-ls1028a-qds-9999-sch-24801.dtsi | 4 +-- arch/arm/dts/fsl-ls1028a-qds-duart.dts | 2 +- .../fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi | 4 +-- .../fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi | 4 +-- .../dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 4 +-- .../dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 4 +-- arch/arm/dts/fsl-ls1028a-qds.dtsi | 20 +++++++------- arch/arm/dts/fsl-ls1028a-rdb.dts | 26 +++++++++---------- arch/arm/dts/fsl-ls1028a.dtsi | 26 +++++++++---------- 23 files changed, 87 insertions(+), 87 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index 0b1afe37e9..68a3e0b7aa 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -5,13 +5,13 @@ / { aliases { mmc0 = &esdhc1; - mmc1 = &esdhc0; + mmc1 = &esdhc; i2c0 = &i2c0; i2c1 = &i2c3; i2c2 = &i2c4; rtc0 = &rtc; - ethernet2 = &enetc2; - ethernet3 = &enetc6; + ethernet2 = &enetc_port2; + ethernet3 = &enetc_port3; }; binman: binman { @@ -281,7 +281,7 @@ u-boot,dm-pre-reloc; }; -&esdhc0 { +&esdhc { u-boot,dm-pre-reloc; }; @@ -293,7 +293,7 @@ u-boot,dm-pre-reloc; }; -&serial0 { +&duart0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi index 98e8939369..a46e07dc6b 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi @@ -3,6 +3,6 @@ / { aliases { - ethernet0 = &enetc1; + ethernet0 = &enetc_port1; }; }; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts index 33d85ed83a..ba2e4de96d 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts @@ -21,19 +21,19 @@ compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a"; }; -&enetc0 { +&enetc_port0 { status = "disabled"; /delete-property/ phy-handle; }; -&enetc1 { +&enetc_port1 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; status = "okay"; }; /delete-node/ &phy0; -&mdio0 { +&enetc_mdio_pf3 { phy0: ethernet-phy@4 { reg = <0x4>; eee-broken-1000t; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts index 7a3aa21408..db80874f4e 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts @@ -17,12 +17,12 @@ compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a"; }; -&enetc0 { +&enetc_port0 { status = "disabled"; /delete-property/ phy-handle; }; -&enetc2 { +&enetc_port2 { status = "okay"; }; @@ -45,12 +45,12 @@ }; &mscc_felix_port4 { - ethernet = <&enetc2>; + ethernet = <&enetc_port2>; status = "okay"; }; /delete-node/ &phy0; -&mdio0 { +&enetc_mdio_pf3 { phy0: ethernet-phy@5 { reg = <0x5>; eee-broken-1000t; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi index 879a76415b..3d6bf5a0bd 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi @@ -3,6 +3,6 @@ / { aliases { - ethernet0 = &enetc0; + ethernet0 = &enetc_port0; }; }; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi index fce4694682..5d82973bba 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi @@ -3,7 +3,7 @@ / { aliases { - ethernet0 = &enetc0; - ethernet1 = &enetc1; + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; }; }; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts index b95e082b70..54d12ab992 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts @@ -18,13 +18,13 @@ compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; }; -&enetc1 { +&enetc_port1 { phy-handle = <&phy1>; phy-mode = "rgmii-id"; status = "okay"; }; -&mdio0 { +&enetc_mdio_pf3 { phy1: ethernet-phy@4 { reg = <0x4>; eee-broken-1000t; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts index 7f237c39ec..9ae70ba541 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts @@ -14,8 +14,8 @@ compatible = "kontron,sl28", "fsl,ls1028a"; aliases { - serial0 = &serial0; - serial1 = &serial1; + serial0 = &duart0; + serial1 = &duart1; serial2 = &lpuart1; spi0 = &fspi; spi1 = &dspi2; @@ -30,21 +30,21 @@ status = "okay"; }; -&enetc0 { +&enetc_port0 { phy-handle = <&phy0>; phy-mode = "sgmii"; status = "okay"; }; -&enetc2 { +&enetc_port2 { status = "disabled"; }; -&enetc6 { +&enetc_port3 { status = "disabled"; }; -&esdhc0 { +&esdhc { sd-uhs-sdr104; sd-uhs-sdr50; sd-uhs-sdr25; @@ -108,7 +108,7 @@ status = "okay"; }; -&mdio0 { +&enetc_mdio_pf3 { status = "okay"; phy0: ethernet-phy@5 { reg = <0x5>; @@ -121,18 +121,18 @@ status = "okay"; }; -&serial0 { +&duart0 { status = "okay"; }; -&serial1 { +&duart1 { + status = "okay"; +}; + +&usb0 { status = "okay"; }; &usb1 { status = "okay"; }; - -&usb2 { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi index 1f13cf80e6..f4c557e69e 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi @@ -13,7 +13,7 @@ #include "fsl-sch-30842.dtsi" }; -&enetc0 { +&enetc_port0 { status = "okay"; phy-mode = "usxgmii"; phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi index 10375b2751..69274ee4e9 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi @@ -12,7 +12,7 @@ #include "fsl-sch-30842.dtsi" }; -&enetc0 { +&enetc_port0 { status = "okay"; phy-mode = "2500base-x"; phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi index f18cb39f21..90da665a3c 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi @@ -20,7 +20,7 @@ #include "fsl-sch-30841.dtsi" }; -&enetc2 { +&enetc_port2 { status = "okay"; }; @@ -53,6 +53,6 @@ }; &mscc_felix_port4 { - ethernet = <&enetc2>; + ethernet = <&enetc_port2>; status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi index f6561a89eb..27c3d655bf 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi @@ -9,7 +9,7 @@ #include "fsl-sch-30841.dtsi" }; -&enetc2 { +&enetc_port2 { status = "okay"; }; @@ -30,6 +30,6 @@ }; &mscc_felix_port4 { - ethernet = <&enetc2>; + ethernet = <&enetc_port2>; status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi index d9ccd8353b..7d197c3181 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi @@ -12,7 +12,7 @@ #include "fsl-sch-24801.dtsi" }; -&enetc0 { +&enetc_port0 { status = "okay"; phy-mode = "sgmii"; phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi index 0630f12069..992092ec78 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi @@ -34,7 +34,7 @@ #include "fsl-sch-24801.dtsi" }; -&enetc2 { +&enetc_port2 { status = "okay"; }; @@ -67,6 +67,6 @@ }; &mscc_felix_port4 { - ethernet = <&enetc2>; + ethernet = <&enetc_port2>; status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi index 170aacf8c0..a905d77a9a 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi @@ -19,7 +19,7 @@ #include "fsl-sch-24801.dtsi" }; -&enetc2 { +&enetc_port2 { status = "okay"; }; @@ -52,6 +52,6 @@ }; &mscc_felix_port4 { - ethernet = <&enetc2>; + ethernet = <&enetc_port2>; status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-duart.dts b/arch/arm/dts/fsl-ls1028a-qds-duart.dts index 83264e0f54..81db21a947 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-duart.dts +++ b/arch/arm/dts/fsl-ls1028a-qds-duart.dts @@ -10,6 +10,6 @@ / { chosen { - stdout-path = &serial0; + stdout-path = &duart0; }; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi index 1a9288a037..62e818f099 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi @@ -19,7 +19,7 @@ #include "fsl-sch-30841.dtsi" }; -&enetc2 { +&enetc_port2 { status = "okay"; }; @@ -52,6 +52,6 @@ }; &mscc_felix_port4 { - ethernet = <&enetc2>; + ethernet = <&enetc_port2>; status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi index 544f548b1a..6f1f6cb32a 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi @@ -13,7 +13,7 @@ #include "fsl-sch-28021.dtsi" }; -&enetc2 { +&enetc_port2 { status = "okay"; }; @@ -46,6 +46,6 @@ }; &mscc_felix_port4 { - ethernet = <&enetc2>; + ethernet = <&enetc_port2>; status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi index 639796263c..6c0d8b23ef 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi @@ -9,7 +9,7 @@ #include "fsl-sch-30842.dtsi" }; -&enetc2 { +&enetc_port2 { status = "okay"; }; @@ -24,6 +24,6 @@ }; &mscc_felix_port4 { - ethernet = <&enetc2>; + ethernet = <&enetc_port2>; status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi index 62c5513c2c..9af6a5a674 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi @@ -9,7 +9,7 @@ #include "fsl-sch-30842.dtsi" }; -&enetc2 { +&enetc_port2 { status = "okay"; }; @@ -24,6 +24,6 @@ }; &mscc_felix_port4 { - ethernet = <&enetc2>; + ethernet = <&enetc_port2>; status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index 335d7b1e4c..babd8445ee 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -105,7 +105,7 @@ }; }; -&esdhc0 { +&esdhc { status = "okay"; }; @@ -144,7 +144,7 @@ reg = <0x54>; #mux-control-cells = <1>; mux-reg-masks = <0x54 0xf0>; - mdio-parent-bus = <&mdio0>; + mdio-parent-bus = <&enetc_mdio_pf3>; /* on-board MDIO with a single RGMII PHY */ mdio@00 { @@ -232,11 +232,15 @@ status = "okay"; }; -&serial0 { +&duart0 { status = "okay"; }; -&serial1 { +&duart1 { + status = "okay"; +}; + +&usb0 { status = "okay"; }; @@ -244,17 +248,13 @@ status = "okay"; }; -&usb2 { - status = "okay"; -}; - -&enetc1 { +&enetc_port1 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <&qds_phy0>; }; -&mdio0 { +&enetc_mdio_pf3 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index 708182f65c..18ee363d75 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -15,8 +15,8 @@ compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; aliases { spi0 = &fspi; - ethernet0 = &enetc0; - ethernet1 = &enetc2; + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port2; ethernet2 = &mscc_felix_port0; ethernet3 = &mscc_felix_port1; ethernet4 = &mscc_felix_port2; @@ -36,7 +36,7 @@ status = "okay"; }; -&esdhc0 { +&esdhc { status = "okay"; }; @@ -114,11 +114,15 @@ status = "okay"; }; -&serial0 { +&duart0 { status = "okay"; }; -&serial1 { +&duart1 { + status = "okay"; +}; + +&usb0 { status = "okay"; }; @@ -126,17 +130,13 @@ status = "okay"; }; -&usb2 { - status = "okay"; -}; - -&enetc0 { +&enetc_port0 { status = "okay"; phy-mode = "sgmii"; phy-handle = <&rdb_phy0>; }; -&enetc2 { +&enetc_port2 { status = "okay"; }; @@ -173,11 +173,11 @@ }; &mscc_felix_port4 { - ethernet = <&enetc2>; + ethernet = <&enetc_port2>; status = "okay"; }; -&mdio0 { +&enetc_mdio_pf3 { status = "okay"; rdb_phy0: phy@2 { reg = <2>; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index ca593c7218..e5b5a0dc9f 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -196,7 +196,7 @@ status = "disabled"; }; - esdhc0: esdhc@2140000 { + esdhc: esdhc@2140000 { compatible = "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; interrupts = ; @@ -215,7 +215,7 @@ status = "disabled"; }; - serial0: serial@21c0500 { + duart0: serial@21c0500 { device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; @@ -223,7 +223,7 @@ status = "disabled"; }; - serial1: serial@21c0600 { + duart1: serial@21c0600 { device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; @@ -291,7 +291,7 @@ status = "disabled"; }; - gpio0: gpio@2300000 { + gpio1: gpio@2300000 { compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; interrupts = ; @@ -302,7 +302,7 @@ little-endian; }; - gpio1: gpio@2310000 { + gpio2: gpio@2310000 { compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; reg = <0x0 0x2310000 0x0 0x10000>; interrupts = ; @@ -313,7 +313,7 @@ little-endian; }; - gpio2: gpio@2320000 { + gpio3: gpio@2320000 { compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; reg = <0x0 0x2320000 0x0 0x10000>; interrupts = ; @@ -324,7 +324,7 @@ little-endian; }; - usb1: usb3@3100000 { + usb0: usb3@3100000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; @@ -332,7 +332,7 @@ status = "disabled"; }; - usb2: usb3@3110000 { + usb1: usb3@3110000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = ; @@ -396,17 +396,17 @@ device_type = "pci"; ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>; - enetc0: pci@0,0 { + enetc_port0: pci@0,0 { reg = <0x000000 0 0 0 0>; status = "disabled"; }; - enetc1: pci@0,1 { + enetc_port1: pci@0,1 { reg = <0x000100 0 0 0 0>; status = "disabled"; }; - enetc2: pci@0,2 { + enetc_port2: pci@0,2 { reg = <0x000200 0 0 0 0>; status = "disabled"; phy-mode = "internal"; @@ -417,7 +417,7 @@ }; }; - mdio0: pci@0,3 { + enetc_mdio_pf3: pci@0,3 { #address-cells=<0>; #size-cells=<1>; reg = <0x000300 0 0 0 0>; @@ -482,7 +482,7 @@ }; }; - enetc6: pci@0,6 { + enetc_port3: pci@0,6 { reg = <0x000600 0 0 0 0>; status = "disabled"; phy-mode = "internal"; From 5709a858c04a12ff6dc04fa003e501e720f91159 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:16 +0200 Subject: [PATCH 35/62] watchdog: sp805_wdt: use correct compatible string According to the linux device tree specification the compatible string is: compatible = "arm,sp805", "arm,primecell"; Fix all users in u-boot. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 2 +- arch/arm/dts/hi3660.dtsi | 4 ++-- drivers/watchdog/sp805_wdt.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index e5b5a0dc9f..cbdddccaea 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -382,7 +382,7 @@ }; cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805-wdt"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; }; diff --git a/arch/arm/dts/hi3660.dtsi b/arch/arm/dts/hi3660.dtsi index 65a45b0e80..028f4db60d 100644 --- a/arch/arm/dts/hi3660.dtsi +++ b/arch/arm/dts/hi3660.dtsi @@ -1087,7 +1087,7 @@ }; watchdog0: watchdog@e8a06000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xe8a06000 0x0 0x1000>; interrupts = ; clocks = <&crg_ctrl HI3660_OSC32K>; @@ -1095,7 +1095,7 @@ }; watchdog1: watchdog@e8a07000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xe8a07000 0x0 0x1000>; interrupts = ; clocks = <&crg_ctrl HI3660_OSC32K>; diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c index bec8827ceb..0d6fb12065 100644 --- a/drivers/watchdog/sp805_wdt.c +++ b/drivers/watchdog/sp805_wdt.c @@ -134,7 +134,7 @@ static const struct wdt_ops sp805_wdt_ops = { }; static const struct udevice_id sp805_wdt_ids[] = { - { .compatible = "arm,sp805-wdt" }, + { .compatible = "arm,sp805" }, {} }; From 765afe7fb3f9d6c030091401b6511eebda06db2d Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:17 +0200 Subject: [PATCH 36/62] spi: fsl_dspi: add new compatible fsl, ls1021a-v1.0-dspi The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; Add the missing compatible to the driver and update the device tree. We can use the fallback "fsl,ls1021a-v1.0-dspi", because the endianness is determined by the little-endian property and not by the compatible string itself. Further, we won't need and specific details on the DMA configuration (which is different on the LS1021A). If it's ever needed, we can later add the more specific "fsl,ls1028a-dspi" compatible to the driver. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 6 +++--- drivers/spi/fsl_dspi.c | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index cbdddccaea..6158a1362a 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -158,7 +158,7 @@ }; dspi0: dspi@2100000 { - compatible = "fsl,vf610-dspi"; + compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; @@ -171,7 +171,7 @@ }; dspi1: dspi@2110000 { - compatible = "fsl,vf610-dspi"; + compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2110000 0x0 0x10000>; @@ -184,7 +184,7 @@ }; dspi2: dspi@2120000 { - compatible = "fsl,vf610-dspi"; + compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2120000 0x0 0x10000>; diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 8fe3508c64..23d812f476 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -654,6 +654,7 @@ static const struct dm_spi_ops fsl_dspi_ops = { static const struct udevice_id fsl_dspi_ids[] = { { .compatible = "fsl,vf610-dspi" }, + { .compatible = "fsl,ls1021a-v1.0-dspi" }, { } }; From 8c580892872bc472f721be3b9662c1d89eb1191b Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:18 +0200 Subject: [PATCH 37/62] spi: fsl_dspi: rename num-cs to spi-num-chipselects The official devicetree bindings specifies spi-num-chipselects as the name. Use it. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1012a.dtsi | 2 +- arch/arm/dts/fsl-ls1028a.dtsi | 6 +++--- arch/arm/dts/fsl-ls1043a.dtsi | 4 ++-- arch/arm/dts/fsl-ls1046a.dtsi | 4 ++-- arch/arm/dts/fsl-ls1088a.dtsi | 2 +- arch/arm/dts/fsl-ls2080a.dtsi | 2 +- arch/arm/dts/fsl-lx2160a.dtsi | 6 +++--- arch/arm/dts/ls1021a.dtsi | 4 ++-- arch/arm/dts/vf.dtsi | 4 ++-- drivers/spi/fsl_dspi.c | 5 +++-- 10 files changed, 20 insertions(+), 19 deletions(-) diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 2894842cf2..dcdcd444b3 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -49,7 +49,7 @@ interrupts = <0 64 0x4>; clock-names = "dspi"; clocks = <&clockgen 4 0>; - num-cs = <6>; + spi-num-chipselects = <6>; big-endian; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 6158a1362a..7da32561a4 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -165,7 +165,7 @@ interrupts = ; clock-names = "dspi"; clocks = <&clockgen 4 0>; - num-cs = <5>; + spi-num-chipselects = <5>; litte-endian; status = "disabled"; }; @@ -178,7 +178,7 @@ interrupts = ; clock-names = "dspi"; clocks = <&clockgen 4 0>; - num-cs = <5>; + spi-num-chipselects = <5>; little-endian; status = "disabled"; }; @@ -191,7 +191,7 @@ interrupts = ; clock-names = "dspi"; clocks = <&clockgen 4 0>; - num-cs = <5>; + spi-num-chipselects = <5>; little-endian; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index d8171bd03b..3aaec8b6af 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -53,7 +53,7 @@ interrupts = <0 64 0x4>; clock-names = "dspi"; clocks = <&clockgen 4 0>; - num-cs = <6>; + spi-num-chipselects = <6>; big-endian; status = "disabled"; }; @@ -66,7 +66,7 @@ interrupts = <0 65 0x4>; clock-names = "dspi"; clocks = <&clockgen 4 0>; - num-cs = <6>; + spi-num-chipselects = <6>; big-endian; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 9df419a87d..6a205cd3df 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -52,7 +52,7 @@ interrupts = <0 64 0x4>; clock-names = "dspi"; clocks = <&clockgen 4 0>; - num-cs = <6>; + spi-num-chipselects = <6>; big-endian; status = "disabled"; }; @@ -65,7 +65,7 @@ interrupts = <0 65 0x4>; clock-names = "dspi"; clocks = <&clockgen 4 0>; - num-cs = <6>; + spi-num-chipselects = <6>; big-endian; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 0db02b1c23..73c8928858 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -89,7 +89,7 @@ #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; interrupts = <0 26 0x4>; /* Level high type */ - num-cs = <6>; + spi-num-chipselects = <6>; }; qspi: quadspi@1550000 { diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 278daeeb6e..72ba52594a 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -93,7 +93,7 @@ #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; interrupts = <0 26 0x4>; /* Level high type */ - num-cs = <6>; + spi-num-chipselects = <6>; }; qspi: quadspi@1550000 { diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 3b5f0d119e..52e4d7205a 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -172,7 +172,7 @@ #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; interrupts = <0 26 0x4>; /* Level high type */ - num-cs = <6>; + spi-num-chipselects = <6>; }; dspi1: dspi@2110000 { @@ -181,7 +181,7 @@ #size-cells = <0>; reg = <0x0 0x2110000 0x0 0x10000>; interrupts = <0 26 0x4>; /* Level high type */ - num-cs = <6>; + spi-num-chipselects = <6>; }; dspi2: dspi@2120000 { @@ -190,7 +190,7 @@ #size-cells = <0>; reg = <0x0 0x2120000 0x0 0x10000>; interrupts = <0 241 0x4>; /* Level high type */ - num-cs = <6>; + spi-num-chipselects = <6>; }; gpio0: gpio@2300000 { diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 7ba2dd2269..8aefc82f87 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -190,7 +190,7 @@ interrupts = ; clock-names = "dspi"; clocks = <&platform_clk 1>; - num-cs = <6>; + spi-num-chipselects = <6>; big-endian; status = "disabled"; }; @@ -203,7 +203,7 @@ interrupts = ; clock-names = "dspi"; clocks = <&platform_clk 1>; - num-cs = <6>; + spi-num-chipselects = <6>; big-endian; status = "disabled"; }; diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi index 5ba13dc62b..1bdaf3de23 100644 --- a/arch/arm/dts/vf.dtsi +++ b/arch/arm/dts/vf.dtsi @@ -70,7 +70,7 @@ #size-cells = <0>; compatible = "fsl,vf610-dspi"; reg = <0x4002c000 0x1000>; - num-cs = <5>; + spi-num-chipselects = <5>; status = "disabled"; }; @@ -79,7 +79,7 @@ #size-cells = <0>; compatible = "fsl,vf610-dspi"; reg = <0x4002d000 0x1000>; - num-cs = <5>; + spi-num-chipselects = <5>; status = "disabled"; }; diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 23d812f476..62444e408a 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -586,8 +586,9 @@ static int fsl_dspi_of_to_plat(struct udevice *bus) if (fdtdec_get_bool(blob, node, "big-endian")) plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG; - plat->num_chipselect = - fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT); + plat->num_chipselect = fdtdec_get_int(blob, node, + "spi-num-chipselects", + FSL_DSPI_MAX_CHIPSELECT); addr = dev_read_addr(bus); if (addr == FDT_ADDR_T_NONE) { From c9bf9af9a71207ea7355af54a88f13addbd737e1 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:19 +0200 Subject: [PATCH 38/62] serial: lpuart: add new compatible fsl, ls1028a-lpuart The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-lpuart"; Add the missing compatible to the driver and update the device tree. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 18 ++++++------------ drivers/serial/serial_lpuart.c | 2 ++ 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 7da32561a4..cf381a0856 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -232,62 +232,56 @@ }; lpuart0: serial@2260000 { - compatible = "fsl,ls1021a-lpuart"; + compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x2260000 0x0 0x1000>; interrupts = <0 232 0x4>; clocks = <&sysclk>; clock-names = "ipg"; - little-endian; status = "disabled"; }; lpuart1: serial@2270000 { - compatible = "fsl,ls1021a-lpuart"; + compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x2270000 0x0 0x1000>; interrupts = <0 233 0x4>; clocks = <&sysclk>; clock-names = "ipg"; - little-endian; status = "disabled"; }; lpuart2: serial@2280000 { - compatible = "fsl,ls1021a-lpuart"; + compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x2280000 0x0 0x1000>; interrupts = <0 234 0x4>; clocks = <&sysclk>; clock-names = "ipg"; - little-endian; status = "disabled"; }; lpuart3: serial@2290000 { - compatible = "fsl,ls1021a-lpuart"; + compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x2290000 0x0 0x1000>; interrupts = <0 235 0x4>; clocks = <&sysclk>; clock-names = "ipg"; - little-endian; status = "disabled"; }; lpuart4: serial@22a0000 { - compatible = "fsl,ls1021a-lpuart"; + compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x22a0000 0x0 0x1000>; interrupts = <0 236 0x4>; clocks = <&sysclk>; clock-names = "ipg"; - little-endian; status = "disabled"; }; lpuart5: serial@22b0000 { - compatible = "fsl,ls1021a-lpuart"; + compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x22b0000 0x0 0x1000>; interrupts = <0 237 0x4>; clocks = <&sysclk>; clock-names = "ipg"; - little-endian; status = "disabled"; }; diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 2b473d70f6..3c9a69598a 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -553,6 +553,8 @@ static const struct dm_serial_ops lpuart_serial_ops = { static const struct udevice_id lpuart_serial_ids[] = { { .compatible = "fsl,ls1021a-lpuart", .data = LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG }, + { .compatible = "fsl,ls1028a-lpuart", + .data = LPUART_FLAG_REGMAP_32BIT_REG }, { .compatible = "fsl,imx7ulp-lpuart", .data = LPUART_FLAG_REGMAP_32BIT_REG }, { .compatible = "fsl,vf610-lpuart"}, From cde9b147ba2f0325d9edeb26b995e65c317e7792 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:20 +0200 Subject: [PATCH 39/62] scsi: ceva: rename the resource name to match the linux kernel one The driver will look for a named resource "ecc-addr", but this isn't the official binding. In fact, the official device tree binding documentation doesn't mention any resource names at all. But it is safe to assume that it's the linux ones we have to use if we want to be compatible with the linux device tree. Thus rename "ecc-addr" to "sata-ecc" and convert all the users in u-boot. While at it, also rename "sata-base" to "ahci" although its not used at all. This change doesn't affect the SATA controller on the ZynqMP. Cc: Michal Simek Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1012a.dtsi | 2 +- arch/arm/dts/fsl-ls1028a.dtsi | 2 +- arch/arm/dts/fsl-ls1043a.dtsi | 2 +- arch/arm/dts/fsl-ls1046a.dtsi | 2 +- arch/arm/dts/fsl-ls1088a.dtsi | 2 +- arch/arm/dts/ls1021a.dtsi | 2 +- drivers/ata/sata_ceva.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index dcdcd444b3..0ea899c7d7 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -157,7 +157,7 @@ compatible = "fsl,ls1012a-ahci"; reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ 0x0 0x20140520 0x0 0x4>; /* ecc sata addr */ - reg-names = "sata-base", "ecc-addr"; + reg-names = "ahci", "sata-ecc"; interrupts = <0 69 4>; clocks = <&clockgen 4 0>; status = "disabled"; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index cf381a0856..34aad526fe 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -338,7 +338,7 @@ compatible = "fsl,ls1028a-ahci"; reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ - reg-names = "sata-base", "ecc-addr"; + reg-names = "ahci", "sata-ecc"; interrupts = ; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 3aaec8b6af..52dc5a9638 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -331,7 +331,7 @@ compatible = "fsl,ls1043a-ahci"; reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/ - reg-names = "sata-base", "ecc-addr"; + reg-names = "ahci", "sata-ecc"; interrupts = <0 69 4>; clocks = <&clockgen 4 0>; status = "disabled"; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 6a205cd3df..a60cbf11fc 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -367,7 +367,7 @@ compatible = "fsl,ls1046a-ahci"; reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/ - reg-names = "sata-base", "ecc-addr"; + reg-names = "ahci", "sata-ecc"; interrupts = <0 69 4>; clocks = <&clockgen 4 1>; status = "disabled"; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 73c8928858..f73fdfda8b 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -226,7 +226,7 @@ compatible = "fsl,ls1088a-ahci"; reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ - reg-names = "sata-base", "ecc-addr"; + reg-names = "ahci", "sata-ecc"; interrupts = <0 133 4>; status = "disabled"; }; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 8aefc82f87..86192cbb7f 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -469,7 +469,7 @@ sata: sata@3200000 { compatible = "fsl,ls1021a-ahci"; reg = <0x3200000 0x10000 0x20220520 0x4>; - reg-names = "sata-base", "ecc-addr"; + reg-names = "ahci", "sata-ecc"; interrupts = <0 101 4>; status = "disabled"; }; diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index 87e6a90f74..b71f10223d 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -212,7 +212,7 @@ static int sata_ceva_of_to_plat(struct udevice *dev) if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; - ret = dev_read_resource_byname(dev, "ecc-addr", &res_regs); + ret = dev_read_resource_byname(dev, "sata-ecc", &res_regs); if (ret) priv->ecc_base = 0; else From 8f176eb8acdb7d2712b5f96bb946751b26a898db Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:21 +0200 Subject: [PATCH 40/62] usb: xhci: fsl: add new compatible fsl,ls1028a-dwc3 The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; Change the ls1028a device tree and add this new compatible to the fsl specific xhci driver, otherwise the generic dwc3 driver will be used with the compatibles above. Cc: Bin Meng Cc: Marek Vasut Signed-off-by: Michael Walle Reviewed-by: Bin Meng Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 4 ++-- drivers/usb/host/xhci-fsl.c | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 34aad526fe..cc055e65e5 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -319,7 +319,7 @@ }; usb0: usb3@3100000 { - compatible = "fsl,layerscape-dwc3"; + compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; dr_mode = "host"; @@ -327,7 +327,7 @@ }; usb1: usb3@3110000 { - compatible = "fsl,layerscape-dwc3"; + compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = ; dr_mode = "host"; diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index f062f12ade..80871908dc 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -159,6 +159,7 @@ static int xhci_fsl_remove(struct udevice *dev) static const struct udevice_id xhci_usb_ids[] = { { .compatible = "fsl,layerscape-dwc3", }, + { .compatible = "fsl,ls1028a-dwc3", }, { } }; From e10da1f985ad8926faa7b18d9467031b41fc9b8e Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:22 +0200 Subject: [PATCH 41/62] pci: layerscape: add official ls1028a binding support The official bindind of the PCIe controller of the ls1028a has the following compatible string: compatible = "fsl,ls1028a-pcie"; Additionally, the resource names and count are different. Update the driver to support this binding and change the entry in the ls1028a device tree. Cc: Hou Zhiqiang Signed-off-by: Michael Walle Reviewed-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 20 +++++------ drivers/pci/pcie_layerscape_rc.c | 61 +++++++++++++++++++++++--------- 2 files changed, 53 insertions(+), 28 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index cc055e65e5..435b965d00 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -344,12 +344,10 @@ }; pcie1: pcie@3400000 { - compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; - reg = <0x00 0x03400000 0x0 0x80000 - 0x00 0x03480000 0x0 0x40000 /* lut registers */ - 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ - 0x80 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; + compatible = "fsl,ls1028a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -360,12 +358,10 @@ }; pcie2: pcie@3500000 { - compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; - reg = <0x00 0x03500000 0x0 0x80000 - 0x00 0x03580000 0x0 0x40000 /* lut registers */ - 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ - 0x88 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; + compatible = "fsl,ls1028a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c index f50d6ef653..217b420076 100644 --- a/drivers/pci/pcie_layerscape_rc.c +++ b/drivers/pci/pcie_layerscape_rc.c @@ -21,6 +21,12 @@ DECLARE_GLOBAL_DATA_PTR; +struct ls_pcie_drvdata { + u32 lut_offset; + u32 ctrl_offset; + bool big_endian; +}; + static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev) { struct ls_pcie *pcie = pcie_rc->pcie; @@ -243,6 +249,7 @@ static void ls_pcie_setup_ctrl(struct ls_pcie_rc *pcie_rc) static int ls_pcie_probe(struct udevice *dev) { + const struct ls_pcie_drvdata *drvdata = (void *)dev_get_driver_data(dev); struct ls_pcie_rc *pcie_rc = dev_get_priv(dev); const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); @@ -260,8 +267,12 @@ static int ls_pcie_probe(struct udevice *dev) pcie_rc->pcie = pcie; + /* try resource name of the official binding first */ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", - "dbi", &pcie_rc->dbi_res); + "regs", &pcie_rc->dbi_res); + if (ret) + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", + "dbi", &pcie_rc->dbi_res); if (ret) { printf("ls-pcie: resource \"dbi\" not found\n"); return ret; @@ -287,21 +298,29 @@ static int ls_pcie_probe(struct udevice *dev) if (pcie->mode == PCI_HEADER_TYPE_NORMAL) return 0; - ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", - "lut", &pcie_rc->lut_res); - if (!ret) - pcie->lut = map_physmem(pcie_rc->lut_res.start, - fdt_resource_size(&pcie_rc->lut_res), - MAP_NOCACHE); + if (drvdata) { + pcie->lut = pcie->dbi + drvdata->lut_offset; + } else { + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", + "lut", &pcie_rc->lut_res); + if (!ret) + pcie->lut = map_physmem(pcie_rc->lut_res.start, + fdt_resource_size(&pcie_rc->lut_res), + MAP_NOCACHE); + } - ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", - "ctrl", &pcie_rc->ctrl_res); - if (!ret) - pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start, - fdt_resource_size(&pcie_rc->ctrl_res), - MAP_NOCACHE); - if (!pcie->ctrl) - pcie->ctrl = pcie->lut; + if (drvdata) { + pcie->ctrl = pcie->lut + drvdata->ctrl_offset; + } else { + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", + "ctrl", &pcie_rc->ctrl_res); + if (!ret) + pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start, + fdt_resource_size(&pcie_rc->ctrl_res), + MAP_NOCACHE); + if (!pcie->ctrl) + pcie->ctrl = pcie->lut; + } if (!pcie->ctrl) { printf("%s: NOT find CTRL\n", dev->name); @@ -343,7 +362,10 @@ static int ls_pcie_probe(struct udevice *dev) pcie_rc->cfg1 = pcie_rc->cfg0 + fdt_resource_size(&pcie_rc->cfg_res) / 2; - pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian"); + if (drvdata) + pcie->big_endian = drvdata->big_endian; + else + pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian"); debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n", dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut, @@ -373,8 +395,15 @@ static const struct dm_pci_ops ls_pcie_ops = { .write_config = ls_pcie_write_config, }; +static const struct ls_pcie_drvdata ls1028a_drvdata = { + .lut_offset = 0x80000, + .ctrl_offset = 0x40000, + .big_endian = false, +}; + static const struct udevice_id ls_pcie_ids[] = { { .compatible = "fsl,ls-pcie" }, + { .compatible = "fsl,ls1028a-pcie", .data = (ulong)&ls1028a_drvdata }, { } }; From d4a64821fbc3a4da91a849655248c9b602424a15 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:23 +0200 Subject: [PATCH 42/62] arm: dts: ls1028a: remove num-lanes in the PCIe controller nodes This property is unused in the layerscape PCIe controller driver and not present in the linux device tree. Remove it to be similarly. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 435b965d00..3ef710bb3d 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -351,7 +351,6 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ @@ -365,7 +364,6 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ From 938d9355e612a90f17b5ce81d2c053ade553cb26 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:24 +0200 Subject: [PATCH 43/62] arm: dts: ls1028a: move the PCI I/O window to match To make the synchronization of the u-boot device tree with the one from linux easier, move the I/O window to the one which is specified in the linux device tree. The actual value shouldn't matter as long as it mapped to the corresponding memory window of the PCIe controller which is a 32GiB window at 80_0000_0000h (first controller) or 88_0000_0000h (second controller). Signed-off-by: Michael Walle Reviewed-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 3ef710bb3d..f11e75032b 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -352,7 +352,7 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; @@ -365,7 +365,7 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; From d08011d7f9b4dfb846b61dbdd5ced92d0ba2a259 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:25 +0200 Subject: [PATCH 44/62] arm: dts: ls1028a: disable the PCIe controller by default Disable the PCIe controllers by default, just like in the linux device tree. But there is one catch, for linux they are enabled in-place by the bootloader. Obviously, this doesn't work for the bootloader. Thus we explicitly enable the controllers in the -u-boot.dtsi files. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 13 +++++++++++++ arch/arm/dts/fsl-ls1028a-qds.dtsi | 8 ++++++++ arch/arm/dts/fsl-ls1028a-rdb.dts | 8 ++++++++ arch/arm/dts/fsl-ls1028a.dtsi | 2 ++ 4 files changed, 31 insertions(+) diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index 68a3e0b7aa..37382e09f1 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -297,6 +297,19 @@ u-boot,dm-pre-reloc; }; +/* + * u-boot will enable the device in the linux device tree in place. Because + * we are using the linux device tree, we have to enable the PCI controller + * ourselves. + */ +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + &soc { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index babd8445ee..0da0a7bc5d 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -240,6 +240,14 @@ status = "okay"; }; +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index 18ee363d75..537ebbc697 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -122,6 +122,14 @@ status = "okay"; }; +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index f11e75032b..d2f558d208 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -354,6 +354,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + status = "disabled"; }; pcie2: pcie@3500000 { @@ -367,6 +368,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + status = "disabled"; }; cluster1_core0_watchdog: wdt@c000000 { From 7f900eabf7d665ccd1ae8cdf7743a0ea46ec13b2 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:26 +0200 Subject: [PATCH 45/62] arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linux Now that everything is prepared, copy the fsl-ls1028a.dtsi from the linux kernel v5.14.12. Notable changes: - second watchdog added - the number of chip selects of the SPI controller is now correct and reflects what the hardware offers - the LPUARTs have the correct clock parent - USB controllers are enabled by default, which was already the case before this sync because all board enabled all the USB controller nodes. A linux patch to fix this is pending. - the eSDHC controller changes from big-endian to little-endian, but that property seems to be not used at all. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1028a.dtsi | 866 ++++++++++++++++-- .../dt-bindings/clock/fsl,qoriq-clockgen.h | 15 + 2 files changed, 788 insertions(+), 93 deletions(-) create mode 100644 include/dt-bindings/clock/fsl,qoriq-clockgen.h diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index d2f558d208..06b36cc658 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -1,12 +1,16 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * NXP ls1028a SOC common device tree source + * Device Tree Include file for NXP Layerscape-1028A family SoC. * - * Copyright 2019-2020 NXP + * Copyright 2018-2020 NXP + * + * Harninder Rai * */ +#include #include +#include / { compatible = "fsl,ls1028a"; @@ -14,6 +18,54 @@ #address-cells = <2>; #size-cells = <2>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0>; + enable-method = "psci"; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PW20>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x1>; + enable-method = "psci"; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PW20>; + #cooling-cells = <2>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + idle-states { + /* + * PSCI node is not added default, U-boot will add missing + * parts if it determines to use PSCI. + */ + entry-method = "psci"; + + CPU_PW20: cpu-pw20 { + compatible = "arm,idle-state"; + idle-state-name = "PW20"; + arm,psci-suspend-param = <0x0>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -21,14 +73,33 @@ clock-output-names = "sysclk"; }; - gic: interrupt-controller@6000000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06040000 0 0x40000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; + osc_27m: clock-osc-27m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "phy_27m"; + }; + + dpclk: clock-controller@f1f0000 { + compatible = "fsl,ls1028a-plldig"; + reg = <0x0 0xf1f0000 0x0 0xffff>; + #clock-cells = <0>; + clocks = <&osc_27m>; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; + + reboot { + compatible ="syscon-reboot"; + regmap = <&rst>; + offset = <0>; + mask = <0x02>; }; timer { @@ -43,13 +114,123 @@ IRQ_TYPE_LEVEL_LOW)>; }; + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + gic: interrupt-controller@6000000 { + compatible= "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ + #interrupt-cells= <3>; + interrupt-controller; + interrupts = ; + its: gic-its@6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ + }; + }; + + thermal-zones { + ddr-controller { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>; + + trips { + ddr-ctrler-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + ddr-ctrler-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + core-cluster { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + + trips { + core_cluster_alert: core-cluster-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core_cluster_crit: core-cluster-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; - clockgen: clocking@1300000 { + ddr: memory-controller@1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = ; + little-endian; + }; + + dcfg: syscon@1e00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; + reg = <0x0 0x1e00000 0x0 0x10000>; + ranges = <0x0 0x0 0x1e00000 0x10000>; + little-endian; + + fspi_clk: clock-controller@900 { + compatible = "fsl,ls1028a-flexspi-clk"; + reg = <0x900 0x4>; + #clock-cells = <0>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; + clock-output-names = "fspi_clk"; + }; + }; + + rst: syscon@1e60000 { + compatible = "syscon"; + reg = <0x0 0x1e60000 0x0 0x10000>; + little-endian; + }; + + scfg: syscon@1fc0000 { + compatible = "fsl,ls1028a-scfg", "syscon"; + reg = <0x0 0x1fc0000 0x0 0x10000>; + big-endian; + }; + + clockgen: clock-controller@1300000 { compatible = "fsl,ls1028a-clockgen"; reg = <0x0 0x1300000 0x0 0xa0000>; #clock-cells = <2>; @@ -62,8 +243,8 @@ #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -73,8 +254,8 @@ #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -84,8 +265,8 @@ #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -95,8 +276,8 @@ #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -106,8 +287,8 @@ #size-cells = <0>; reg = <0x0 0x2040000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -117,8 +298,8 @@ #size-cells = <0>; reg = <0x0 0x2050000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -128,8 +309,8 @@ #size-cells = <0>; reg = <0x0 0x2060000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; @@ -139,152 +320,237 @@ #size-cells = <0>; reg = <0x0 0x2070000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; - fspi: flexspi@20c0000 { + fspi: spi@20c0000 { compatible = "nxp,lx2160a-fspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "fspi_en", "fspi"; interrupts = ; + clocks = <&fspi_clk>, <&fspi_clk>; + clock-names = "fspi_en", "fspi"; status = "disabled"; }; - dspi0: dspi@2100000 { + dspi0: spi@2100000 { compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&clockgen 4 0>; - spi-num-chipselects = <5>; - litte-endian; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + dmas = <&edma0 0 62>, <&edma0 0 60>; + dma-names = "tx", "rx"; + spi-num-chipselects = <4>; + little-endian; status = "disabled"; }; - dspi1: dspi@2110000 { + dspi1: spi@2110000 { compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2110000 0x0 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&clockgen 4 0>; - spi-num-chipselects = <5>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + dmas = <&edma0 0 58>, <&edma0 0 56>; + dma-names = "tx", "rx"; + spi-num-chipselects = <4>; little-endian; status = "disabled"; }; - dspi2: dspi@2120000 { + dspi2: spi@2120000 { compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2120000 0x0 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&clockgen 4 0>; - spi-num-chipselects = <5>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + dmas = <&edma0 0 54>, <&edma0 0 2>; + dma-names = "tx", "rx"; + spi-num-chipselects = <3>; little-endian; status = "disabled"; }; - esdhc: esdhc@2140000 { - compatible = "fsl,esdhc"; + esdhc: mmc@2140000 { + compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; interrupts = ; - big-endian; + clock-frequency = <0>; /* fixed up by bootloader */ + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; bus-width = <4>; status = "disabled"; }; - esdhc1: esdhc@2150000 { - compatible = "fsl,esdhc"; + esdhc1: mmc@2150000 { + compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; reg = <0x0 0x2150000 0x0 0x10000>; interrupts = ; - big-endian; + clock-frequency = <0>; /* fixed up by bootloader */ + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; + voltage-ranges = <1800 1800>; + sdhci,auto-cmd12; non-removable; + little-endian; bus-width = <4>; status = "disabled"; }; + can0: can@2180000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@2190000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + duart0: serial@21c0500 { - device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; + reg = <0x00 0x21c0500 0x0 0x100>; interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; duart1: serial@21c0600 { - device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; + reg = <0x00 0x21c0600 0x0 0x100>; interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; + lpuart0: serial@2260000 { compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x2260000 0x0 0x1000>; - interrupts = <0 232 0x4>; - clocks = <&sysclk>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; + dma-names = "rx","tx"; + dmas = <&edma0 1 32>, + <&edma0 1 33>; status = "disabled"; }; lpuart1: serial@2270000 { compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x2270000 0x0 0x1000>; - interrupts = <0 233 0x4>; - clocks = <&sysclk>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; + dma-names = "rx","tx"; + dmas = <&edma0 1 30>, + <&edma0 1 31>; status = "disabled"; }; lpuart2: serial@2280000 { compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x2280000 0x0 0x1000>; - interrupts = <0 234 0x4>; - clocks = <&sysclk>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; + dma-names = "rx","tx"; + dmas = <&edma0 1 28>, + <&edma0 1 29>; status = "disabled"; }; lpuart3: serial@2290000 { compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x2290000 0x0 0x1000>; - interrupts = <0 235 0x4>; - clocks = <&sysclk>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; + dma-names = "rx","tx"; + dmas = <&edma0 1 26>, + <&edma0 1 27>; status = "disabled"; }; lpuart4: serial@22a0000 { compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x22a0000 0x0 0x1000>; - interrupts = <0 236 0x4>; - clocks = <&sysclk>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; + dma-names = "rx","tx"; + dmas = <&edma0 1 24>, + <&edma0 1 25>; status = "disabled"; }; lpuart5: serial@22b0000 { compatible = "fsl,ls1028a-lpuart"; reg = <0x0 0x22b0000 0x0 0x1000>; - interrupts = <0 237 0x4>; - clocks = <&sysclk>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; clock-names = "ipg"; + dma-names = "rx","tx"; + dmas = <&edma0 1 22>, + <&edma0 1 23>; status = "disabled"; }; + edma0: dma-controller@22c0000 { + #dma-cells = <2>; + compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; + reg = <0x0 0x22c0000 0x0 0x10000>, + <0x0 0x22d0000 0x0 0x10000>, + <0x0 0x22e0000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + }; + gpio1: gpio@2300000 { compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; @@ -318,28 +584,34 @@ little-endian; }; - usb0: usb3@3100000 { + usb0: usb@3100000 { compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; dr_mode = "host"; - status = "disabled"; + snps,dis_rxdet_inp3_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; - usb1: usb3@3110000 { + usb1: usb@3110000 { compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = ; dr_mode = "host"; - status = "disabled"; + snps,dis_rxdet_inp3_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; sata: sata@3200000 { compatible = "fsl,ls1028a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ - 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ + reg = <0x0 0x3200000 0x0 0x10000>, + <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; status = "disabled"; }; @@ -348,12 +620,25 @@ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; + interrupts = , /* PME interrupt */ + ; /* aer interrupt */ + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; + num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ status = "disabled"; }; @@ -362,44 +647,380 @@ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; + interrupts = , + ; + interrupt-names = "pme", "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; + num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ status = "disabled"; }; - cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc000000 0x0 0x1000>; + smmu: iommu@5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #global-interrupts = <8>; + #iommu-cells = <1>; + stream-match-mask = <0x7c00>; + /* global secure fault */ + interrupts = , + /* combined secure interrupt */ + , + /* global non-secure fault */ + , + /* combined non-secure interrupt */ + , + /* performance counter interrupts 0-7 */ + , , + , , + /* per context interrupt, 64 interrupts */ + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; }; - pcie@1f0000000 { + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = ; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = ; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = ; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + }; + }; + + qdma: dma-controller@8380000 { + compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ + <0x0 0x8390000 0x0 0x10000>, /* Status regs */ + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ + interrupts = , + , + , + , + ; + interrupt-names = "qdma-error", "qdma-queue0", + "qdma-queue1", "qdma-queue2", "qdma-queue3"; + dma-channels = <8>; + block-number = <1>; + block-offset = <0x10000>; + fsl,dma-queues = <2>; + status-sizes = <64>; + queue-sizes = <64 64>; + }; + + cluster1_core0_watchdog: watchdog@c000000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core1_watchdog: watchdog@c010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + sai1: audio-controller@f100000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0xf100000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 4>, + <&edma0 1 3>; + fsl,sai-asynchronous; + status = "disabled"; + }; + + sai2: audio-controller@f110000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0xf110000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 6>, + <&edma0 1 5>; + fsl,sai-asynchronous; + status = "disabled"; + }; + + sai3: audio-controller@f120000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0xf120000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 8>, + <&edma0 1 7>; + fsl,sai-asynchronous; + status = "disabled"; + }; + + sai4: audio-controller@f130000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0xf130000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 10>, + <&edma0 1 9>; + fsl,sai-asynchronous; + status = "disabled"; + }; + + sai5: audio-controller@f140000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0xf140000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 12>, + <&edma0 1 11>; + fsl,sai-asynchronous; + status = "disabled"; + }; + + sai6: audio-controller@f150000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0xf150000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 14>, + <&edma0 1 13>; + fsl,sai-asynchronous; + status = "disabled"; + }; + + tmu: tmu@1f80000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f80000 0x0 0x10000>; + interrupts = <0 23 0x4>; + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; + fsl,tmu-calibration = <0x00000000 0x00000024 + 0x00000001 0x0000002b + 0x00000002 0x00000031 + 0x00000003 0x00000038 + 0x00000004 0x0000003f + 0x00000005 0x00000045 + 0x00000006 0x0000004c + 0x00000007 0x00000053 + 0x00000008 0x00000059 + 0x00000009 0x00000060 + 0x0000000a 0x00000066 + 0x0000000b 0x0000006d + + 0x00010000 0x0000001c + 0x00010001 0x00000024 + 0x00010002 0x0000002c + 0x00010003 0x00000035 + 0x00010004 0x0000003d + 0x00010005 0x00000045 + 0x00010006 0x0000004d + 0x00010007 0x00000055 + 0x00010008 0x0000005e + 0x00010009 0x00000066 + 0x0001000a 0x0000006e + + 0x00020000 0x00000018 + 0x00020001 0x00000022 + 0x00020002 0x0000002d + 0x00020003 0x00000038 + 0x00020004 0x00000043 + 0x00020005 0x0000004d + 0x00020006 0x00000058 + 0x00020007 0x00000063 + 0x00020008 0x0000006e + + 0x00030000 0x00000010 + 0x00030001 0x0000001c + 0x00030002 0x00000029 + 0x00030003 0x00000036 + 0x00030004 0x00000042 + 0x00030005 0x0000004f + 0x00030006 0x0000005b + 0x00030007 0x00000068>; + little-endian; + #thermal-sensor-cells = <1>; + }; + + pcie@1f0000000 { /* Integrated Endpoint Root Complex */ compatible = "pci-host-ecam-generic"; - /* ECAM bus 0, HW has more space reserved but not populated */ - bus-range = <0x0 0x0>; reg = <0x01 0xf0000000 0x0 0x100000>; #address-cells = <3>; #size-cells = <2>; + msi-parent = <&its>; device_type = "pci"; - ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>; + bus-range = <0x0 0x0>; + dma-coherent; + msi-map = <0 &its 0x17 0xe>; + iommu-map = <0 &smmu 0x17 0xe>; + /* PF0-6 BAR0 - non-prefetchable memory */ + ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 + /* PF0-6 BAR2 - prefetchable memory */ + 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 + /* PF0: VF0-1 BAR0 - non-prefetchable memory */ + 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 + /* PF0: VF0-1 BAR2 - prefetchable memory */ + 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 + /* PF1: VF0-1 BAR0 - non-prefetchable memory */ + 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 + /* PF1: VF0-1 BAR2 - prefetchable memory */ + 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 + /* BAR4 (PF5) - non-prefetchable memory */ + 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; - enetc_port0: pci@0,0 { + enetc_port0: ethernet@0,0 { + compatible = "fsl,enetc"; reg = <0x000000 0 0 0 0>; status = "disabled"; }; - enetc_port1: pci@0,1 { + enetc_port1: ethernet@0,1 { + compatible = "fsl,enetc"; reg = <0x000100 0 0 0 0>; status = "disabled"; }; - enetc_port2: pci@0,2 { + enetc_port2: ethernet@0,2 { + compatible = "fsl,enetc"; reg = <0x000200 0 0 0 0>; - status = "disabled"; phy-mode = "internal"; + status = "disabled"; fixed-link { speed = <2500>; @@ -407,26 +1028,32 @@ }; }; - enetc_mdio_pf3: pci@0,3 { - #address-cells=<0>; - #size-cells=<1>; + enetc_mdio_pf3: mdio@0,3 { + compatible = "fsl,enetc-mdio"; reg = <0x000300 0 0 0 0>; - status = "disabled"; - - fixed-link { - speed = <1000>; - full-duplex; - }; + #address-cells = <1>; + #size-cells = <0>; }; - mscc_felix: pci@0,5 { + ethernet@0,4 { + compatible = "fsl,enetc-ptp"; + reg = <0x000400 0 0 0 0>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; + little-endian; + fsl,extts-fifo; + }; + + mscc_felix: ethernet-switch@0,5 { reg = <0x000500 0 0 0 0>; + /* IEP INT_B */ + interrupts = ; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; + /* External ports */ mscc_felix_port0: port@0 { reg = <0>; status = "disabled"; @@ -447,6 +1074,7 @@ status = "disabled"; }; + /* Internal ports */ mscc_felix_port4: port@4 { reg = <4>; phy-mode = "internal"; @@ -467,15 +1095,67 @@ speed = <1000>; full-duplex; }; - }; }; }; - enetc_port3: pci@0,6 { + enetc_port3: ethernet@0,6 { + compatible = "fsl,enetc"; reg = <0x000600 0 0 0 0>; - status = "disabled"; phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + rcec@1f,0 { + reg = <0x00f800 0 0 0 0>; + /* IEP INT_A */ + interrupts = ; + }; + }; + + /* Integrated Endpoint Register Block */ + ierb@1f0800000 { + compatible = "fsl,ls1028a-enetc-ierb"; + reg = <0x01 0xf0800000 0x0 0x10000>; + }; + + rcpm: power-controller@1e34040 { + compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x1c>; + #fsl,rcpm-wakeup-cells = <7>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,ls1028a-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; + interrupts = ; + }; + }; + + malidp0: display@f080000 { + compatible = "arm,mali-dp500"; + reg = <0x0 0xf080000 0x0 0x10000>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, + <0 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "DE", "SE"; + clocks = <&dpclk>, + <&clockgen QORIQ_CLK_HWACCEL 2>, + <&clockgen QORIQ_CLK_HWACCEL 2>, + <&clockgen QORIQ_CLK_HWACCEL 2>; + clock-names = "pxlclk", "mclk", "aclk", "pclk"; + arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; + arm,malidp-arqos-value = <0xd000d000>; + + port { + dp0_out: endpoint { + }; }; }; diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h b/include/dt-bindings/clock/fsl,qoriq-clockgen.h new file mode 100644 index 0000000000..ddec7d0bdc --- /dev/null +++ b/include/dt-bindings/clock/fsl,qoriq-clockgen.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H +#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H + +#define QORIQ_CLK_SYSCLK 0 +#define QORIQ_CLK_CMUX 1 +#define QORIQ_CLK_HWACCEL 2 +#define QORIQ_CLK_FMAN 3 +#define QORIQ_CLK_PLATFORM_PLL 4 +#define QORIQ_CLK_CORECLK 5 + +#define QORIQ_CLK_PLL_DIV(x) ((x) - 1) + +#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */ From c7155d29fb041143e33e0b2d691699e614d84936 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 13 Oct 2021 18:14:27 +0200 Subject: [PATCH 46/62] arm: dts: sl28: sync dtbs Copy the board device tree files from linux v5.14. On top of the v5.14 dtbs the changes of these two patches are included here which are needed for u-boot: https://lore.kernel.org/linux-devicetree/20210831134013.1625527-7-michael@walle.cc/ https://lore.kernel.org/linux-devicetree/20210831134013.1625527-8-michael@walle.cc/ At the time of this writing the patches were accepted and will be included in 5.15. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- .../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 12 +- .../arm/dts/fsl-ls1028a-kontron-sl28-var1.dts | 31 +-- .../fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi | 8 + .../arm/dts/fsl-ls1028a-kontron-sl28-var2.dts | 40 +-- .../arm/dts/fsl-ls1028a-kontron-sl28-var4.dts | 16 +- arch/arm/dts/fsl-ls1028a-kontron-sl28.dts | 252 +++++++++++++++--- 6 files changed, 266 insertions(+), 93 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index 37382e09f1..d4b833284e 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -4,12 +4,9 @@ / { aliases { - mmc0 = &esdhc1; - mmc1 = &esdhc; i2c0 = &i2c0; i2c1 = &i2c3; i2c2 = &i2c4; - rtc0 = &rtc; ethernet2 = &enetc_port2; ethernet3 = &enetc_port3; }; @@ -265,11 +262,6 @@ }; #endif -&i2c0 { - rtc: rtc@32 { - }; -}; - &fspi { u-boot,dm-pre-reloc; flash@0 { @@ -310,6 +302,10 @@ status = "okay"; }; +&sata { + status = "okay"; +}; + &soc { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts index ba2e4de96d..7cd29ab970 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts @@ -8,7 +8,7 @@ * None of the four SerDes lanes are used by the module, instead they are * all led out to the carrier for customer use. * - * Copyright (C) 2020 Michael Walle + * Copyright (C) 2021 Michael Walle * */ @@ -21,28 +21,17 @@ compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a"; }; -&enetc_port0 { - status = "disabled"; - /delete-property/ phy-handle; -}; - -&enetc_port1 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -/delete-node/ &phy0; &enetc_mdio_pf3 { + /* Delete unused phy node */ + /delete-node/ ethernet-phy@5; + phy0: ethernet-phy@4 { reg = <0x4>; eee-broken-1000t; eee-broken-100tx; - qca,clk-out-frequency = <125000000>; qca,clk-out-strength = ; qca,keep-pll-enabled; - vddio-supply = <&vddio>; vddio: vddio-regulator { @@ -56,3 +45,15 @@ }; }; }; + +&enetc_port0 { + status = "disabled"; + /* Delete the phy-handle to the old phy0 label */ + /delete-property/ phy-handle; +}; + +&enetc_port1 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi index 4e0ce3f77d..c010ea0dc7 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi @@ -7,3 +7,11 @@ ethernet1 = &mscc_felix_port1; }; }; + +&mscc_felix_port0 { + label = "gbe0"; +}; + +&mscc_felix_port1 { + label = "gbe1"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts index db80874f4e..330e34f933 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts @@ -2,10 +2,10 @@ /* * Device Tree file for the Kontron SMARC-sAL28 board. * - * This is for the network variant 2 which has no ethernet support in the - * bootloader. + * This is for the network variant 2 which has two ethernet ports. These + * ports are connected to the internal switch. * - * Copyright (C) 2020 Michael Walle + * Copyright (C) 2021 Michael Walle * */ @@ -17,8 +17,21 @@ compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a"; }; +&enetc_mdio_pf3 { + phy1: ethernet-phy@4 { + reg = <0x4>; + eee-broken-1000t; + eee-broken-100tx; + }; +}; + &enetc_port0 { status = "disabled"; + /* + * In the base device tree the PHY at address 5 was assigned for + * this port. On this module this PHY is connected to a switch + * port instead. Therefore, delete the phy-handle property here. + */ /delete-property/ phy-handle; }; @@ -31,14 +44,16 @@ }; &mscc_felix_port0 { - label = "gbe0"; + label = "swp0"; + managed = "in-band-status"; phy-handle = <&phy0>; phy-mode = "sgmii"; status = "okay"; }; &mscc_felix_port1 { - label = "gbe1"; + label = "swp1"; + managed = "in-band-status"; phy-handle = <&phy1>; phy-mode = "sgmii"; status = "okay"; @@ -48,18 +63,3 @@ ethernet = <&enetc_port2>; status = "okay"; }; - -/delete-node/ &phy0; -&enetc_mdio_pf3 { - phy0: ethernet-phy@5 { - reg = <0x5>; - eee-broken-1000t; - eee-broken-100tx; - }; - - phy1: ethernet-phy@4 { - reg = <0x4>; - eee-broken-1000t; - eee-broken-100tx; - }; -}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts index 54d12ab992..9b5e92fb75 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts @@ -5,7 +5,7 @@ * This is for the network variant 4 which has two ethernet ports. It * extends the base and provides one more port connected via RGMII. * - * Copyright (C) 2019 Michael Walle + * Copyright (C) 2021 Michael Walle * */ @@ -18,22 +18,14 @@ compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; }; -&enetc_port1 { - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - &enetc_mdio_pf3 { phy1: ethernet-phy@4 { reg = <0x4>; eee-broken-1000t; eee-broken-100tx; - qca,clk-out-frequency = <125000000>; qca,clk-out-strength = ; qca,keep-pll-enabled; - vddio-supply = <&vddio>; vddio: vddio-regulator { @@ -47,3 +39,9 @@ }; }; }; + +&enetc_port1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts index 9ae70ba541..ab713b4949 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts @@ -2,23 +2,61 @@ /* * Device Tree file for the Kontron SMARC-sAL28 board. * - * Copyright (C) 2019 Michael Walle + * Copyright (C) 2021 Michael Walle * */ /dts-v1/; #include "fsl-ls1028a.dtsi" +#include +#include +#include / { model = "Kontron SMARC-sAL28"; compatible = "kontron,sl28", "fsl,ls1028a"; aliases { + crypto = &crypto; serial0 = &duart0; serial1 = &duart1; serial2 = &lpuart1; spi0 = &fspi; spi1 = &dspi2; + mmc0 = &esdhc1; + mmc1 = &esdhc; + rtc0 = &rtc; + rtc1 = &ftm_alarm0; + }; + + buttons0 { + compatible = "gpio-keys"; + + power-button { + interrupts-extended = <&sl28cpld_intc + 4 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + label = "Power"; + }; + + sleep-button { + interrupts-extended = <&sl28cpld_intc + 5 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + label = "Sleep"; + }; + }; + + buttons1 { + compatible = "gpio-keys-polled"; + poll-interval = <200>; + + lid-switch { + linux,input-type = ; + linux,code = ; + gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>; + label = "Lid"; + }; }; chosen { @@ -26,24 +64,37 @@ }; }; +&can0 { + status = "okay"; +}; + &dspi2 { status = "okay"; }; +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&enetc_mdio_pf3 { + phy0: ethernet-phy@5 { + reg = <0x5>; + eee-broken-1000t; + eee-broken-100tx; + }; +}; + &enetc_port0 { phy-handle = <&phy0>; phy-mode = "sgmii"; + managed = "in-band-status"; status = "okay"; }; -&enetc_port2 { - status = "disabled"; -}; - -&enetc_port3 { - status = "disabled"; -}; - &esdhc { sd-uhs-sdr104; sd-uhs-sdr50; @@ -63,8 +114,6 @@ status = "okay"; flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "jedec,spi-nor"; m25p,fast-read; spi-max-frequency = <133000000>; @@ -72,17 +121,167 @@ /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */ spi-rx-bus-width = <2>; /* 2 SPI Rx lines */ spi-tx-bus-width = <1>; /* 1 SPI Tx line */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x000000 0x010000>; + label = "rcw"; + read-only; + }; + + partition@10000 { + reg = <0x010000 0x1d0000>; + label = "failsafe bootloader"; + read-only; + }; + + partition@200000 { + reg = <0x200000 0x010000>; + label = "configuration store"; + }; + + partition@210000 { + reg = <0x210000 0x1d0000>; + label = "bootloader"; + }; + + partition@3e0000 { + reg = <0x3e0000 0x020000>; + label = "bootloader environment"; + }; + }; }; }; +&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "TDO", "TCK", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "TMS", "TDI", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c0 { status = "okay"; - rtc@32 { + rtc: rtc@32 { compatible = "microcrystal,rv8803"; reg = <0x32>; }; + sl28cpld@4a { + compatible = "kontron,sl28cpld"; + reg = <0x4a>; + #address-cells = <1>; + #size-cells = <0>; + + watchdog@4 { + compatible = "kontron,sl28cpld-wdt"; + reg = <0x4>; + kontron,assert-wdt-timeout-pin; + }; + + hwmon@b { + compatible = "kontron,sl28cpld-fan"; + reg = <0xb>; + }; + + sl28cpld_pwm0: pwm@c { + compatible = "kontron,sl28cpld-pwm"; + reg = <0xc>; + #pwm-cells = <2>; + }; + + sl28cpld_pwm1: pwm@e { + compatible = "kontron,sl28cpld-pwm"; + reg = <0xe>; + #pwm-cells = <2>; + }; + + sl28cpld_gpio0: gpio@10 { + compatible = "kontron,sl28cpld-gpio"; + reg = <0x10>; + interrupts-extended = <&gpio2 6 + IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N", + "GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N", + "GPIO4_HDA_RST_N", "GPIO5_PWM_OUT", + "GPIO6_TACHIN", "GPIO7"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sl28cpld_gpio1: gpio@15 { + compatible = "kontron,sl28cpld-gpio"; + reg = <0x15>; + interrupts-extended = <&gpio2 6 + IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "GPIO8", "GPIO9", "GPIO10", "GPIO11", + "", "", "", ""; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sl28cpld_gpio2: gpio@1a { + compatible = "kontron,sl28cpld-gpo"; + reg = <0x1a>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "LCD0 voltage enable", + "LCD0 backlight enable", + "eMMC reset", "LVDS bridge reset", + "LVDS bridge power-down", + "SDIO power enable", + "", ""; + }; + + sl28cpld_gpio3: gpio@1b { + compatible = "kontron,sl28cpld-gpi"; + reg = <0x1b>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "Power button", "Force recovery", "Sleep", + "Battery low", "Lid state", "Charging", + "Charger present", ""; + }; + + sl28cpld_intc: interrupt-controller@1c { + compatible = "kontron,sl28cpld-intc"; + reg = <0x1c>; + interrupts-extended = <&gpio2 6 + IRQ_TYPE_EDGE_FALLING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + eeprom@50 { compatible = "atmel,24c32"; reg = <0x50>; @@ -107,32 +306,3 @@ &lpuart1 { status = "okay"; }; - -&enetc_mdio_pf3 { - status = "okay"; - phy0: ethernet-phy@5 { - reg = <0x5>; - eee-broken-1000t; - eee-broken-100tx; - }; -}; - -&sata { - status = "okay"; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; From b8ec9458a35167ab689b3ebfba169f520e1064c4 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 15 Oct 2021 15:15:17 +0200 Subject: [PATCH 47/62] dm: core: add ofnode_for_each_compatible_node() Add a helper to iterate over all nodes with a given compatible string. Signed-off-by: Michael Walle Reviewed-by: Simon Glass Reviewed-by: Priyanka Jain --- include/dm/ofnode.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 6a714d0c7b..0f680e5aa6 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -1009,6 +1009,30 @@ ofnode ofnode_by_prop_value(ofnode from, const char *propname, ofnode_valid(node); \ node = ofnode_next_subnode(node)) +/** + * ofnode_for_each_compatible_node() - iterate over all nodes with a given + * compatible string + * + * @node: child node (ofnode, lvalue) + * @compat: compatible string to match + * + * This is a wrapper around a for loop and is used like so: + * + * ofnode node; + * + * ofnode_for_each_compatible_node(node, parent, compatible) { + * Use node + * ... + * } + * + * Note that this is implemented as a macro and @node is used as + * iterator in the loop. + */ +#define ofnode_for_each_compatible_node(node, compat) \ + for (node = ofnode_by_compatible(ofnode_null(), compat); \ + ofnode_valid(node); \ + node = ofnode_by_compatible(node, compat)) + /** * ofnode_get_child_count() - get the child count of a ofnode * From bce039acf2661b1484aeee3704100b645a3d2198 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 15 Oct 2021 15:15:18 +0200 Subject: [PATCH 48/62] test: dm: add test for ofnode_for_each_compatible_node() Check that all matching nodes have the correct compatible and that there is at least one match. Signed-off-by: Michael Walle Reviewed-by: Simon Glass Reviewed-by: Priyanka Jain --- test/dm/ofnode.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index 49efabe871..cea0746bb3 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -333,3 +333,21 @@ static int dm_test_ofnode_conf(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_ofnode_conf, 0); + +static int dm_test_ofnode_for_each_compatible_node(struct unit_test_state *uts) +{ + const char compatible[] = "denx,u-boot-fdt-test"; + bool found = false; + ofnode node; + + ofnode_for_each_compatible_node(node, compatible) { + ut_assert(ofnode_device_is_compatible(node, compatible)); + found = true; + } + + /* There should be at least one matching node */ + ut_assert(found); + + return 0; +} +DM_TEST(dm_test_ofnode_for_each_compatible_node, UT_TESTF_SCAN_FDT); From f53e102e12c0e1bdda035be1aa5ec59c9787a21a Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 15 Oct 2021 15:15:19 +0200 Subject: [PATCH 49/62] armv8: fsl-layerscape: rework the dwc3 snooping enable code Instead of looking at all USB (host) devices, just search all DWC3 device tree nodes. This will (1) fix a panic if of_match is zero and (2) also apply the fixup if the controller is in peripheral mode. Both happen when the DWC3 USB controller driver is used. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 28 ++++++++++++------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index a08ed3f544..d3a5cfaac1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -929,25 +929,23 @@ __weak int fsl_board_late_init(void) #define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \ << DWC3_GSBUSCFG0_CACHETYPE_SHIFT) -void enable_dwc3_snooping(void) +static void enable_dwc3_snooping(void) { - int ret; - u32 val; - struct udevice *bus; - struct uclass *uc; + static const char * const compatibles[] = { + "fsl,layerscape-dwc3", + "fsl,ls1028a-dwc3", + }; fdt_addr_t dwc3_base; + ofnode node; + u32 val; + int i; - ret = uclass_get(UCLASS_USB, &uc); - if (ret) - return; - - uclass_foreach_dev(bus, uc) { - if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) { - dwc3_base = devfdt_get_addr(bus); - if (dwc3_base == FDT_ADDR_T_NONE) { - dev_err(bus, "dwc3 regs missing\n"); + for (i = 0; i < ARRAY_SIZE(compatibles); i++) { + ofnode_for_each_compatible_node(node, compatibles[i]) { + dwc3_base = ofnode_get_addr(node); + if (dwc3_base == FDT_ADDR_T_NONE) continue; - } + val = in_le32(dwc3_base + DWC3_GSBUSCFG0); val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0); val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222); From 7f79a2c2357d16fc9dd08e761e931a4f2169d625 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 15 Oct 2021 15:15:20 +0200 Subject: [PATCH 50/62] usb: common: silence dubious errors Both dr_mode and maximum-speed properties are usually optional. Drivers will still try to fetch the properties nonetheless, which leads to error messages, although they are no errors. Change pr_err() to pr_debug(). Signed-off-by: Michael Walle Reviewed-by: Simon Glass Reviewed-by: Priyanka Jain --- drivers/usb/common/common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c index 43564c9fba..ee0c064f1f 100644 --- a/drivers/usb/common/common.c +++ b/drivers/usb/common/common.c @@ -29,7 +29,7 @@ enum usb_dr_mode usb_get_dr_mode(ofnode node) dr_mode = ofnode_read_string(node, "dr_mode"); if (!dr_mode) { - pr_err("usb dr_mode not found\n"); + pr_debug("usb dr_mode not found\n"); return USB_DR_MODE_UNKNOWN; } @@ -64,7 +64,7 @@ enum usb_device_speed usb_get_maximum_speed(ofnode node) max_speed = ofnode_read_string(node, "maximum-speed"); if (!max_speed) { - pr_err("usb maximum-speed not found\n"); + pr_debug("usb maximum-speed not found\n"); return USB_SPEED_UNKNOWN; } From d274cbbc1cef8909d47b3f797fef3667bc170620 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 15 Oct 2021 15:15:21 +0200 Subject: [PATCH 51/62] usb: dwc3: Add frame length adjustment quirk [backport from linux commit db2be4e9e30c6e43e48c5749d3fc74cee0a6bbb3] Add adjust_frame_length_quirk for writing to fladj register which adjusts (micro)frame length to value provided by "snps,quirk-frame-length-adjustment" property thus avoiding USB 2.0 devices to time-out over a longer run Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- drivers/usb/dwc3/core.c | 26 ++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 6 ++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index dfd7cf683f..4fb6b59d50 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -93,6 +93,27 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) return 0; } +/* + * dwc3_frame_length_adjustment - Adjusts frame length if required + * @dwc3: Pointer to our controller context structure + * @fladj: Value of GFLADJ_30MHZ to adjust frame length + */ +static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj) +{ + u32 reg; + + if (dwc->revision < DWC3_REVISION_250A) + return; + + if (fladj == 0) + return; + + reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); + reg &= ~DWC3_GFLADJ_30MHZ_MASK; + reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj; + dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); +} + /** * dwc3_free_one_event_buffer - Frees one event buffer * @dwc: Pointer to our controller context structure @@ -569,6 +590,9 @@ static int dwc3_core_init(struct dwc3 *dwc) if (ret) goto err1; + /* Adjust Frame Length */ + dwc3_frame_length_adjustment(dwc, dwc->fladj); + return 0; err1: @@ -958,6 +982,8 @@ void dwc3_of_parse(struct dwc3 *dwc) dwc->hird_threshold = hird_threshold | (dwc->is_utmi_l1_suspend << 4); + + dev_read_u32(dev, "snps,quirk-frame-length-adjustment", &dwc->fladj); } int dwc3_init(struct dwc3 *dwc) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 1502cb859a..62e4df74fa 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -115,6 +115,7 @@ #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) #define DWC3_GHWPARAMS8 0xc600 +#define DWC3_GFLADJ 0xc630 /* Device Registers */ #define DWC3_DCFG 0xc700 @@ -233,6 +234,10 @@ /* Global HWPARAMS6 Register */ #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) +/* Global Frame Length Adjustment Register */ +#define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7) +#define DWC3_GFLADJ_30MHZ_MASK 0x3f + /* Device Configuration Register */ #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) @@ -812,6 +817,7 @@ struct dwc3 { u8 test_mode_nr; u8 lpm_nyet_threshold; u8 hird_threshold; + u32 fladj; unsigned delayed_status:1; unsigned ep0_bounced:1; From f150b8d28b4eab267fdd4af4a2d0a41443702cc5 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 15 Oct 2021 15:15:22 +0200 Subject: [PATCH 52/62] usb: dwc3: Enable undefined length INCR burst type [backport from linux commit d9612c2f0449e24983a8b689603210486a930c90] Enable the undefined length INCR burst type and set INCRx. Different platform may has the different burst size type. In order to get best performance, we need to tune the burst size to one special value, instead of the default value. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- drivers/usb/dwc3/core.c | 69 +++++++++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 16 ++++++++++ 2 files changed, 85 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 4fb6b59d50..ce1c0e88c2 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -462,6 +462,53 @@ static void dwc3_phy_setup(struct dwc3 *dwc) mdelay(100); } +/* set global incr burst type configuration registers */ +static void dwc3_set_incr_burst_type(struct dwc3 *dwc) +{ + struct udevice *dev = dwc->dev; + u32 cfg; + + if (!dwc->incrx_size) + return; + + cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); + + /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ + cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; + if (dwc->incrx_mode) + cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; + switch (dwc->incrx_size) { + case 256: + cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; + break; + case 128: + cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; + break; + case 64: + cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; + break; + case 32: + cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; + break; + case 16: + cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; + break; + case 8: + cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; + break; + case 4: + cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; + break; + case 1: + break; + default: + dev_err(dev, "Invalid property\n"); + break; + } + + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); +} + /** * dwc3_core_init - Low-level initialization of DWC3 Core * @dwc: Pointer to our controller context structure @@ -593,6 +640,8 @@ static int dwc3_core_init(struct dwc3 *dwc) /* Adjust Frame Length */ dwc3_frame_length_adjustment(dwc, dwc->fladj); + dwc3_set_incr_burst_type(dwc); + return 0; err1: @@ -916,6 +965,8 @@ void dwc3_of_parse(struct dwc3 *dwc) u8 lpm_nyet_threshold; u8 tx_de_emphasis; u8 hird_threshold; + u32 val; + int i; /* default to highest possible threshold */ lpm_nyet_threshold = 0xff; @@ -984,6 +1035,24 @@ void dwc3_of_parse(struct dwc3 *dwc) | (dwc->is_utmi_l1_suspend << 4); dev_read_u32(dev, "snps,quirk-frame-length-adjustment", &dwc->fladj); + + /* + * Handle property "snps,incr-burst-type-adjustment". + * Get the number of value from this property: + * result <= 0, means this property is not supported. + * result = 1, means INCRx burst mode supported. + * result > 1, means undefined length burst mode supported. + */ + dwc->incrx_mode = INCRX_BURST_MODE; + dwc->incrx_size = 0; + for (i = 0; i < 8; i++) { + if (dev_read_u32_index(dev, "snps,incr-burst-type-adjustment", + i, &val)) + break; + + dwc->incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; + dwc->incrx_size = max(dwc->incrx_size, val); + } } int dwc3_init(struct dwc3 *dwc) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 62e4df74fa..d7cce3a861 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -139,6 +139,17 @@ /* Bit fields */ +/* Global SoC Bus Configuration INCRx Register 0 */ +#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ +#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ +#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ +#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ +#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ +#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ +#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ +#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff + /* Global Configuration Register */ #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) #define DWC3_GCTL_U2RSTECN (1 << 16) @@ -818,6 +829,8 @@ struct dwc3 { u8 lpm_nyet_threshold; u8 hird_threshold; u32 fladj; + u8 incrx_mode; + u32 incrx_size; unsigned delayed_status:1; unsigned ep0_bounced:1; @@ -855,6 +868,9 @@ struct dwc3 { struct list_head list; }; +#define INCRX_BURST_MODE 0 +#define INCRX_UNDEF_LENGTH_BURST_MODE 1 + /* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */ From 2b0b51d0bedf70ced90960eb029908d04c8e4d77 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 15 Oct 2021 15:15:23 +0200 Subject: [PATCH 53/62] usb: dwc3: add layerscape support Add support for the proper dwc3 device tree binding support as specified in the offical device tree spec. Initially, add support for the LS1028A support. Other SoCs should be easy to add by just adding the corresponding compatible string. Unfortunately, the device trees of all other layerscape SoCs are not converted and uses a wrong compatible string only known in u-boot. To maintain backwards compatibility with current u-boot device trees, add the generic "fsl,layerscape-dwc3" compatible string. OTG mode is not supported yet. The dr_mode in the devicetree will either have to be set to peripheral or host. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- drivers/usb/dwc3/Kconfig | 10 ++ drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-layerscape.c | 222 +++++++++++++++++++++++++++++ 3 files changed, 233 insertions(+) create mode 100644 drivers/usb/dwc3/dwc3-layerscape.c diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 93707e05fb..62aa65bf0c 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -53,6 +53,16 @@ config USB_DWC3_UNIPHIER Support of USB2/3 functionality in Socionext UniPhier platforms. Say 'Y' here if you have one such device. +config USB_DWC3_LAYERSCAPE + bool "Freescale Layerscape platform support" + depends on DM_USB && USB_DWC3 + depends on !USB_XHCI_FSL + help + Select this for Freescale Layerscape Platforms. + + Host and Peripheral operation modes are supported. OTG is not + supported. + menu "PHY Subsystem" config USB_DWC3_PHY_OMAP diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 6e3e024e97..0dd1ba87cd 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -11,5 +11,6 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o +obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o diff --git a/drivers/usb/dwc3/dwc3-layerscape.c b/drivers/usb/dwc3/dwc3-layerscape.c new file mode 100644 index 0000000000..79cf71f7a8 --- /dev/null +++ b/drivers/usb/dwc3/dwc3-layerscape.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Layerscape DWC3 Glue layer + * + * Copyright (C) 2021 Michael Walle + * + * Based on dwc3-generic.c. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "core.h" +#include "gadget.h" +#include + +struct dwc3_layerscape_plat { + fdt_addr_t base; + u32 maximum_speed; + enum usb_dr_mode dr_mode; +}; + +struct dwc3_layerscape_priv { + void *base; + struct dwc3 dwc3; + struct phy_bulk phys; +}; + +struct dwc3_layerscape_host_priv { + struct xhci_ctrl xhci_ctrl; + struct dwc3_layerscape_priv gen_priv; +}; + +static int dwc3_layerscape_probe(struct udevice *dev, + struct dwc3_layerscape_priv *priv) +{ + int rc; + struct dwc3_layerscape_plat *plat = dev_get_plat(dev); + struct dwc3 *dwc3 = &priv->dwc3; + + dwc3->dev = dev; + dwc3->maximum_speed = plat->maximum_speed; + dwc3->dr_mode = plat->dr_mode; + if (CONFIG_IS_ENABLED(OF_CONTROL)) + dwc3_of_parse(dwc3); + + rc = dwc3_setup_phy(dev, &priv->phys); + if (rc && rc != -ENOTSUPP) + return rc; + + priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE); + dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START; + + rc = dwc3_init(dwc3); + if (rc) { + unmap_physmem(priv->base, MAP_NOCACHE); + return rc; + } + + return 0; +} + +static int dwc3_layerscape_remove(struct udevice *dev, + struct dwc3_layerscape_priv *priv) +{ + struct dwc3 *dwc3 = &priv->dwc3; + + dwc3_remove(dwc3); + dwc3_shutdown_phy(dev, &priv->phys); + unmap_physmem(dwc3->regs, MAP_NOCACHE); + + return 0; +} + +static int dwc3_layerscape_of_to_plat(struct udevice *dev) +{ + struct dwc3_layerscape_plat *plat = dev_get_plat(dev); + ofnode node = dev_ofnode(dev); + + plat->base = dev_read_addr(dev); + + plat->maximum_speed = usb_get_maximum_speed(node); + if (plat->maximum_speed == USB_SPEED_UNKNOWN) { + dev_dbg(dev, "No USB maximum speed specified. Using super speed\n"); + plat->maximum_speed = USB_SPEED_SUPER; + } + + plat->dr_mode = usb_get_dr_mode(node); + if (plat->dr_mode == USB_DR_MODE_UNKNOWN) { + dev_err(dev, "Invalid usb mode setup\n"); + return -ENODEV; + } + + return 0; +} + +#if CONFIG_IS_ENABLED(DM_USB_GADGET) +int dm_usb_gadget_handle_interrupts(struct udevice *dev) +{ + struct dwc3_layerscape_priv *priv = dev_get_priv(dev); + + dwc3_gadget_uboot_handle_interrupt(&priv->dwc3); + + return 0; +} + +static int dwc3_layerscape_peripheral_probe(struct udevice *dev) +{ + struct dwc3_layerscape_priv *priv = dev_get_priv(dev); + + return dwc3_layerscape_probe(dev, priv); +} + +static int dwc3_layerscape_peripheral_remove(struct udevice *dev) +{ + struct dwc3_layerscape_priv *priv = dev_get_priv(dev); + + return dwc3_layerscape_remove(dev, priv); +} + +U_BOOT_DRIVER(dwc3_layerscape_peripheral) = { + .name = "dwc3-layerscape-peripheral", + .id = UCLASS_USB_GADGET_GENERIC, + .of_to_plat = dwc3_layerscape_of_to_plat, + .probe = dwc3_layerscape_peripheral_probe, + .remove = dwc3_layerscape_peripheral_remove, + .priv_auto = sizeof(struct dwc3_layerscape_priv), + .plat_auto = sizeof(struct dwc3_layerscape_plat), +}; +#endif + +#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || \ + !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST) +static int dwc3_layerscape_host_probe(struct udevice *dev) +{ + struct xhci_hcor *hcor; + struct xhci_hccr *hccr; + struct dwc3_layerscape_host_priv *priv = dev_get_priv(dev); + int rc; + + rc = dwc3_layerscape_probe(dev, &priv->gen_priv); + if (rc) + return rc; + + hccr = priv->gen_priv.base; + hcor = priv->gen_priv.base + HC_LENGTH(xhci_readl(&hccr->cr_capbase)); + + return xhci_register(dev, hccr, hcor); +} + +static int dwc3_layerscape_host_remove(struct udevice *dev) +{ + struct dwc3_layerscape_host_priv *priv = dev_get_priv(dev); + int rc; + + rc = xhci_deregister(dev); + if (rc) + return rc; + + return dwc3_layerscape_remove(dev, &priv->gen_priv); +} + +U_BOOT_DRIVER(dwc3_layerscape_host) = { + .name = "dwc3-layerscape-host", + .id = UCLASS_USB, + .of_to_plat = dwc3_layerscape_of_to_plat, + .probe = dwc3_layerscape_host_probe, + .remove = dwc3_layerscape_host_remove, + .priv_auto = sizeof(struct dwc3_layerscape_host_priv), + .plat_auto = sizeof(struct dwc3_layerscape_plat), + .ops = &xhci_usb_ops, + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#endif + +static int dwc3_layerscape_bind(struct udevice *dev) +{ + ofnode node = dev_ofnode(dev); + const char *name = ofnode_get_name(node); + enum usb_dr_mode dr_mode; + char *driver; + + dr_mode = usb_get_dr_mode(node); + + switch (dr_mode) { +#if CONFIG_IS_ENABLED(DM_USB_GADGET) + case USB_DR_MODE_PERIPHERAL: + dev_dbg(dev, "Using peripheral mode\n"); + driver = "dwc3-layerscape-peripheral"; + break; +#endif +#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) + case USB_DR_MODE_HOST: + dev_dbg(dev, "Using host mode\n"); + driver = "dwc3-layerscape-host"; + break; +#endif + default: + dev_dbg(dev, "Unsupported dr_mode\n"); + return -ENODEV; + }; + + return device_bind_driver_to_node(dev, driver, name, node, NULL); +} + +static const struct udevice_id dwc3_layerscape_ids[] = { + { .compatible = "fsl,layerscape-dwc3" }, + { .compatible = "fsl,ls1028a-dwc3" }, + { } +}; + +U_BOOT_DRIVER(dwc3_layerscape_wrapper) = { + .name = "dwc3-layerscape-wrapper", + .id = UCLASS_NOP, + .of_match = dwc3_layerscape_ids, + .bind = dwc3_layerscape_bind, +}; From f6cc9da16678659accb904fe3cbf27b6e97c1489 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 15 Oct 2021 15:15:24 +0200 Subject: [PATCH 54/62] board: sl28: switch to dwc3 driver Now that the DWC3 USB driver has support for the layerscape platform, use it. This will have the benefit that peripheral mode will work. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- configs/kontron_sl28_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 4689d44b68..1b4c1b4d6b 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -93,7 +93,9 @@ CONFIG_NXP_FSPI=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y +# CONFIG_USB_XHCI_FSL is not set +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_LAYERSCAPE=y CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_SET_TIME=y From 12d2b42a054f419184386012b14845e2c05f2c86 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 15 Oct 2021 15:15:25 +0200 Subject: [PATCH 55/62] board: sl28: enable USB periheral support and gadgets Enable support to update the board via the DFU protocol and make it possible to export the block devices via USB mass storage protocol. This will not work out of the box, yet. You have to change the dr_mode of the usb0 controller to peripheral manually to make it work. True, OTG support will hopefully coming soon. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- configs/kontron_sl28_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 1b4c1b4d6b..31a1083b0a 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -39,12 +39,14 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_DFU=y CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RNG=y @@ -92,10 +94,13 @@ CONFIG_FSL_DSPI=y CONFIG_NXP_FSPI=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y # CONFIG_USB_XHCI_FSL is not set CONFIG_USB_DWC3=y CONFIG_USB_DWC3_LAYERSCAPE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_SET_TIME=y From cdf8534b8a01fd894fcc24f404e1feb5c51d95b2 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 31 Oct 2021 23:21:56 +0100 Subject: [PATCH 56/62] armv8: layerscape: use memalign() to allocate spintable code Don't use efi_allocate_pages(). The allocated memory isn't carved out of the lmb allocations. The memory might then be allocated twice. Particulary, this might happened with the fdt_high/initrd_high feature which will relocate the fdt/ramdisk. This might then overlap with the spin table. Instead use memalign() which allocates on memory on the heap which is correctly carved out by lmb. Please note, that the memory is later reserved in the device tree as well as in the EFI memory map in ft_fixup_cpu() (in arch/arm/cpu/armv8/fsl-layerscape/fdt.c). Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 29 +++++++++++++------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 730d7663d0..d28ab26533 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -14,11 +14,12 @@ #include #include #include +#include #include #include +#include #include "cpu.h" #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -83,8 +84,7 @@ int fsl_layerscape_wake_seconday_cores(void) int i, timeout = 10; u64 *table; #ifdef CONFIG_EFI_LOADER - u64 reloc_addr = U32_MAX; - efi_status_t ret; + void *reloc_addr; #endif #ifdef COUNTER_FREQUENCY_REAL @@ -102,27 +102,26 @@ int fsl_layerscape_wake_seconday_cores(void) * Keep this after the __real_cntfrq update, so we have it when we * copy the complete section here. */ - ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, - EFI_RESERVED_MEMORY_TYPE, - efi_size_in_pages(secondary_boot_code_size), - &reloc_addr); - if (ret == EFI_SUCCESS) { - debug("Relocating spin table from %llx to %llx (size %lx)\n", - (u64)secondary_boot_code_start, reloc_addr, + reloc_addr = memalign(PAGE_SIZE, + round_up(secondary_boot_code_size, PAGE_SIZE)); + if (reloc_addr) { + debug("Relocating spin table from %p to %p (size %lx)\n", + secondary_boot_code_start, reloc_addr, secondary_boot_code_size); - memcpy((void *)reloc_addr, secondary_boot_code_start, + memcpy(reloc_addr, secondary_boot_code_start, secondary_boot_code_size); - flush_dcache_range(reloc_addr, - reloc_addr + secondary_boot_code_size); + flush_dcache_range((unsigned long)reloc_addr, + (unsigned long)reloc_addr + + secondary_boot_code_size); /* set new entry point for secondary cores */ - secondary_boot_addr += (void *)reloc_addr - + secondary_boot_addr += reloc_addr - secondary_boot_code_start; flush_dcache_range((unsigned long)&secondary_boot_addr, (unsigned long)&secondary_boot_addr + 8); /* this will be used to reserve the memory */ - secondary_boot_code_start = (void *)reloc_addr; + secondary_boot_code_start = reloc_addr; } #endif From 8bbbb29815e3d56a51e8a8f6c907705b8683bf3c Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 31 Oct 2021 23:39:35 +0100 Subject: [PATCH 57/62] board: kontron: sl28: add myself to ls1028a.dtsi maintainers I'd like to keep informed about ls1028a.dtsi changes. For now, there is no top-level entry for any layerscape specific files. Instead, add the file entry to my board MAINTAINERS file. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- board/kontron/sl28/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/kontron/sl28/MAINTAINERS b/board/kontron/sl28/MAINTAINERS index a7b0fbbdd1..6b24cba24f 100644 --- a/board/kontron/sl28/MAINTAINERS +++ b/board/kontron/sl28/MAINTAINERS @@ -1,6 +1,7 @@ Kontron SMARC-sAL28 board M: Michael Walle S: Maintained +F: arch/arm/dts/fsl-ls1028a.dtsi F: arch/arm/dts/fsl-ls1028a-kontron-sl28-* F: board/kontron/sl28/ F: configs/kontron_sl28_defconfig From 266e68be759aeb42f305af3827ca914e9eea51c2 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 9 Nov 2021 14:52:26 +0530 Subject: [PATCH 58/62] configs: ls1046aqds: Move CONFIG_SPI_FLASH_* definitions to defconfigs LS1046A-QDS has CONFIG_SPI_FLASH_SST, CONFIG_SPI_FLASH_EON and CONFIG_SPI_FLASH_STMICRO defines present in header. Move these entries from header to defconfigs. Signed-off-by: Kuldeep Singh [Rebased] Signed-off-by: Priyanka Jain --- configs/ls1046aqds_SECURE_BOOT_defconfig | 3 +++ configs/ls1046aqds_defconfig | 3 +++ configs/ls1046aqds_lpuart_defconfig | 3 +++ configs/ls1046aqds_nand_defconfig | 3 +++ configs/ls1046aqds_qspi_defconfig | 3 +++ configs/ls1046aqds_sdcard_ifc_defconfig | 3 +++ configs/ls1046aqds_sdcard_qspi_defconfig | 3 +++ configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 3 +++ configs/ls1046aqds_tfa_defconfig | 3 +++ include/configs/ls1046aqds.h | 7 ------- 10 files changed, 27 insertions(+), 7 deletions(-) diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index e72c24cc98..6b1701f7e7 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -60,6 +60,9 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index a8d03d994a..59d05bffe3 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -63,6 +63,9 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index be81f391e8..0e919045aa 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -64,6 +64,9 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 58a8a91d2b..777a894af7 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -83,6 +83,9 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 6002601f00..01942388b2 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -57,7 +57,10 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index d4b39292b6..1106b73dc8 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -83,6 +83,9 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 90c36516cb..faa885d1c2 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -75,7 +75,10 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 02477280c6..4d87f1267a 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -63,7 +63,10 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 5bf74cdf6a..eb8d95022b 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -73,7 +73,10 @@ CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SF_DEFAULT_BUS=1 # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 987df5f6e5..8bc09d0066 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -27,13 +27,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -/* DSPI */ -#ifdef CONFIG_FSL_DSPI -#define CONFIG_SPI_FLASH_STMICRO /* cs0 */ -#define CONFIG_SPI_FLASH_SST /* cs1 */ -#define CONFIG_SPI_FLASH_EON /* cs2 */ -#endif - #ifdef CONFIG_SYS_DPAA_FMAN #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 From 5e736c9397e50c7b9b4b5f2bbe26d2d964e56e39 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 9 Nov 2021 14:56:41 +0530 Subject: [PATCH 59/62] configs: ls1046aqds: Configure environment related configs LS1046A-QDS board requires updation in few environment configs in TFA defconfigs of the board. Following are the changes: - Update CONFIG_ENV_ADDR - Update CONFIG_ENV_SECT_SIZE - Enable CONFIG_SYS_RELOC_GD_ENV_ADDR Signed-off-by: Kuldeep Singh [Rebased] Signed-off-by: Priyanka Jain --- configs/ls1046aqds_tfa_defconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index eb8d95022b..88d4f75123 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -8,7 +8,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 -CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y @@ -51,7 +51,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=0 -CONFIG_ENV_ADDR=0x40500000 +CONFIG_ENV_ADDR=0x60500000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y From a97a071d10d2b2d49b86f92481f766ed30f6a5ed Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Tue, 9 Nov 2021 16:30:38 +0530 Subject: [PATCH 60/62] configs: fsl: migrate FMAN/QE specific defines to Kconfig Use moveconfig.py script to convert CONFIG_SYS_FMAN_FW_ADDR, CONFIG_SYS_QE_FW_ADDR and CONFIG_SYS_QE_FMAN_FW_LENGTH to Kconfig and move these entries to defconfigs. Signed-off-by: Rajesh Bhagat [Rebased] Signed-off-by: Priyanka Jain --- configs/P2041RDB_NAND_defconfig | 1 + configs/P2041RDB_SDCARD_defconfig | 1 + configs/P2041RDB_SPIFLASH_defconfig | 1 + configs/P2041RDB_defconfig | 1 + configs/P3041DS_NAND_defconfig | 1 + configs/P3041DS_SDCARD_defconfig | 1 + configs/P3041DS_SPIFLASH_defconfig | 1 + configs/P3041DS_defconfig | 1 + configs/P4080DS_SDCARD_defconfig | 1 + configs/P4080DS_SPIFLASH_defconfig | 1 + configs/P4080DS_defconfig | 1 + configs/P5040DS_NAND_defconfig | 1 + configs/P5040DS_SDCARD_defconfig | 1 + configs/P5040DS_SPIFLASH_defconfig | 1 + configs/P5040DS_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 2 ++ configs/T1024RDB_SDCARD_defconfig | 2 ++ configs/T1024RDB_SPIFLASH_defconfig | 2 ++ configs/T1024RDB_defconfig | 2 ++ configs/T1042D4RDB_NAND_defconfig | 2 ++ configs/T1042D4RDB_SDCARD_defconfig | 2 ++ configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++ configs/T1042D4RDB_defconfig | 2 ++ configs/T2080QDS_NAND_defconfig | 1 + configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SECURE_BOOT_defconfig | 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2080QDS_defconfig | 1 + configs/T2080RDB_NAND_defconfig | 1 + configs/T2080RDB_SDCARD_defconfig | 1 + configs/T2080RDB_SPIFLASH_defconfig | 1 + configs/T2080RDB_defconfig | 1 + configs/T2080RDB_revD_NAND_defconfig | 1 + configs/T2080RDB_revD_SDCARD_defconfig | 1 + configs/T2080RDB_revD_SPIFLASH_defconfig | 1 + configs/T2080RDB_revD_defconfig | 1 + configs/T4240RDB_SDCARD_defconfig | 1 + configs/T4240RDB_defconfig | 1 + configs/kmcent2_defconfig | 2 ++ configs/kmtegr1_defconfig | 1 + configs/ls1021aiot_qspi_defconfig | 1 + configs/ls1021aiot_sdcard_defconfig | 1 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_defconfig | 2 ++ configs/ls1043aqds_lpuart_defconfig | 2 ++ configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_nor_ddr3_defconfig | 2 ++ configs/ls1043aqds_qspi_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1043aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1043aqds_tfa_defconfig | 2 ++ configs/ls1043ardb_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_defconfig | 2 ++ configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_sdcard_defconfig | 2 ++ configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_tfa_defconfig | 2 ++ configs/ls1046aqds_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_defconfig | 1 + configs/ls1046aqds_lpuart_defconfig | 1 + configs/ls1046aqds_nand_defconfig | 1 + configs/ls1046aqds_qspi_defconfig | 1 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 + configs/ls1046aqds_sdcard_qspi_defconfig | 1 + configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_tfa_defconfig | 1 + configs/ls1046ardb_emmc_defconfig | 1 + configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_qspi_defconfig | 1 + configs/ls1046ardb_qspi_spl_defconfig | 1 + .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_sdcard_defconfig | 1 + configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_tfa_defconfig | 1 + configs/pg_wcom_expu1_defconfig | 1 + configs/pg_wcom_seli8_defconfig | 1 + drivers/net/Kconfig | 10 ++++++ drivers/qe/Kconfig | 4 +++ include/configs/P2041RDB.h | 31 +----------------- include/configs/T102xRDB.h | 32 +------------------ include/configs/T104xRDB.h | 29 +---------------- include/configs/T208xQDS.h | 27 ---------------- include/configs/T208xRDB.h | 29 ----------------- include/configs/T4240RDB.h | 18 ----------- include/configs/corenet_ds.h | 31 +----------------- include/configs/km/km-mpc8309.h | 3 -- include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/kmcent2.h | 4 --- include/configs/ls1012a_common.h | 4 --- include/configs/ls1021aiot.h | 2 -- include/configs/ls1021aqds.h | 3 -- include/configs/ls1021atwr.h | 2 -- include/configs/ls1043a_common.h | 23 ------------- include/configs/ls1046a_common.h | 20 ------------ include/configs/p1_p2_rdb_pc.h | 6 ---- scripts/config_whitelist.txt | 3 -- 115 files changed, 135 insertions(+), 264 deletions(-) diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 3f0e5122ff..63a15ced49 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -62,6 +62,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x100000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 6ef758d3d4..eb97360e71 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xD2000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index e9b9983e68..1937110862 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -62,6 +62,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index f8ce5ee0a7..7b430f69e2 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -57,6 +57,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index 129ba3da4d..96a6161f16 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -60,6 +60,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x100000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 059df80538..49a30ddca1 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -59,6 +59,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xD2000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 592eb87901..047d65b331 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -60,6 +60,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 7b030ebaa1..821a7c3bc1 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -55,6 +55,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 11b807b055..9186ed1a5e 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -58,6 +58,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xD2000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index cbd830171a..2a4dc5db7d 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -59,6 +59,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index d4c3e65341..564f28caba 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -54,6 +54,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 025293ac9a..370eb23e05 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -61,6 +61,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x100000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index a67ba411ca..8e0d33212c 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -59,6 +59,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xD2000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 4e1565b9b2..172f5ed250 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -60,6 +60,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index 27fc797229..79c6e466c7 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -55,6 +55,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index f1d7b6ba9d..e5c1876dab 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -92,6 +92,8 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +ONFIG_SYS_FMAN_FW_ADDR=0x180000 +CONFIG_SYS_QE_FW_ADDR=0x200000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index ddb52ddd5a..6a552a02cf 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -88,6 +88,8 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x104000 +CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index da0a9d5df0..88f49fac01 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -90,6 +90,8 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x110000 +CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index c9cf187dca..ab591c2697 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -73,6 +73,8 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 +CONFIG_SYS_QE_FW_ADDR=0xEFE00000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 962a3f452d..5d7ed36bbb 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -87,6 +87,8 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x280000 +CONFIG_SYS_QE_FW_ADDR=0x380000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 7b0289fc4a..0813a06643 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -83,6 +83,8 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x10400 +ONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 71a39c2860..c0b2808042 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -85,6 +85,8 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x110000 +CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 12f1349660..1067011f08 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -68,6 +68,8 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 +CONFIG_SYS_QE_FW_ADDR=0xEFF10000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 695b047a35..c39329b751 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -86,6 +86,7 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x160000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 6fc5f01bc9..1075acf561 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -82,6 +82,7 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x104000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index c30343328f..b761a1f850 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -66,6 +66,7 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index cb459ecf83..11a0ed4555 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -84,6 +84,7 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 1dc5cf8778..e3ff9260be 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -59,6 +59,7 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xFFE00000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 00cd009e09..d76547ab63 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -67,6 +67,7 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index f19df03cd4..88f29f408a 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -93,6 +93,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x180000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index b8656efe8f..07de4bcebf 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -89,6 +89,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x104000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index b0d5e256e5..ea43361aa6 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -91,6 +91,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 610f706473..9fbac172d8 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -73,6 +73,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +ONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index ae1b4ed89b..ed7cf4f96c 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -94,6 +94,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x180000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 1c42f54c96..0e80031c39 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -90,6 +90,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x104000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index a03b211f73..00b19f5290 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -92,6 +92,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index 569efe9e7d..f8f459f27b 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index ea71242c09..bfd913a4e5 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -76,6 +76,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x104000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 3a28c2a315..c66b152d20 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 66262d5e5f..16ec0fadcf 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -69,6 +69,8 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0xE8020000 +CONFIG_SYS_QE_FW_ADDR=0xE8040000 CONFIG_RGMII=y CONFIG_MII=y CONFIG_PCI_REGION_MULTI_ENTRY=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 315ba867b5..c3a4d94009 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -179,5 +179,6 @@ CONFIG_QE_UEC=y # CONFIG_PINCTRL_FULL is not set CONFIG_QE=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y +CONFIG_SYS_QE_FW_ADDR=0xF00C0000 CONFIG_SYS_NS16550=y CONFIG_BCH=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 2a999e8798..81d721ea78 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -63,3 +63,4 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_SYS_QE_FW_ADDR=0xf40000 diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index 8456e98e8e..f1b156afbe 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -79,3 +79,4 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_SYS_QE_FW_ADDR=0xf40000 diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 7d4cdb867b..5ef48ae0a0 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -84,3 +84,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index b8c5997dd0..2b8a20c118 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -84,3 +84,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index d6b36e61bc..11425a3e39 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -105,3 +105,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 5168dfe712..e07a2dba89 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -83,3 +83,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index acd01ccf55..2e9309c3ca 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -85,3 +85,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 0b54804e7b..ef920daea2 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -85,3 +85,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index a787ce0b7c..2c62af6984 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -80,3 +80,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index e9efcd7fbc..435ee4483c 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -102,3 +102,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 082ef4c54f..3eb01ea362 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -97,3 +97,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index db27f3b9fb..88fc0c7223 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -70,3 +70,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 8f55d6756b..e9c46152bc 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -72,3 +72,4 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 73174ea893..d06f8edfbb 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -73,3 +73,4 @@ CONFIG_FSL_LPUART=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_SYS_QE_FW_ADDR=0x60940000 diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 16af46177e..d6158976e2 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -74,3 +74,4 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 7ef099d670..3351b390d4 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -89,3 +89,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 1377ce6462..741d64bc5a 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -89,3 +89,4 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 84bab31218..d34ed5be03 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -90,3 +90,4 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_SYS_QE_FW_ADDR=0x940000 diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 051edb0cf7..65af4e7819 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -69,6 +69,8 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x60900000 +CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index e254fdd21c..bbb32e3ea2 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -70,6 +70,8 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x60900000 +CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 54174f32ed..e2dd6e61ac 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -90,6 +90,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 8a40481576..247e98a5b2 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -70,6 +70,8 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x60900000 +CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 1c61e79c64..6b13c492f0 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -64,6 +64,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 385c2adb88..324c96b03f 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -89,6 +89,8 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 +CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index f58d95aae6..47e02a33d7 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -81,6 +81,8 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 +CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index ff2ffcb07c..3683385e71 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -71,6 +71,8 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 +CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 8946526d36..f5deec7ce3 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -81,6 +81,8 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 +CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 4e92ce4afa..5c9fb914a3 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -58,6 +58,8 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x60900000 +CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index e90c3f709e..7604e70017 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -61,6 +61,8 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x60900000 +CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 8624e7e874..94b4f13ed4 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 3c875fe622..a188dd03fe 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -82,6 +82,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 35a5da439e..b2c6a42bd6 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -75,6 +75,8 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 +CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index ae1aff9cd7..4b7c0b924e 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -80,6 +80,8 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 +CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index b3a742e4cb..67ccb2da29 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -60,6 +60,8 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 +CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 295fb0b9b7..a6af9b10ef 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -66,6 +66,8 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 +CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 6b1701f7e7..eb32965146 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -69,6 +69,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 59d05bffe3..a8d9441df3 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -72,6 +72,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 0e919045aa..e41c91619e 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -73,6 +73,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 777a894af7..25a178f793 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -92,6 +92,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 01942388b2..dad335af1d 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -68,6 +68,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 1106b73dc8..d9d4bf264a 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -92,6 +92,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index faa885d1c2..10b3b668ad 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -86,6 +86,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 4d87f1267a..a73ced200c 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -73,6 +73,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 88d4f75123..4bf413c0eb 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -84,6 +84,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 6a3823b972..0fb5998a4b 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -81,6 +81,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 099bb61506..a50f381f08 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -63,6 +63,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 71f4b85b0b..eeb0b8ac85 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -67,6 +67,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 55b5058b71..4556713b8a 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -85,6 +85,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 47c63217ce..7a1b0cff16 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -78,6 +78,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +ONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 28dde01588..0ea465c698 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -79,6 +79,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 5953bb8ad5..995daae10e 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -60,6 +60,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index f7934928bf..3501764e6f 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -66,6 +66,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index 7f56c44a45..a83166d4a4 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -74,3 +74,4 @@ CONFIG_TSEC_ENET=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_QE_FW_ADDR=0x60020000 diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index d4079aad5d..9fe5b2fe94 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -74,3 +74,4 @@ CONFIG_TSEC_ENET=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_QE_FW_ADDR=0x60020000 diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 6c12959f37..3f12b758be 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -344,6 +344,16 @@ config FMAN_ENET help This driver support the Freescale FMan Ethernet controller +config SYS_FMAN_FW_ADDR + hex "FMAN Firmware Address" + depends on FMAN_ENET + default 0x0 + +config SYS_QE_FMAN_FW_LENGTH + hex "FMAN QE Firmware length" + depends on FMAN_ENET || QE || U_QE + default 0x10000 + config FTMAC100 bool "Ftmac100 Ethernet Support" help diff --git a/drivers/qe/Kconfig b/drivers/qe/Kconfig index 553ed5780e..c44a81f69a 100644 --- a/drivers/qe/Kconfig +++ b/drivers/qe/Kconfig @@ -18,6 +18,10 @@ config U_QE help Choose this option to add support for U QUICC Engine. +config SYS_QE_FW_ADDR + hex "QE Firmware Address" + depends on FMAN_ENET || QE || U_QE + default 0x0 choice prompt "QUICC Engine FMan ethernet firmware location" depends on FMAN_ENET || QE diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 198b698f21..bf8a92c69b 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011-2012 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ /* @@ -361,35 +361,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024)) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #ifdef CONFIG_PCI diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index ef79c1beea..89bbeb7784 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ /* @@ -500,36 +500,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_DPAA_FMAN -/* Default address of microcode for the Linux FMan driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#define CONFIG_SYS_QE_FW_ADDR 0x130000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 4485f40a6b..48fc8a271c 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ #ifndef __CONFIG_H @@ -501,33 +501,6 @@ #define CONFIG_U_QE -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_QE_FW_ADDR 0x130000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) -#else -#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 -#endif - -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index e70d108919..78562bc08f 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -482,33 +482,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_DPAA_RMAN /* RMan */ #define CONFIG_SYS_INTERLAKEN -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index fbe8852c48..471ed94b80 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -434,35 +434,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_DPAA_RMAN /* RMan */ #define CONFIG_SYS_INTERLAKEN -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 - -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) - -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 87e3e67a9a..f6ccaf4952 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -456,24 +456,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_DPAA_RMAN #define CONFIG_SYS_INTERLAKEN -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 8819935de1..1e55d5259d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2009-2012 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ /* @@ -365,35 +365,6 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024)) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #ifdef CONFIG_PCI diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h index ff97c6cc79..869bd9b30a 100644 --- a/include/configs/km/km-mpc8309.h +++ b/include/configs/km/km-mpc8309.h @@ -13,9 +13,6 @@ /* QE microcode/firmware address */ /* between the u-boot partition and env */ -#ifndef CONFIG_SYS_QE_FW_ADDR -#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 -#endif /* * System IO Config diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index a5bc689557..743d09e9c4 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -212,7 +212,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */ -#define CONFIG_SYS_QE_FW_ADDR 0x60020000 #define CONFIG_SYS_BOOTCOUNT_BE diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 91b50cb29a..8274dd349b 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -411,10 +411,6 @@ int get_scl(void); #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -/* Default address of microcode for the Linux Fman driver */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xE8020000 -#define CONFIG_SYS_QE_FW_ADDR 0xE8040000 -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) /* Qman / Bman */ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index d072eaab87..4e654ca14e 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -29,10 +29,6 @@ /* CSU */ #define CONFIG_LAYERSCAPE_NS_ACCESS -/* PFE */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x300000 - /*SPI device */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index f73dafef05..222caa161d 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -174,8 +174,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #endif -#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 - #define CONFIG_OF_BOARD_SETUP #define CONFIG_OF_STDOUT_VIA_ALIAS diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 748c04ba69..27b97ffd2f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -390,9 +390,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_FSL_DEVICE_DISABLE - -#define CONFIG_SYS_QE_FW_ADDR 0x60940000 - #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 067d4f725d..c099629607 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -408,8 +408,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif -#define CONFIG_SYS_QE_FW_ADDR 0x60940000 - /* * Environment */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 6e8eebfe22..bdf1b434ac 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -168,29 +168,6 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 -#define CONFIG_SYS_QE_FW_ADDR 0x940000 - - -#else -#if defined(CONFIG_SD_BOOT) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2040 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) -#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00) -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 -#else -/* FMan fireware Pre-load address */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 -#define CONFIG_SYS_QE_FW_ADDR 0x60940000 -#endif -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 7822e9d9fa..515f4209bb 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -145,26 +145,6 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #endif - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 -#else -#ifdef CONFIG_SD_BOOT -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800). - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 -#elif defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_FMAN_FW_ADDR (36 * (256 * 1024)) -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 -#endif -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index d3ac057d1c..6b4fc398a8 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -528,12 +528,6 @@ #define CONFIG_HAS_ETH2 #endif /* CONFIG_TSEC_ENET */ -#ifdef CONFIG_QE -/* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#endif /* CONFIG_QE */ - /* * Environment */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 6792e284a1..f6ca93fa5c 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1685,7 +1685,6 @@ CONFIG_SYS_FM2_DTSEC3_PHY_ADDR CONFIG_SYS_FM2_DTSEC4_PHY_ADDR CONFIG_SYS_FM2_DTSEC_MDIO_ADDR CONFIG_SYS_FM2_TGEC_MDIO_ADDR -CONFIG_SYS_FMAN_FW_ADDR CONFIG_SYS_FMAN_V3 CONFIG_SYS_FM_MURAM_SIZE CONFIG_SYS_FORM_3U_CPCI @@ -2629,8 +2628,6 @@ CONFIG_SYS_PTCPAR CONFIG_SYS_PTDPAR CONFIG_SYS_PTV CONFIG_SYS_PUAPAR -CONFIG_SYS_QE_FMAN_FW_LENGTH -CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_CENA_SIZE CONFIG_SYS_QMAN_CINH_BASE From be3841603467b42d90010d164cb7e2744f61e06d Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 9 Nov 2021 16:56:24 +0530 Subject: [PATCH 61/62] pci: layerscape: Fix the LUT and msi-map mismatch issue In the current code, it doesn't reset the cursors of LUT entry and StreamID at the beginning of the fixup, so it can result in LUT entry setup and msi-map mismatch and LUT entries and StreamID leaking when reload and fixup the DTB. This patch move the initialization of LUT entry and StreamID cursors to the beginning of the fixup to resolve the issues. Signed-off-by: Hou Zhiqiang [Rebased] Signed-off-by: Priyanka Jain --- drivers/pci/pcie_layerscape_fixup.c | 8 +++++++- drivers/pci/pcie_layerscape_fixup_common.c | 6 +++--- drivers/pci/pcie_layerscape_gen4.c | 4 +--- drivers/pci/pcie_layerscape_gen4_fixup.c | 5 ++++- drivers/pci/pcie_layerscape_rc.c | 3 +-- 5 files changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index a58e7a3892..8a2a0e1f4a 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2021 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver */ @@ -24,6 +24,8 @@ #include "pcie_layerscape.h" #include "pcie_layerscape_fixup_common.h" +int next_stream_id; + static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie_rc *pcie_rc) { int nodeoffset; @@ -607,6 +609,9 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc *pcie_rc) { ft_pcie_ep_fix(blob, pcie_rc); ft_pcie_rc_fix(blob, pcie_rc); + + pcie_rc->stream_id_cur = 0; + pcie_rc->next_lut_index = 0; } /* Fixup Kernel DT for PCIe */ @@ -618,6 +623,7 @@ void ft_pci_setup_ls(void *blob, struct bd_info *bd) ft_pcie_ls_setup(blob, pcie_rc); #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) + next_stream_id = FSL_PEX_STREAM_ID_START; fdt_fixup_pcie_ls(blob); #endif } diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c index 3216a20027..faccf6c141 100644 --- a/drivers/pci/pcie_layerscape_fixup_common.c +++ b/drivers/pci/pcie_layerscape_fixup_common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP * * PCIe DT fixup for NXP Layerscape SoCs * Author: Wasim Khan @@ -15,6 +15,8 @@ #include #include "pcie_layerscape_fixup_common.h" +extern int next_stream_id; + void ft_pci_setup(void *blob, struct bd_info *bd) { #if defined(CONFIG_PCIE_LAYERSCAPE_GEN4) @@ -147,8 +149,6 @@ int pcie_next_streamid(int currentid, int idx) /* returns the next available streamid for pcie, -errno if failed */ int pcie_next_streamid(int currentid, int idx) { - static int next_stream_id = FSL_PEX_STREAM_ID_START; - if (next_stream_id > FSL_PEX_STREAM_ID_END) return -EINVAL; diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 255e73181d..6ecdd6af40 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP * * PCIe Gen4 driver for NXP Layerscape SoCs * Author: Hou Zhiqiang @@ -305,8 +305,6 @@ static void ls_pcie_g4_setup_ctrl(struct ls_pcie_g4 *pcie) ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val); ls_pcie_g4_setup_wins(pcie); - - pcie->stream_id_cur = 0; } static void ls_pcie_g4_ep_inbound_win_set(struct ls_pcie_g4 *pcie, int pf, diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c index e9ee15558e..7d11234106 100644 --- a/drivers/pci/pcie_layerscape_gen4_fixup.c +++ b/drivers/pci/pcie_layerscape_gen4_fixup.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP * * PCIe Gen4 driver for NXP Layerscape SoCs * Author: Hou Zhiqiang @@ -223,6 +223,9 @@ static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie) { ft_pcie_rc_layerscape_gen4_fix(blob, pcie); ft_pcie_ep_layerscape_gen4_fix(blob, pcie); + + pcie->stream_id_cur = 0; + pcie->next_lut_index = 0; } /* Fixup Kernel DT for PCIe */ diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c index 217b420076..17969e2f23 100644 --- a/drivers/pci/pcie_layerscape_rc.c +++ b/drivers/pci/pcie_layerscape_rc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2020 NXP + * Copyright 2020,2021 NXP * Layerscape PCIe driver */ @@ -244,7 +244,6 @@ static void ls_pcie_setup_ctrl(struct ls_pcie_rc *pcie_rc) ls_pcie_dbi_ro_wr_dis(pcie); ls_pcie_disable_bars(pcie_rc); - pcie_rc->stream_id_cur = 0; } static int ls_pcie_probe(struct udevice *dev) From 99e1fa89f1a6ce13787af34cbd933c846bc7e93a Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 9 Nov 2021 17:02:31 +0530 Subject: [PATCH 62/62] configs: ls1028a: ensure Ethernet is enabled CONFIG_FSL_ENETC is not explicitly enabled in the NXP LS1028A config files, instead it is selected by CONFIG_MSCC_FELIX_SWITCH, a state of matters which is fragile. CONFIG_MSCC_FELIX_SWITCH depends on CONFIG_DM_DSA, which depends on CONFIG_PHY_FIXED. Not all LS1028A boards did enable CONFIG_PHY_FIXED, which resulted in all of Ethernet being compiled out. This patch makes sure that CONFIG_PHY_FIXED is enabled for all LS1028A boards, and CONFIG_FSL_ENETC as well - don't rely on that fragile selection done by the Felix switch config. Signed-off-by: Vladimir Oltean Reviewed-by: Bin Meng [Rebased] Signed-off-by: Priyanka Jain --- configs/kontron_sl28_defconfig | 1 + configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028aqds_tfa_defconfig | 1 + configs/ls1028aqds_tfa_lpuart_defconfig | 1 + configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028ardb_tfa_defconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 31a1083b0a..bc746abb5c 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -82,6 +82,7 @@ CONFIG_PHY_FIXED=y CONFIG_DM_DSA=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_FSL_ENETC=y CONFIG_MSCC_FELIX_SWITCH=y CONFIG_NVME=y CONFIG_PCIE_ECAM_GENERIC=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 2c4a60e38c..62ec2b9b1c 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -67,6 +67,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_DM_DSA=y CONFIG_E1000=y +CONFIG_FSL_ENETC=y CONFIG_MSCC_FELIX_SWITCH=y CONFIG_MDIO_MUX_I2CREG=y CONFIG_NVME=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 0aa91b183b..f0a49431c7 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -72,6 +72,7 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_DM_DSA=y +CONFIG_FSL_ENETC=y CONFIG_E1000=y CONFIG_MSCC_FELIX_SWITCH=y CONFIG_MDIO_MUX_I2CREG=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index d3a69c749e..0a76166987 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -67,6 +67,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index c385978d37..0fed4c0665 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -63,6 +63,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_DSA=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_FSL_ENETC=y CONFIG_MSCC_FELIX_SWITCH=y CONFIG_NVME=y CONFIG_PCI=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 035974afd8..54dc24cc35 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -69,6 +69,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_DSA=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_FSL_ENETC=y CONFIG_MSCC_FELIX_SWITCH=y CONFIG_NVME=y CONFIG_PCI=y