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arm: dts: r8a774b1: Import DTS from Linux 5.9-rc4

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Import R8A774B1 (RZ/G2N) SoC DTSI and headers from upstream Linux kernel
5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4")

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
This commit is contained in:
Biju Das 2020-09-16 09:05:07 +01:00 committed by Marek Vasut
parent 00407251c3
commit 1abdab94f1
3 changed files with 2713 additions and 0 deletions
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2630
arch/arm/dts/r8a774b1.dtsi Normal file
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include/dt-bindings/clock/r8a774b1-cpg-mssr.h Normal file
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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a774b1 CPG Core Clocks */
#define R8A774B1_CLK_Z 0
#define R8A774B1_CLK_ZG 1
#define R8A774B1_CLK_ZTR 2
#define R8A774B1_CLK_ZTRD2 3
#define R8A774B1_CLK_ZT 4
#define R8A774B1_CLK_ZX 5
#define R8A774B1_CLK_S0D1 6
#define R8A774B1_CLK_S0D2 7
#define R8A774B1_CLK_S0D3 8
#define R8A774B1_CLK_S0D4 9
#define R8A774B1_CLK_S0D6 10
#define R8A774B1_CLK_S0D8 11
#define R8A774B1_CLK_S0D12 12
#define R8A774B1_CLK_S1D2 13
#define R8A774B1_CLK_S1D4 14
#define R8A774B1_CLK_S2D1 15
#define R8A774B1_CLK_S2D2 16
#define R8A774B1_CLK_S2D4 17
#define R8A774B1_CLK_S3D1 18
#define R8A774B1_CLK_S3D2 19
#define R8A774B1_CLK_S3D4 20
#define R8A774B1_CLK_LB 21
#define R8A774B1_CLK_CL 22
#define R8A774B1_CLK_ZB3 23
#define R8A774B1_CLK_ZB3D2 24
#define R8A774B1_CLK_CR 25
#define R8A774B1_CLK_DDR 26
#define R8A774B1_CLK_SD0H 27
#define R8A774B1_CLK_SD0 28
#define R8A774B1_CLK_SD1H 29
#define R8A774B1_CLK_SD1 30
#define R8A774B1_CLK_SD2H 31
#define R8A774B1_CLK_SD2 32
#define R8A774B1_CLK_SD3H 33
#define R8A774B1_CLK_SD3 34
#define R8A774B1_CLK_RPC 35
#define R8A774B1_CLK_RPCD2 36
#define R8A774B1_CLK_MSO 37
#define R8A774B1_CLK_HDMI 38
#define R8A774B1_CLK_CSI0 39
#define R8A774B1_CLK_CP 40
#define R8A774B1_CLK_CPEX 41
#define R8A774B1_CLK_R 42
#define R8A774B1_CLK_OSC 43
#define R8A774B1_CLK_CANFD 44
#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */

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include/dt-bindings/power/r8a774b1-sysc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A774B1_PD_CA57_CPU0 0
#define R8A774B1_PD_CA57_CPU1 1
#define R8A774B1_PD_A3VP 9
#define R8A774B1_PD_CA57_SCU 12
#define R8A774B1_PD_A3VC 14
#define R8A774B1_PD_3DG_A 17
#define R8A774B1_PD_3DG_B 18
#define R8A774B1_PD_A2VC1 26
/* Always-on power area */
#define R8A774B1_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */