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Prepare v2024.01-rc5

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Merge tag 'v2024.01-rc5' into next

Prepare v2024.01-rc5
This commit is contained in:
Tom Rini 2023-12-18 08:31:50 -05:00
commit 1373ffde52
78 changed files with 1015 additions and 2227 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
MAINTAINERS
View file

@ -117,7 +117,7 @@ F: drivers/mmc/snps_dw_mmc.c
APPLE M1 SOC SUPPORT
M: Mark Kettenis <kettenis@openbsd.org>
S: Maintained
F: arch/arm/include/asm/arch-m1/
F: arch/arm/include/asm/arch-apple/
F: arch/arm/mach-apple/
F: configs/apple_m1_defconfig
F: drivers/iommu/apple_dart.c
@ -1528,7 +1528,6 @@ F: cmd/stackprot_test.c
F: test/py/tests/test_stackprotector.py
TARGET_BCMNS3
M: Bharat Gooty <bharat.gooty@broadcom.com>
M: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
S: Maintained
F: board/broadcom/bcmns3/

2
Makefile
View file

@ -3,7 +3,7 @@
VERSION = 2024
PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION = -rc4
EXTRAVERSION = -rc5
NAME =
# *DOCUMENTATION*

3
arch/arm/dts/Makefile
View file

@ -835,6 +835,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-tanix-tx6-mini.dtb
dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h616-orangepi-zero2.dtb \
sun50i-h618-orangepi-zero3.dtb \
sun50i-h616-x96-mate.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
@ -1516,6 +1517,8 @@ targets += $(dtb-y)
# Add any required device tree compiler flags here
DTC_FLAGS += -a 0x8
DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format
PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:

6
arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
View file

@ -93,6 +93,12 @@
&gpio4 {
bootph-some-ram;
usbh_en {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&gpio5 {

10
arch/arm/dts/imx7d-pico-pi-u-boot.dtsi
View file

@ -7,6 +7,12 @@
usb0 = &usbotg1;
display0 = &lcdif;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&usbotg1 {
@ -46,6 +52,10 @@
};
};
&wdog1 {
bootph-pre-ram;
};
&iomuxc {
pinctrl_backlight: backlight {
fsl,pins = <

14
arch/arm/dts/imx7s-warp-u-boot.dtsi
View file

@ -1,12 +1,12 @@
/ {
aliases {
mmc0 = &usdhc3;
usb0 = &usbotg1;
};
aliases {
mmc0 = &usdhc3;
usb0 = &usbotg1;
};
chosen {
stdout-path = &uart1;
};
chosen {
stdout-path = &uart1;
};
};
&aips3 {

6
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
View file

@ -39,11 +39,11 @@
};
&i2c1 {
bootph-pre-ram;
bootph-all;
};
&pinctrl_i2c1 {
bootph-pre-ram;
bootph-all;
};
&pinctrl_pmic {
@ -83,5 +83,5 @@
};
&eeprom_som {
bootph-pre-ram;
bootph-all;
};

3
arch/arm/dts/sun50i-h616-orangepi-zero.dtsi
View file

@ -68,10 +68,7 @@
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
allwinner,rx-delay-ps = <3100>;
allwinner,tx-delay-ps = <700>;
status = "okay";
};

3
arch/arm/dts/sun50i-h616-orangepi-zero2.dts
View file

@ -13,6 +13,9 @@
};
&emac0 {
allwinner,rx-delay-ps = <3100>;
allwinner,tx-delay-ps = <700>;
phy-mode = "rgmii";
phy-supply = <&reg_dcdce>;
};

2
arch/arm/dts/sun50i-h618-orangepi-zero3.dts
View file

@ -13,6 +13,8 @@
};
&emac0 {
allwinner,tx-delay-ps = <700>;
phy-mode = "rgmii-rxid";
phy-supply = <&reg_dldo1>;
};

48
arch/arm/mach-apple/board.c
View file

@ -370,6 +370,22 @@ static struct mm_region t6020_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x400000000,
.phys = 0x400000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x480000000,
.phys = 0x480000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x580000000,
@ -471,6 +487,22 @@ static struct mm_region t6022_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x400000000,
.phys = 0x400000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x480000000,
.phys = 0x480000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x580000000,
@ -551,6 +583,22 @@ static struct mm_region t6022_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x2400000000,
.phys = 0x2400000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x2480000000,
.phys = 0x2480000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x2580000000,

1
arch/arm/mach-imx/imx8m/clock_imx8mm.c
View file

@ -56,6 +56,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
PLL_1443X_RATE(900000000U, 300, 8, 0, 0),
PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),

14
arch/riscv/dts/binman.dtsi
View file

@ -5,9 +5,6 @@
#include <config.h>
#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff)
#define U64_TO_U32_L(addr) ((addr) & 0xffffffff)
/ {
binman: binman {
multiple-images;
@ -36,8 +33,7 @@
os = "U-Boot";
arch = "riscv";
compression = "none";
load = <U64_TO_U32_H(CONFIG_TEXT_BASE)
U64_TO_U32_L(CONFIG_TEXT_BASE)>;
load = /bits/ 64 <CONFIG_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
@ -50,7 +46,7 @@
os = "Linux";
arch = "riscv";
compression = "none";
load = <CONFIG_TEXT_BASE>;
load = /bits/ 64 <CONFIG_TEXT_BASE>;
linux_blob: blob-ext {
filename = "Image";
@ -64,10 +60,8 @@
os = "opensbi";
arch = "riscv";
compression = "none";
load = <U64_TO_U32_H(CONFIG_SPL_OPENSBI_LOAD_ADDR)
U64_TO_U32_L(CONFIG_SPL_OPENSBI_LOAD_ADDR)>;
entry = <U64_TO_U32_H(CONFIG_SPL_OPENSBI_LOAD_ADDR)
U64_TO_U32_L(CONFIG_SPL_OPENSBI_LOAD_ADDR)>;
load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
opensbi_blob: opensbi {
filename = "fw_dynamic.bin";

10
arch/riscv/dts/jh7110.dtsi
View file

@ -533,6 +533,16 @@
#gpio-cells = <2>;
};
watchdog@13070000 {
compatible = "starfive,jh7110-wdt";
reg = <0x0 0x13070000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
<&syscrg JH7110_SYSCLK_WDT_CORE>;
clock-names = "apb", "core";
resets = <&syscrg JH7110_SYSRST_WDT_APB>,
<&syscrg JH7110_SYSRST_WDT_CORE>;
};
mmc0: mmc@16010000 {
compatible = "starfive,jh7110-mmc";
reg = <0x0 0x16010000 0x0 0x10000>;

33
arch/riscv/lib/andes_plicsw.c
View file

@ -21,41 +21,36 @@
#include <linux/err.h>
/* pending register */
#define PENDING_REG(base) ((ulong)(base) + 0x1000)
#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + 4 * (((hart) + 1) / 32))
/* enable register */
#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80 + 4 * (((hart) + 1) / 32))
/* claim register */
#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
/* priority register */
#define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE)
/* Bit 0 of PLIC-SW pending array is hardwired to zero, so we start from bit 1 */
#define FIRST_AVAILABLE_BIT 0x2
#define SEND_IPI_TO_HART(hart) (FIRST_AVAILABLE_BIT << (hart))
#define PLICSW_PRIORITY_BASE 0x4
#define PLICSW_INTERRUPT_PER_HART 0x1
DECLARE_GLOBAL_DATA_PTR;
static int enable_ipi(int hart)
{
unsigned int en;
u32 enable_bit = (hart + 1) % 32;
en = FIRST_AVAILABLE_BIT << hart;
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
writel(BIT(enable_bit), (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
return 0;
}
static void init_priority_ipi(int hart_num)
{
uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw);
u32 *priority = (void *)PRIORITY_REG(gd->arch.plicsw);
for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) {
writel(1, &priority[i]);
}
for (int i = 0; i < hart_num; i++)
writel(1, &priority[i]);
return;
return;
}
int riscv_init_ipi(void)
@ -104,9 +99,10 @@ int riscv_init_ipi(void)
int riscv_send_ipi(int hart)
{
unsigned int ipi = SEND_IPI_TO_HART(hart);
u32 interrupt_id = hart + 1;
u32 pending_bit = interrupt_id % 32;
writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw));
writel(BIT(pending_bit), (void __iomem *)PENDING_REG(gd->arch.plicsw, hart));
return 0;
}
@ -123,10 +119,11 @@ int riscv_clear_ipi(int hart)
int riscv_get_ipi(int hart, int *pending)
{
unsigned int ipi = SEND_IPI_TO_HART(hart);
u32 interrupt_id = hart + 1;
u32 pending_bit = interrupt_id % 32;
*pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw));
*pending = !!(*pending & ipi);
*pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw, hart));
*pending = !!(*pending & BIT(pending_bit));
return 0;
}

4
arch/sandbox/dts/test.dts
View file

@ -631,9 +631,10 @@
clocks = <&clk_fixed>,
<&clk_sandbox 1>,
<&clk_sandbox 0>,
<&ccf 11>,
<&clk_sandbox 3>,
<&clk_sandbox 2>;
clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
};
clk-test2 {
@ -654,6 +655,7 @@
ccf: clk-ccf {
compatible = "sandbox,clk-ccf";
#clock-cells = <1>;
};
efi-media {

1
arch/sandbox/include/asm/clk.h
View file

@ -38,6 +38,7 @@ enum sandbox_clk_test_id {
SANDBOX_CLK_TEST_ID_FIXED,
SANDBOX_CLK_TEST_ID_SPI,
SANDBOX_CLK_TEST_ID_I2C,
SANDBOX_CLK_TEST_ID_I2C_ROOT,
SANDBOX_CLK_TEST_ID_DEVM1,
SANDBOX_CLK_TEST_ID_DEVM2,
SANDBOX_CLK_TEST_ID_DEVM_NULL,

18
board/data_modul/common/common.c
View file

@ -30,6 +30,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7
u8 dmo_get_memcfg(void)
{
struct gpio_desc gpio[4];
@ -58,8 +60,16 @@ u8 dmo_get_memcfg(void)
int board_phys_sdram_size(phys_size_t *size)
{
u8 memcfg = dmo_get_memcfg();
u8 ecc = 0;
*size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G;
*size = 4ULL >> ((memcfg >> 1) & 0x3);
if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) {
/* 896 MiB, i.e. 1 GiB without 12.5% reserved for in-band ECC */
ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK;
}
*size *= SZ_1G - (ecc ? (SZ_1G / 8) : 0);
return 0;
}
@ -100,6 +110,12 @@ static void spl_dram_init(struct dram_timing_info *dram_timing_info[8])
}
ddr_init(dram_timing_info[memcfg]);
if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) {
printf("DDR: Inline ECC %sabled\n",
(readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?
"en" : "dis");
}
}
void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad,

175
board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c
View file

@ -19,47 +19,66 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
{ 0x3d400020, 0x1303 },
{ 0x3d400024, 0x1c79100 },
{ 0x3d400024, 0x1c7cf80 },
{ 0x3d400064, 0x710106 },
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
{ 0x3d400070, 0x7027fd4 },
#else
{ 0x3d400070, 0x7027f90 },
#endif
{ 0x3d400074, 0x790 },
{ 0x3d4000d0, 0xc0030720 },
{ 0x3d4000d0, 0xc0030721 },
{ 0x3d4000d4, 0xb80000 },
{ 0x3d4000dc, 0xe40036 },
{ 0x3d4000e0, 0x330000 },
{ 0x3d4000dc, 0xf4003f },
{ 0x3d4000e0, 0xf30000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
{ 0x3d400100, 0x1e262028 },
{ 0x3d400104, 0x7073b },
{ 0x3d400100, 0x1f262028 },
{ 0x3d400104, 0x8083b },
{ 0x3d40010c, 0xe0e000 },
{ 0x3d400110, 0x11040a11 },
{ 0x3d400114, 0x2050e0e },
{ 0x3d400118, 0x1010008 },
{ 0x3d40011c, 0x501 },
{ 0x3d400130, 0x20700 },
{ 0x3d400114, 0x2050f0f },
{ 0x3d400118, 0x1010009 },
{ 0x3d40011c, 0x502 },
{ 0x3d400130, 0x20800 },
{ 0x3d400134, 0xe100002 },
{ 0x3d400138, 0x10d },
{ 0x3d400144, 0xbb005e },
{ 0x3d400180, 0x3a5001c },
{ 0x3d400184, 0x2f071e5 },
{ 0x3d400180, 0x3a6001d },
{ 0x3d400184, 0x2f071f4 },
{ 0x3d400188, 0x0 },
{ 0x3d400190, 0x49b820c },
{ 0x3d400190, 0x4a3820e },
{ 0x3d400194, 0x80303 },
{ 0x3d4001b4, 0x1b0c },
{ 0x3d4001b4, 0x230e },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c0, 0x7 },
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0xc99 },
{ 0x3d400108, 0x810191a },
{ 0x3d4000f4, 0x799 },
{ 0x3d400108, 0x9141c1c },
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
{ 0x3d400200, 0x14 },
#else
{ 0x3d400200, 0x17 },
#endif
{ 0x3d400208, 0x0 },
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
{ 0x3d40020c, 0x14141400 },
#else
{ 0x3d40020c, 0x0 },
#endif
{ 0x3d400210, 0x1f1f },
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
{ 0x3d400204, 0x50505 },
{ 0x3d400214, 0x4040404 },
{ 0x3d400218, 0x4040404 },
#else
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
#endif
{ 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
@ -78,7 +97,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 },
{ 0x3d4020e0, 0x330000 },
{ 0x3d4020e0, 0xf30000 },
{ 0x3d4020e8, 0x660048 },
{ 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
@ -88,7 +107,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
{ 0x3d40211c, 0x301 },
{ 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
{ 0x3d402138, 0x1d },
@ -97,13 +116,13 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d4020f4, 0xc99 },
{ 0x3d4020f4, 0x599 },
{ 0x3d403020, 0x1001 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 },
{ 0x3d4030e0, 0x330000 },
{ 0x3d4030e0, 0xf30000 },
{ 0x3d4030e8, 0x660048 },
{ 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
@ -113,7 +132,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
{ 0x3d40311c, 0x301 },
{ 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
{ 0x3d403138, 0x8 },
@ -122,7 +141,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
{ 0x3d4030f4, 0xc99 },
{ 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
@ -260,16 +279,16 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x212149, 0xeba },
{ 0x213049, 0xeba },
{ 0x213149, 0xeba },
{ 0x43, 0xe7 },
{ 0x1043, 0xe7 },
{ 0x2043, 0xe7 },
{ 0x3043, 0xe7 },
{ 0x4043, 0xe7 },
{ 0x5043, 0xe7 },
{ 0x6043, 0xe7 },
{ 0x7043, 0xe7 },
{ 0x8043, 0xe7 },
{ 0x9043, 0xe7 },
{ 0x43, 0x3ff },
{ 0x1043, 0x3ff },
{ 0x2043, 0x3ff },
{ 0x3043, 0x3ff },
{ 0x4043, 0x3ff },
{ 0x5043, 0x3ff },
{ 0x6043, 0x3ff },
{ 0x7043, 0x3ff },
{ 0x8043, 0x3ff },
{ 0x9043, 0x3ff },
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
@ -319,19 +338,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
{ 0x2002d, 0x0 },
{ 0x12002d, 0x0 },
{ 0x22002d, 0x0 },
{ 0x2002d, 0x1 },
{ 0x12002d, 0x1 },
{ 0x22002d, 0x1 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x22007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x22007c, 0x61 },
{ 0x1004a, 0x500 },
{ 0x1104a, 0x500 },
{ 0x1204a, 0x500 },
{ 0x1304a, 0x500 },
{ 0x2002c, 0x0 },
};
@ -1061,7 +1076,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
/* P0 message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54003, 0xe94 },
{ 0x54003, 0xe96 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@ -1070,26 +1085,26 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x36e4 },
{ 0x5401a, 0x33 },
{ 0x54019, 0x3ff4 },
{ 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
{ 0x54020, 0x33 },
{ 0x5401f, 0x3ff4 },
{ 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0xe400 },
{ 0x54033, 0x3336 },
{ 0x54032, 0xf400 },
{ 0x54033, 0xf33f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
{ 0x54039, 0x3336 },
{ 0x54038, 0xf400 },
{ 0x54039, 0xf33f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@ -1111,25 +1126,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
{ 0x5401a, 0x33 },
{ 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
{ 0x54020, 0x33 },
{ 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
{ 0x54033, 0x3300 },
{ 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
{ 0x54039, 0x3300 },
{ 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@ -1151,25 +1166,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
{ 0x5401a, 0x33 },
{ 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
{ 0x54020, 0x33 },
{ 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
{ 0x54033, 0x3300 },
{ 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
{ 0x54039, 0x3300 },
{ 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@ -1180,7 +1195,7 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54003, 0xe94 },
{ 0x54003, 0xe96 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@ -1190,26 +1205,26 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x310 },
{ 0x54019, 0x36e4 },
{ 0x5401a, 0x33 },
{ 0x54019, 0x3ff4 },
{ 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
{ 0x54020, 0x33 },
{ 0x5401f, 0x3ff4 },
{ 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0xe400 },
{ 0x54033, 0x3336 },
{ 0x54032, 0xf400 },
{ 0x54033, 0xf33f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
{ 0x54039, 0x3336 },
{ 0x54038, 0xf400 },
{ 0x54039, 0xf33f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@ -1699,9 +1714,9 @@ static struct dram_cfg_param ddr_phy_pie[] = {
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
{ 0x2000b, 0x419 },
{ 0x2000b, 0x41a },
{ 0x2000c, 0xe9 },
{ 0x2000d, 0x91c },
{ 0x2000d, 0x91d },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
@ -1804,8 +1819,8 @@ static struct dram_cfg_param ddr_phy_pie[] = {
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
/* P0 3733mts 1D */
.drate = 3733,
/* P0 3600mts 1D */
.drate = 3600,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@ -1825,8 +1840,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
/* P0 3733mts 2D */
.drate = 3733,
/* P0 3600mts 2D */
.drate = 3600,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@ -1845,5 +1860,19 @@ struct dram_timing_info dmo_imx8mp_sbc_dram_timing_32_32 = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3733, 400, 100, },
.fsp_table = { 3600, 400, 100, },
};
#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
void board_dram_ecc_scrub(void)
{
ddrc_inline_ecc_scrub(0x0,0x7ffffff);
ddrc_inline_ecc_scrub(0x8000000,0xfffffff);
ddrc_inline_ecc_scrub(0x10000000,0x17ffffff);
ddrc_inline_ecc_scrub(0x18000000,0x1fffffff);
ddrc_inline_ecc_scrub(0x20000000,0x27ffffff);
ddrc_inline_ecc_scrub(0x28000000,0x2fffffff);
ddrc_inline_ecc_scrub(0x30000000,0x37ffffff);
ddrc_inline_ecc_scrub_end(0x0,0x3fffffff);
}
#endif

5
board/data_modul/imx8mp_edm_sbc/spl.c
View file

@ -68,6 +68,11 @@ int data_modul_imx_edm_sbc_board_power_init(void)
/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
/* DRAM Vdd1 always FPWM */
pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d);
/* DRAM Vdd2/Vddq always FPWM */
pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d);
/* Set LDO4 and CONFIG2 to enable the I2C level translator. */
pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);

2
board/emulation/qemu-riscv/Kconfig
View file

@ -54,8 +54,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SCSI_AHCI
imply AHCI_PCI
imply E1000
imply NVME
imply PCI
imply NVME_PCI
imply PCIE_ECAM_GENERIC
imply DM_RNG
imply SCSI

1849
board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c
View file

File diff suppressed because it is too large Load diff

327
board/gateworks/venice/lpddr4_timing_imx8mp.c
View file

@ -1211,9 +1211,9 @@ static struct dram_cfg_param ddr_phy_pie[] = {
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
{ 0x2000b, 0x34b },
{ 0x2000c, 0xbb },
{ 0x2000d, 0x753 },
{ 0x2000b, 0x465 },
{ 0x2000c, 0xfa },
{ 0x2000d, 0x9c4 },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
@ -1323,42 +1323,42 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = {
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa1080020 },
{ 0x3d400020, 0x1203 },
{ 0x3d400024, 0x16e3600 },
{ 0x3d400064, 0x5b0087 },
{ 0x3d400020, 0x1323 },
{ 0x3d400024, 0x1e84800 },
{ 0x3d400064, 0x7a00b4 },
{ 0x3d400070, 0x7027f90 },
{ 0x3d400074, 0x790 },
{ 0x3d4000d0, 0xc00305ba },
{ 0x3d4000d4, 0x940000 },
{ 0x3d4000dc, 0xd4002d },
{ 0x3d4000e0, 0x310000 },
{ 0x3d4000d0, 0xc00307a3 },
{ 0x3d4000d4, 0xc50000 },
{ 0x3d4000dc, 0xf4003f },
{ 0x3d4000e0, 0x330000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
{ 0x3d400100, 0x191e1920 },
{ 0x3d400104, 0x60630 },
{ 0x3d40010c, 0xb0b000 },
{ 0x3d400110, 0xe04080e },
{ 0x3d400114, 0x2040c0c },
{ 0x3d400118, 0x1010007 },
{ 0x3d40011c, 0x402 },
{ 0x3d400130, 0x20600 },
{ 0x3d400134, 0xc100002 },
{ 0x3d400138, 0x8d },
{ 0x3d400144, 0x96004b },
{ 0x3d400180, 0x2ee0017 },
{ 0x3d400184, 0x2605b8e },
{ 0x3d400100, 0x2028222a },
{ 0x3d400104, 0x8083f },
{ 0x3d40010c, 0xe0e000 },
{ 0x3d400110, 0x12040a12 },
{ 0x3d400114, 0x2050f0f },
{ 0x3d400118, 0x1010009 },
{ 0x3d40011c, 0x502 },
{ 0x3d400130, 0x20800 },
{ 0x3d400134, 0xe100002 },
{ 0x3d400138, 0xbc },
{ 0x3d400144, 0xc80064 },
{ 0x3d400180, 0x3e8001e },
{ 0x3d400184, 0x3207a12 },
{ 0x3d400188, 0x0 },
{ 0x3d400190, 0x497820a },
{ 0x3d400190, 0x49f820e },
{ 0x3d400194, 0x80303 },
{ 0x3d4001b4, 0x170a },
{ 0x3d4001b4, 0x1f0e },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0x699 },
{ 0x3d400108, 0x70e1617 },
{ 0x3d4000f4, 0x799 },
{ 0x3d400108, 0x9121b1c },
{ 0x3d400200, 0x1f },
{ 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
@ -1379,7 +1379,7 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = {
{ 0x3d400498, 0x620096 },
{ 0x3d40049c, 0x1100e07 },
{ 0x3d4004a0, 0xc8012c },
{ 0x3d402020, 0x1001 },
{ 0x3d402020, 0x1021 },
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc0012 },
@ -1404,7 +1404,7 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = {
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d4020f4, 0x599 },
{ 0x3d403020, 0x1001 },
{ 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30005 },
@ -1436,36 +1436,36 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = {
struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = {
{ 0x100a0, 0x0 },
{ 0x100a1, 0x1 },
{ 0x100a2, 0x3 },
{ 0x100a3, 0x2 },
{ 0x100a4, 0x5 },
{ 0x100a5, 0x4 },
{ 0x100a6, 0x7 },
{ 0x100a7, 0x6 },
{ 0x100a2, 0x2 },
{ 0x100a3, 0x3 },
{ 0x100a4, 0x4 },
{ 0x100a5, 0x5 },
{ 0x100a6, 0x6 },
{ 0x100a7, 0x7 },
{ 0x110a0, 0x0 },
{ 0x110a1, 0x1 },
{ 0x110a2, 0x2 },
{ 0x110a3, 0x3 },
{ 0x110a4, 0x4 },
{ 0x110a5, 0x5 },
{ 0x110a6, 0x6 },
{ 0x110a7, 0x7 },
{ 0x110a2, 0x3 },
{ 0x110a3, 0x4 },
{ 0x110a4, 0x5 },
{ 0x110a5, 0x2 },
{ 0x110a6, 0x7 },
{ 0x110a7, 0x6 },
{ 0x120a0, 0x0 },
{ 0x120a1, 0x1 },
{ 0x120a2, 0x2 },
{ 0x120a3, 0x3 },
{ 0x120a4, 0x4 },
{ 0x120a5, 0x5 },
{ 0x120a6, 0x6 },
{ 0x120a7, 0x7 },
{ 0x120a2, 0x3 },
{ 0x120a3, 0x2 },
{ 0x120a4, 0x5 },
{ 0x120a5, 0x4 },
{ 0x120a6, 0x7 },
{ 0x120a7, 0x6 },
{ 0x130a0, 0x0 },
{ 0x130a1, 0x1 },
{ 0x130a2, 0x3 },
{ 0x130a3, 0x4 },
{ 0x130a4, 0x5 },
{ 0x130a5, 0x2 },
{ 0x130a6, 0x7 },
{ 0x130a7, 0x6 },
{ 0x130a2, 0x2 },
{ 0x130a3, 0x3 },
{ 0x130a4, 0x4 },
{ 0x130a5, 0x5 },
{ 0x130a6, 0x6 },
{ 0x130a7, 0x7 },
{ 0x1005f, 0x1ff },
{ 0x1015f, 0x1ff },
{ 0x1105f, 0x1ff },
@ -1500,7 +1500,7 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = {
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },
{ 0x200c5, 0x19 },
{ 0x200c5, 0x18 },
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },
{ 0x2002e, 0x2 },
@ -1509,11 +1509,11 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = {
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },
{ 0x20024, 0x1a3 },
{ 0x20024, 0x1e3 },
{ 0x2003a, 0x2 },
{ 0x120024, 0x1a3 },
{ 0x120024, 0x1e3 },
{ 0x2003a, 0x2 },
{ 0x220024, 0x1a3 },
{ 0x220024, 0x1e3 },
{ 0x2003a, 0x2 },
{ 0x20056, 0x3 },
{ 0x120056, 0x3 },
@ -1579,7 +1579,7 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = {
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
{ 0x20008, 0x2ee },
{ 0x20008, 0x3e8 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
@ -1644,7 +1644,7 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = {
/* P0 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = {
{ 0xd0000, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@ -1653,26 +1653,26 @@ struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = {
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, 0x31 },
{ 0x54019, 0x3ff4 },
{ 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, 0x31 },
{ 0x5401f, 0x3ff4 },
{ 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0xd400 },
{ 0x54033, 0x312d },
{ 0x54032, 0xf400 },
{ 0x54033, 0x333f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xd400 },
{ 0x54039, 0x312d },
{ 0x54038, 0xf400 },
{ 0x54039, 0x333f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@ -1763,7 +1763,7 @@ struct dram_cfg_param ddr_fsp2_cfg_1gb_single_die[] = {
/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = {
{ 0xd0000, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@ -1773,26 +1773,26 @@ struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = {
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x110 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, 0x31 },
{ 0x54019, 0x3ff4 },
{ 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, 0x31 },
{ 0x5401f, 0x3ff4 },
{ 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0xd400 },
{ 0x54033, 0x312d },
{ 0x54032, 0xf400 },
{ 0x54033, 0x333f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xd400 },
{ 0x54039, 0x312d },
{ 0x54038, 0xf400 },
{ 0x54039, 0x333f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@ -1802,8 +1802,8 @@ struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = {
struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = {
{
/* P0 3000mts 1D */
.drate = 3000,
/* P0 4000mts 1D */
.drate = 4000,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg_1gb_single_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1gb_single_die),
@ -1823,8 +1823,8 @@ struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = {
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1gb_single_die),
},
{
/* P0 3000mts 2D */
.drate = 3000,
/* P0 4000mts 2D */
.drate = 4000,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg_1gb_single_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1gb_single_die),
@ -1843,7 +1843,7 @@ struct dram_timing_info dram_timing_1gb_single_die = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3000, 400, 100, },
.fsp_table = { 4000, 400, 100, },
};
/*
@ -1856,43 +1856,44 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = {
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
{ 0x3d400020, 0x1203 },
{ 0x3d400024, 0x16e3600 },
{ 0x3d400064, 0x5b00d2 },
{ 0x3d400020, 0x1323 },
{ 0x3d400024, 0x1e84800 },
{ 0x3d400064, 0x7a0118 },
{ 0x3d400070, 0x7027f90 },
{ 0x3d400074, 0x790 },
{ 0x3d4000d0, 0xc00305ba },
{ 0x3d4000d4, 0x940000 },
{ 0x3d4000dc, 0xd4002d },
{ 0x3d4000e0, 0x310000 },
{ 0x3d4000d0, 0xc00307a3 },
{ 0x3d4000d4, 0xc50000 },
{ 0x3d4000dc, 0xf4003f },
{ 0x3d4000e0, 0x330000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
{ 0x3d400100, 0x191e1920 },
{ 0x3d400104, 0x60630 },
{ 0x3d40010c, 0xb0b000 },
{ 0x3d400110, 0xe04080e },
{ 0x3d400114, 0x2040c0c },
{ 0x3d400118, 0x1010007 },
{ 0x3d40011c, 0x401 },
{ 0x3d400130, 0x20600 },
{ 0x3d400134, 0xc100002 },
{ 0x3d400138, 0xd8 },
{ 0x3d400144, 0x96004b },
{ 0x3d400180, 0x2ee0017 },
{ 0x3d400184, 0x2605b8e },
{ 0x3d400100, 0x2028222a },
{ 0x3d400104, 0x8083f },
{ 0x3d40010c, 0xe0e000 },
{ 0x3d400110, 0x12040a12 },
{ 0x3d400114, 0x2050f0f },
{ 0x3d400118, 0x1010009 },
{ 0x3d40011c, 0x502 },
{ 0x3d400130, 0x20800 },
{ 0x3d400134, 0xe100002 },
{ 0x3d400138, 0x120 },
{ 0x3d400144, 0xc80064 },
{ 0x3d400180, 0x3e8001e },
{ 0x3d400184, 0x3207a12 },
{ 0x3d400188, 0x0 },
{ 0x3d400190, 0x497820a },
{ 0x3d400190, 0x49f820e},
{ 0x3d400194, 0x80303 },
{ 0x3d4001b4, 0x170a },
{ 0x3d4001b4, 0x1f0e },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0xc99 },
{ 0x3d400108, 0x70e1617 },
{ 0x3d4000f4, 0x799 },
{ 0x3d400108, 0x9121b1c },
{ 0x3d400200, 0x17 },
{ 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 },
@ -1911,7 +1912,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = {
{ 0x3d400498, 0x620096 },
{ 0x3d40049c, 0x1100e07 },
{ 0x3d4004a0, 0xc8012c },
{ 0x3d402020, 0x1001 },
{ 0x3d402020, 0x1021 },
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
@ -1926,7 +1927,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = {
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
{ 0x3d40211c, 0x301 },
{ 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
{ 0x3d402138, 0x1d },
@ -1935,8 +1936,8 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = {
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d4020f4, 0xc99 },
{ 0x3d403020, 0x1001 },
{ 0x3d4020f4, 0x599 },
{ 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
@ -1951,7 +1952,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = {
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
{ 0x3d40311c, 0x301 },
{ 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
{ 0x3d403138, 0x8 },
@ -1960,7 +1961,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = {
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
{ 0x3d4030f4, 0xc99 },
{ 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
@ -1968,36 +1969,36 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = {
static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = {
{ 0x100a0, 0x0 },
{ 0x100a1, 0x1 },
{ 0x100a2, 0x3 },
{ 0x100a3, 0x2 },
{ 0x100a4, 0x5 },
{ 0x100a5, 0x4 },
{ 0x100a6, 0x7 },
{ 0x100a7, 0x6 },
{ 0x100a2, 0x2 },
{ 0x100a3, 0x3 },
{ 0x100a4, 0x4 },
{ 0x100a5, 0x5 },
{ 0x100a6, 0x6 },
{ 0x100a7, 0x7 },
{ 0x110a0, 0x0 },
{ 0x110a1, 0x1 },
{ 0x110a2, 0x2 },
{ 0x110a3, 0x3 },
{ 0x110a4, 0x4 },
{ 0x110a5, 0x5 },
{ 0x110a6, 0x6 },
{ 0x110a7, 0x7 },
{ 0x110a2, 0x3 },
{ 0x110a3, 0x4 },
{ 0x110a4, 0x5 },
{ 0x110a5, 0x2 },
{ 0x110a6, 0x7 },
{ 0x110a7, 0x6 },
{ 0x120a0, 0x0 },
{ 0x120a1, 0x1 },
{ 0x120a2, 0x2 },
{ 0x120a3, 0x3 },
{ 0x120a4, 0x4 },
{ 0x120a5, 0x5 },
{ 0x120a6, 0x6 },
{ 0x120a7, 0x7 },
{ 0x120a2, 0x3 },
{ 0x120a3, 0x2 },
{ 0x120a4, 0x5 },
{ 0x120a5, 0x4 },
{ 0x120a6, 0x7 },
{ 0x120a7, 0x6 },
{ 0x130a0, 0x0 },
{ 0x130a1, 0x1 },
{ 0x130a2, 0x3 },
{ 0x130a3, 0x4 },
{ 0x130a4, 0x5 },
{ 0x130a5, 0x2 },
{ 0x130a6, 0x7 },
{ 0x130a7, 0x6 },
{ 0x130a2, 0x2 },
{ 0x130a3, 0x3 },
{ 0x130a4, 0x4 },
{ 0x130a5, 0x5 },
{ 0x130a6, 0x6 },
{ 0x130a7, 0x7 },
{ 0x1005f, 0x1ff },
{ 0x1015f, 0x1ff },
{ 0x1105f, 0x1ff },
@ -2032,7 +2033,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = {
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },
{ 0x200c5, 0x19 },
{ 0x200c5, 0x18 },
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },
{ 0x2002e, 0x2 },
@ -2041,11 +2042,11 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = {
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },
{ 0x20024, 0x1a3 },
{ 0x20024, 0x1e3 },
{ 0x2003a, 0x2 },
{ 0x120024, 0x1a3 },
{ 0x120024, 0x1e3 },
{ 0x2003a, 0x2 },
{ 0x220024, 0x1a3 },
{ 0x220024, 0x1e3 },
{ 0x2003a, 0x2 },
{ 0x20056, 0x3 },
{ 0x120056, 0x3 },
@ -2111,7 +2112,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = {
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
{ 0x20008, 0x2ee },
{ 0x20008, 0x3e8 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
@ -2175,7 +2176,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = {
static struct dram_cfg_param ddr_fsp0_cfg_4gb_dual_die[] = {
{ 0xd0000, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@ -2184,26 +2185,26 @@ static struct dram_cfg_param ddr_fsp0_cfg_4gb_dual_die[] = {
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, 0x31 },
{ 0x54019, 0x3ff4 },
{ 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, 0x31 },
{ 0x5401f, 0x3ff4 },
{ 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0xd400 },
{ 0x54033, 0x312d },
{ 0x54032, 0xf400 },
{ 0x54033, 0x333f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xd400 },
{ 0x54039, 0x312d },
{ 0x54038, 0xf400 },
{ 0x54039, 0x333f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@ -2294,7 +2295,7 @@ static struct dram_cfg_param ddr_fsp2_cfg_4gb_dual_die[] = {
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = {
{ 0xd0000, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@ -2304,26 +2305,26 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = {
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x310 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, 0x31 },
{ 0x54019, 0x3ff4 },
{ 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, 0x31 },
{ 0x5401f, 0x3ff4 },
{ 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0xd400 },
{ 0x54033, 0x312d },
{ 0x54032, 0xf400 },
{ 0x54033, 0x333f },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xd400 },
{ 0x54039, 0x312d },
{ 0x54038, 0xf400 },
{ 0x54039, 0x333f },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@ -2333,8 +2334,8 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = {
static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = {
{
/* P0 3000mts 1D */
.drate = 3000,
/* P0 4000mts 1D */
.drate = 4000,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg_4gb_dual_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_4gb_dual_die),
@ -2354,8 +2355,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = {
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_4gb_dual_die),
},
{
/* P0 3000mts 2D */
.drate = 3000,
/* P0 4000mts 2D */
.drate = 4000,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg_4gb_dual_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_4gb_dual_die),
@ -2374,5 +2375,5 @@ struct dram_timing_info dram_timing_4gb_dual_die = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3000, 400, 100, },
.fsp_table = { 4000, 400, 100, },
};

6
board/gateworks/venice/venice.c
View file

@ -238,12 +238,12 @@ int ft_board_setup(void *fdt, struct bd_info *bd)
if (!strncmp(base_model, "GW73", 4)) {
pcbrev = get_pcb_rev(base_model);
if (pcbrev > 'B') {
if (pcbrev > 'B' && pcbrev < 'E') {
printf("adjusting dt for %s\n", base_model);
/*
* revC replaced PCIe 5-port switch with 4-port
* which changed ethernet1 PCIe GbE
* revC/D/E has PCIe 4-port switch which changes
* ethernet1 PCIe GbE:
* from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0
* to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0
*/

1
board/pine64/rockpro64_rk3399/MAINTAINERS
View file

@ -1,5 +1,4 @@
ROCKPRO64
M: Akash Gajjar <akash@openedev.com>
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/pine64/rockpro64_rk3399

1
board/rockchip/evb_rk3399/MAINTAINERS
View file

@ -93,7 +93,6 @@ F: configs/rock-4se-rk3399_defconfig
F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
ROCK-PI-4
M: Akash Gajjar <akash@openedev.com>
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/rock-pi-4-rk3399_defconfig

5
board/sunxi/MAINTAINERS
View file

@ -455,6 +455,11 @@ M: Jernej Skrabec <jernej.skrabec@siol.net>
S: Maintained
F: configs/orangepi_zero2_defconfig
ORANGEPI ZERO 3 BOARD
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
F: configs/orangepi_zero3_defconfig
ORANGEPI PC 2 BOARD
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained

6
board/toradex/colibri_imx7/colibri_imx7.c
View file

@ -66,7 +66,7 @@ int dram_init(void)
}
static iomux_v3_cfg_t const flash_detection_pads[] = {
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL),
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL) | MUX_MODE_SION,
};
static iomux_v3_cfg_t const uart1_pads[] = {
@ -193,9 +193,9 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
/*
* Enable GPIO on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST
* Enable GPIO SION on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST
* is pulled high with 4.7k for eMMC devices. This allows to reliably
* detect eMMC/NAND flash
* detect eMMC vs NAND flash.
*/
imx_iomux_v3_setup_multiple_pads(flash_detection_pads, ARRAY_SIZE(flash_detection_pads));
gpio_request(FLASH_DET_GPIO, "flash-detection-gpio");

2
board/tq/tqma6/tqma6q.cfg
View file

@ -36,7 +36,7 @@ DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
DATA 4, MX6_IOM_DRAM_RESET, 0x00003030
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000

40
boot/bootmeth_efi.c
View file

@ -160,7 +160,6 @@ static int efiload_read_file(struct bootflow *bflow, ulong addr)
if (ret)
return log_msg_ret("read", ret);
bflow->buf = map_sysmem(addr, bflow->size);
bflow->flags |= BOOTFLOWF_STATIC_BUF;
set_efi_bootdev(desc, bflow);
@ -313,6 +312,7 @@ static int distro_efi_try_bootflow_files(struct udevice *dev,
*/
} else {
log_debug("No device tree available\n");
bflow->flags |= BOOTFLOWF_USE_BUILTIN_FDT;
}
return 0;
@ -323,7 +323,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow)
char file_addr[17], fname[256];
char *tftp_argv[] = {"tftp", file_addr, fname, NULL};
struct cmd_tbl cmdtp = {}; /* dummy */
const char *addr_str, *fdt_addr_str;
const char *addr_str, *fdt_addr_str, *bootfile_name;
int ret, arch, size;
ulong addr, fdt_addr;
char str[36];
@ -339,7 +339,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow)
ret = env_set("bootp_vci", str);
if (ret)
return log_msg_ret("vcs", ret);
ret = env_set_ulong("bootp_arch", arch);
ret = env_set_hex("bootp_arch", arch);
if (ret)
return log_msg_ret("ars", ret);
@ -360,6 +360,12 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow)
return log_msg_ret("sz", -EINVAL);
bflow->size = size;
/* bootfile should be setup by dhcp*/
bootfile_name = env_get("bootfile");
if (!bootfile_name)
return log_msg_ret("bootfile_name", ret);
bflow->fname = strdup(bootfile_name);
/* do the hideous EFI hack */
efi_set_bootdev("Net", "", bflow->fname, map_sysmem(addr, 0),
bflow->size);
@ -385,6 +391,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow)
bflow->fdt_addr = fdt_addr;
} else {
log_debug("No device tree available\n");
bflow->flags |= BOOTFLOWF_USE_BUILTIN_FDT;
}
bflow->state = BOOTFLOWST_READY;
@ -396,6 +403,12 @@ static int distro_efi_read_bootflow(struct udevice *dev, struct bootflow *bflow)
{
int ret;
/*
* bootmeth_efi doesn't allocate any buffer neither for blk nor net device
* set flag to avoid freeing static buffer.
*/
bflow->flags |= BOOTFLOWF_STATIC_BUF;
if (bootmeth_uses_network(bflow)) {
/* we only support reading from one device, so ignore 'dev' */
ret = distro_efi_read_bootflow_net(bflow);
@ -422,13 +435,11 @@ static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow)
return log_msg_ret("read", ret);
/*
* use the provided device tree if available, else fall back to
* the control FDT
* use the provided device tree if not using the built-in fdt
*/
if (bflow->fdt_fname)
if (bflow->flags & ~BOOTFLOWF_USE_BUILTIN_FDT)
fdt = bflow->fdt_addr;
else
fdt = (ulong)map_to_sysmem(gd->fdt_blob);
} else {
/*
* This doesn't actually work for network devices:
@ -441,8 +452,17 @@ static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow)
fdt = env_get_hex("fdt_addr_r", 0);
}
if (efi_binary_run(map_sysmem(kernel, 0), 0, map_sysmem(fdt, 0)))
return log_msg_ret("run", -EINVAL);
if (bflow->flags & BOOTFLOWF_USE_BUILTIN_FDT) {
log_debug("Booting with built-in fdt\n");
if (efi_binary_run(map_sysmem(kernel, 0), 0,
EFI_FDT_USE_INTERNAL))
return log_msg_ret("run", -EINVAL);
} else {
log_debug("Booting with external fdt\n");
if (efi_binary_run(map_sysmem(kernel, 0), 0,
map_sysmem(fdt, 0)))
return log_msg_ret("run", -EINVAL);
}
return 0;
}

4
cmd/efi_common.c
View file

@ -17,10 +17,8 @@ void efi_show_tables(struct efi_system_table *systab)
for (i = 0; i < systab->nr_tables; i++) {
struct efi_configuration_table *tab = &systab->tables[i];
char guid_str[37];
uuid_bin_to_str(tab->guid.b, guid_str, 1);
printf("%p %pUl %s\n", tab->table, guid_str,
printf("%p %pUl %s\n", tab->table, tab->guid.b,
uuid_guid_get_str(tab->guid.b) ?: "(unknown)");
}
}

2
common/spl/Kconfig
View file

@ -378,7 +378,7 @@ config SPL_STACK
default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB
default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB
default 0x118000 if MACH_SUN50I_H6
default 0x58000 if MACH_SUN50I_H616
default 0x52a00 if MACH_SUN50I_H616
default 0x40000 if MACH_SUN8I_R528
default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5
default 0x18000 if MACH_SUN9I

1
configs/apalis-imx8_defconfig
View file

@ -65,6 +65,7 @@ CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
CONFIG_GPIO_HOG=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y

1
configs/bananapi-m2-pro_defconfig
View file

@ -56,6 +56,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y

1
configs/bananapi-m2s_defconfig
View file

@ -61,6 +61,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y

1
configs/imx8mm_data_modul_edm_sbc_defconfig
View file

@ -162,6 +162,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
CONFIG_FSL_CAAM=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y

2
configs/imx8mp_data_modul_edm_sbc_defconfig
View file

@ -169,6 +169,8 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
CONFIG_FSL_CAAM=y
CONFIG_IMX8M_DRAM_INLINE_ECC=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y

1
configs/imx8mp_dhcom_pdk2_defconfig
View file

@ -165,6 +165,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
CONFIG_FSL_CAAM=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y

1
configs/imx8mp_dhcom_pdk3_defconfig
View file

@ -167,6 +167,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
CONFIG_FSL_CAAM=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y

1
configs/imx8mp_evk_defconfig
View file

@ -71,6 +71,7 @@ CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_IMX8MP=y

1
configs/libretech-cc_v2_defconfig
View file

@ -66,6 +66,7 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MESON_SPIFC=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y

1
configs/odroid-go-ultra_defconfig
View file

@ -63,6 +63,7 @@ CONFIG_MESON_SERIAL=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y

2
configs/orangepi_zero2_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e
CONFIG_DRAM_SUN50I_H616_TPR10=0xf83438
CONFIG_MACH_SUN50I_H616=y
CONFIG_SUNXI_DRAM_H616_DDR3_1333=y
CONFIG_USB1_VBUS_PIN="PC16"
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@ -19,6 +20,7 @@ CONFIG_SYS_I2C_SPEED=400000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
CONFIG_AXP305_POWER=y
CONFIG_SPI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y

32
configs/orangepi_zero3_defconfig Normal file
View file

@ -0,0 +1,32 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero3"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e
CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee
CONFIG_DRAM_SUN50I_H616_TPR6=0x44000000
CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663
CONFIG_DRAM_SUN50I_H616_TPR11=0x24242624
CONFIG_DRAM_SUN50I_H616_TPR12=0x0f0f100f
CONFIG_MACH_SUN50I_H616=y
CONFIG_SUNXI_DRAM_H616_LPDDR4=y
CONFIG_DRAM_CLK=792
CONFIG_USB1_VBUS_PIN="PC16"
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_SPI_FLASH_ZBIT=y
CONFIG_PHY_MOTORCOMM=y
CONFIG_SUN8I_EMAC=y
CONFIG_AXP313_POWER=y
CONFIG_SPI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y

1
configs/pico-pi-imx6ul_defconfig
View file

@ -70,6 +70,7 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y

3
configs/pico-pi-imx7d_defconfig
View file

@ -76,6 +76,8 @@ CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_SPL_USB_HOST=y
@ -95,3 +97,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
CONFIG_IMX_WATCHDOG=y

1
configs/radxa-zero2_defconfig
View file

@ -52,6 +52,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y

5
configs/starfive_visionfive2_defconfig
View file

@ -72,6 +72,7 @@ CONFIG_CMD_MEMINFO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_BOARD=y
@ -133,3 +134,7 @@ CONFIG_USB_EHCI_PCI=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_PCI=y
CONFIG_USB_KEYBOARD=y
# CONFIG_WATCHDOG is not set
# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_WDT=y
CONFIG_WDT_STARFIVE=y

1
configs/x96_mate_defconfig
View file

@ -18,6 +18,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_AXP305_POWER=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y

50
doc/arch/sandbox/sandbox.rst
View file

@ -424,15 +424,59 @@ space. See existing code for examples.
VPL (Verifying Program Loader)
------------------------------
Sandbox provides an example build of vpl called `sandbox_vpl`. This can be run
using::
Sandbox provides an example build of vpl called `sandbox_vpl`. To build it:
/path/to/sandbox_vpl/tpl/u-boot-tpl -D
.. code-block:: bash
make sandbox_vpl_defconfig all
This can be run using:
.. code-block:: bash
./tpl/u-boot-tpl -d u-boot.dtb
It starts up TPL (first-stage init), then VPL, then runs SPL and finally U-Boot
proper, following the normal flow for a verified boot. At present, no
verification is actually implemented.
Here is an example trace::
U-Boot TPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700)
Trying to boot from sandbox_image
Trying to boot from sandbox_file
U-Boot VPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700)
Trying to boot from vbe_simple
Trying to boot from sandbox_image
Trying to boot from sandbox_file
U-Boot SPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700)
Trying to boot from vbe_simple
Trying to boot from sandbox_image
Trying to boot from sandbox_file
U-Boot 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700)
Reset Status: COLD
Model: sandbox
DRAM: 256 MiB
using memory 0x1b576000-0x1f578000 for malloc()
Warning: host_lo MAC addresses don't match:
Address in ROM is 96:cd:ef:82:78:51
Address in environment is 02:00:11:22:33:44
Core: 103 devices, 51 uclasses, devicetree: board
MMC:
Loading Environment from nowhere... OK
In: serial,cros-ec-keyb,usbkbd
Out: serial,vidconsole
Err: serial,vidconsole
Model: sandbox
Net: eth0: host_lo, eth1: host_enp14s0, eth2: host_eth6, eth3: host_wlp15s0, eth4: host_virbr0, eth5: host_docker0, eth6: eth@10002000
Hit any key to stop autoboot: 1
Debugging the init sequence
---------------------------

3
doc/board/allwinner/sunxi.rst
View file

@ -251,8 +251,7 @@ the SPI flash content from Linux, using the `MTD utils`_::
# apt-get install mtd-utils
# mtdinfo
# mtd_debug erase /dev/mtdX 0 0xf0000
# mtd_debug write /dev/mtdX 0 0xf0000 u-boot-sunxi-with-spl.bin
# flashcp -v u-boot-sunxi-with-spl.bin /dev/mtdX
``/dev/mtdX`` needs to be replaced with the respective device name, as listed
in the output of ``mtdinfo``.

22
doc/build/clang.rst vendored
View file

@ -11,14 +11,6 @@ The ARM backend can be instructed not to use the r9 and x18 registers using
supported inline assembly is needed to get and set the r9 or x18 value. This
leads to larger code then strictly necessary, but at least works.
**NOTE:** target compilation only work for _some_ ARM boards at the moment.
Also AArch64 is not supported currently due to a lack of private libgcc
support. Boards which reassign gd in c will also fail to compile, but there is
in no strict reason to do so in the ARM world, since crt0.S takes care of this.
These assignments can be avoided by changing the init calls but this is not in
mainline yet.
Debian based
------------
@ -28,14 +20,20 @@ Required packages can be installed via apt, e.g.
sudo apt-get install clang
Note that we still use binutils for some tools so we must continue to set
CROSS_COMPILE. To compile U-Boot with Clang on Linux without IAS use e.g.
We make use of the CROSS_COMPILE variable to derive the build target which is
passed as the --target parameter to clang.
The CROSS_COMPILE variable further determines the paths to other build
tools. As assembler we use the binary pointed to by '$(CROSS_COMPILE)as'
instead of the LLVM integrated assembler (IAS).
Here is an example demonstrating building U-Boot for the Raspberry Pi 2
using clang:
.. code-block:: bash
make HOSTCC=clang rpi_2_defconfig
make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- \
CC="clang -target arm-linux-gnueabi" -j8
make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- CC=clang -j8
It can also be used to compile sandbox:

2
doc/develop/release_cycle.rst
View file

@ -72,7 +72,7 @@ For the next scheduled release, release candidates were made on::
* U-Boot v2024.01-rc4 was released on Mon 04 December 2023.
.. * U-Boot v2024.01-rc5 was released on Mon 18 December 2023.
* U-Boot v2024.01-rc5 was released on Mon 18 December 2023.
.. * U-Boot v2024.01-rc6 was released on Tue 02 January 2024.

4
doc/develop/sending_patches.rst
View file

@ -363,7 +363,7 @@ A Custodian has additional privileges and can:
* Awaiting Upstream
* Superseeded
* Superseded
* Deferred
@ -399,7 +399,7 @@ today. Not all states are used by all custodians.
and has not merged yet to master, or has queued the patch up to be submitted
to be merged, but has not yet.
* Superseeded: Patches are marked as 'superseeded' when the poster submits a
* Superseded: Patches are marked as 'superseded' when the poster submits a
new version of these patches.
* Deferred: Deferred usually means the patch depends on something else that

2
drivers/clk/clk-composite.c
View file

@ -66,7 +66,7 @@ static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk *clk_rate = composite->rate;
if (rate && rate_ops)
if (rate && rate_ops && rate_ops->set_rate)
return rate_ops->set_rate(clk_rate, rate);
else
return clk_get_rate(clk);

2
drivers/clk/clk-uclass.c
View file

@ -640,6 +640,7 @@ int clk_enable(struct clk *clk)
if (CONFIG_IS_ENABLED(CLK_CCF)) {
/* Take id 0 as a non-valid clk, such as dummy */
if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
ops = clk_dev_ops(clkp->dev);
if (clkp->enable_count) {
clkp->enable_count++;
return 0;
@ -699,6 +700,7 @@ int clk_disable(struct clk *clk)
if (CONFIG_IS_ENABLED(CLK_CCF)) {
if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
ops = clk_dev_ops(clkp->dev);
if (clkp->flags & CLK_IS_CRITICAL)
return 0;

18
drivers/clk/clk.c
View file

@ -18,17 +18,19 @@
int clk_register(struct clk *clk, const char *drv_name,
const char *name, const char *parent_name)
{
struct udevice *parent;
struct udevice *parent = NULL;
struct driver *drv;
int ret;
ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
if (ret) {
log_err("%s: failed to get %s device (parent of %s)\n",
__func__, parent_name, name);
} else {
log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name,
parent->name, parent);
if (parent_name) {
ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
if (ret) {
log_err("%s: failed to get %s device (parent of %s)\n",
__func__, parent_name, name);
} else {
log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name,
parent->name, parent);
}
}
drv = lists_driver_lookup_name(drv_name);

1
drivers/clk/clk_sandbox_ccf.c
View file

@ -284,6 +284,7 @@ static int sandbox_clk_ccf_probe(struct udevice *dev)
U_BOOT_DRIVER(sandbox_clk_ccf) = {
.name = "sandbox_clk_ccf",
.id = UCLASS_CLK,
.ops = &ccf_clk_ops,
.probe = sandbox_clk_ccf_probe,
.of_match = sandbox_clk_ccf_test_ids,
};

1
drivers/clk/clk_sandbox_test.c
View file

@ -15,6 +15,7 @@ static const char * const sandbox_clk_test_names[] = {
[SANDBOX_CLK_TEST_ID_FIXED] = "fixed",
[SANDBOX_CLK_TEST_ID_SPI] = "spi",
[SANDBOX_CLK_TEST_ID_I2C] = "i2c",
[SANDBOX_CLK_TEST_ID_I2C_ROOT] = "i2c_root",
};
int sandbox_clk_test_get(struct udevice *dev)

9
drivers/clk/starfive/clk-jh7110.c
View file

@ -434,6 +434,15 @@ static int jh7110_syscrg_init(struct udevice *dev)
starfive_clk_gate(priv->reg,
"i2c5_apb", "apb0",
OFFSET(JH7110_SYSCLK_I2C5_APB)));
/* Watchdog clocks */
clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB),
starfive_clk_gate(priv->reg,
"wdt_apb", "apb0",
OFFSET(JH7110_SYSCLK_WDT_APB)));
clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE),
starfive_clk_gate(priv->reg,
"wdt_core", "oscillator",
OFFSET(JH7110_SYSCLK_WDT_CORE)));
/* enable noc_bus_stg_axi clock */
if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))

5
drivers/ddr/imx/phy/ddrphy_utils.c
View file

@ -111,11 +111,16 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(1000));
dram_disable_bypass();
break;
case 3734:
case 3733:
case 3732:
dram_pll_init(MHZ(933));
dram_disable_bypass();
break;
case 3600:
dram_pll_init(MHZ(900));
dram_disable_bypass();
break;
case 3200:
dram_pll_init(MHZ(800));
dram_disable_bypass();

2
drivers/misc/Kconfig
View file

@ -615,7 +615,7 @@ config FS_LOADER
ie. the FPGA device.
config SPL_FS_LOADER
bool "Enable loader driver for file system"
bool "Enable loader driver for file system in SPL"
depends on SPL
help
This is file system generic loader which can be used to load

5
drivers/mtd/spi/Kconfig
View file

@ -224,6 +224,11 @@ config SPI_FLASH_XTX
Add support for various XTX (XTX Technology Limited)
SPI flash chips (XT25xxx).
config SPI_FLASH_ZBIT
bool "ZBIT SPI flash support"
help
Add support for Zbit Semiconductor Inc. SPI flash chips (ZB25xxx).
endif
config SPI_FLASH_USE_4K_SECTORS

5
drivers/mtd/spi/spi-nor-ids.c
View file

@ -571,6 +571,11 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("xt25w01g", 0x0b651B, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_ZBIT
/* Zbit Semiconductor Inc. */
{ INFO("zb25vq128", 0x5e4018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
#endif
{ },
};

1
drivers/power/Kconfig
View file

@ -56,7 +56,6 @@ choice
depends on ARCH_SUNXI
default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
default AXP305_POWER if MACH_SUN50I_H616
default AXP818_POWER if MACH_SUN8I_A83T
default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_V3S

7
drivers/watchdog/Kconfig
View file

@ -344,6 +344,13 @@ config WDT_STM32MP
Enable the STM32 watchdog (IWDG) driver. Enable support to
configure STM32's on-SoC watchdog.
config WDT_STARFIVE
bool "StarFive watchdog timer support"
depends on WDT
imply WATCHDOG
help
Enable support for the watchdog timer of StarFive JH7110 SoC.
config WDT_SUNXI
bool "Allwinner sunxi watchdog timer support"
depends on WDT && ARCH_SUNXI

1
drivers/watchdog/Makefile
View file

@ -44,6 +44,7 @@ obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o
obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o
obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o
obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o

329
drivers/watchdog/starfive_wdt.c Normal file
View file

@ -0,0 +1,329 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Starfive Watchdog driver
*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#include <clk.h>
#include <dm.h>
#include <reset.h>
#include <wdt.h>
#include <linux/iopoll.h>
/* JH7110 Watchdog register define */
#define STARFIVE_WDT_JH7110_LOAD 0x000
#define STARFIVE_WDT_JH7110_VALUE 0x004
#define STARFIVE_WDT_JH7110_CONTROL 0x008 /*
* [0]: reset enable;
* [1]: interrupt enable && watchdog enable
* [31:2]: reserved.
*/
#define STARFIVE_WDT_JH7110_INTCLR 0x00c /* clear intterupt and reload the counter */
#define STARFIVE_WDT_JH7110_IMS 0x014
#define STARFIVE_WDT_JH7110_LOCK 0xc00 /* write 0x1ACCE551 to unlock */
/* WDOGCONTROL */
#define STARFIVE_WDT_ENABLE 0x1
#define STARFIVE_WDT_EN_SHIFT 0
#define STARFIVE_WDT_RESET_EN 0x1
#define STARFIVE_WDT_JH7110_RST_EN_SHIFT 1
/* WDOGLOCK */
#define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551
/* WDOGINTCLR */
#define STARFIVE_WDT_INTCLR 0x1
#define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */
#define STARFIVE_WDT_MAXCNT 0xffffffff
#define STARFIVE_WDT_DEFAULT_TIME (15)
#define STARFIVE_WDT_DELAY_US 0
#define STARFIVE_WDT_TIMEOUT_US 10000
/* module parameter */
#define STARFIVE_WDT_EARLY_ENA 0
struct starfive_wdt_variant {
unsigned int control; /* Watchdog Control Resgister for reset enable */
unsigned int load; /* Watchdog Load register */
unsigned int reload; /* Watchdog Reload Control register */
unsigned int enable; /* Watchdog Enable Register */
unsigned int value; /* Watchdog Counter Value Register */
unsigned int int_clr; /* Watchdog Interrupt Clear Register */
unsigned int unlock; /* Watchdog Lock Register */
unsigned int int_status; /* Watchdog Interrupt Status Register */
u32 unlock_key;
char enrst_shift;
char en_shift;
bool intclr_check; /* whether need to check it before clearing interrupt */
char intclr_ava_shift;
bool double_timeout; /* The watchdog need twice timeout to reboot */
};
struct starfive_wdt_priv {
void __iomem *base;
struct clk *core_clk;
struct clk *apb_clk;
struct reset_ctl_bulk *rst;
const struct starfive_wdt_variant *variant;
unsigned long freq;
u32 count; /* count of timeout */
u32 reload; /* restore the count */
};
/* Register layout and configuration for the JH7110 */
static const struct starfive_wdt_variant starfive_wdt_jh7110_variant = {
.control = STARFIVE_WDT_JH7110_CONTROL,
.load = STARFIVE_WDT_JH7110_LOAD,
.enable = STARFIVE_WDT_JH7110_CONTROL,
.value = STARFIVE_WDT_JH7110_VALUE,
.int_clr = STARFIVE_WDT_JH7110_INTCLR,
.unlock = STARFIVE_WDT_JH7110_LOCK,
.unlock_key = STARFIVE_WDT_JH7110_UNLOCK_KEY,
.int_status = STARFIVE_WDT_JH7110_IMS,
.enrst_shift = STARFIVE_WDT_JH7110_RST_EN_SHIFT,
.en_shift = STARFIVE_WDT_EN_SHIFT,
.intclr_check = false,
.double_timeout = true,
};
static int starfive_wdt_enable_clock(struct starfive_wdt_priv *wdt)
{
int ret;
ret = clk_enable(wdt->apb_clk);
if (ret)
return ret;
ret = clk_enable(wdt->core_clk);
if (ret) {
clk_disable(wdt->apb_clk);
return ret;
}
return 0;
}
static void starfive_wdt_disable_clock(struct starfive_wdt_priv *wdt)
{
clk_disable(wdt->core_clk);
clk_disable(wdt->apb_clk);
}
/* Write unlock-key to unlock. Write other value to lock. */
static void starfive_wdt_unlock(struct starfive_wdt_priv *wdt)
{
writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
}
static void starfive_wdt_lock(struct starfive_wdt_priv *wdt)
{
writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
}
/* enable watchdog interrupt to reset/reboot */
static void starfive_wdt_enable_reset(struct starfive_wdt_priv *wdt)
{
u32 val;
val = readl(wdt->base + wdt->variant->control);
val |= STARFIVE_WDT_RESET_EN << wdt->variant->enrst_shift;
writel(val, wdt->base + wdt->variant->control);
}
/* waiting interrupt can be free to clear */
static int starfive_wdt_wait_int_free(struct starfive_wdt_priv *wdt)
{
u32 value;
return readl_poll_timeout(wdt->base + wdt->variant->int_clr, value,
!(value & BIT(wdt->variant->intclr_ava_shift)),
STARFIVE_WDT_TIMEOUT_US);
}
/* clear interrupt signal before initialization or reload */
static int starfive_wdt_int_clr(struct starfive_wdt_priv *wdt)
{
int ret;
if (wdt->variant->intclr_check) {
ret = starfive_wdt_wait_int_free(wdt);
if (ret)
return ret;
}
writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr);
return 0;
}
static inline void starfive_wdt_set_count(struct starfive_wdt_priv *wdt,
u32 val)
{
writel(val, wdt->base + wdt->variant->load);
}
/* enable watchdog */
static inline void starfive_wdt_enable(struct starfive_wdt_priv *wdt)
{
u32 val;
val = readl(wdt->base + wdt->variant->enable);
val |= STARFIVE_WDT_ENABLE << wdt->variant->en_shift;
writel(val, wdt->base + wdt->variant->enable);
}
/* disable watchdog */
static inline void starfive_wdt_disable(struct starfive_wdt_priv *wdt)
{
u32 val;
val = readl(wdt->base + wdt->variant->enable);
val &= ~(STARFIVE_WDT_ENABLE << wdt->variant->en_shift);
writel(val, wdt->base + wdt->variant->enable);
}
static inline void starfive_wdt_set_reload_count(struct starfive_wdt_priv *wdt,
u32 count)
{
starfive_wdt_set_count(wdt, count);
/* 7100 need set any value to reload register and could reload value to counter */
if (wdt->variant->reload)
writel(0x1, wdt->base + wdt->variant->reload);
}
static int starfive_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
int ret;
struct starfive_wdt_priv *wdt = dev_get_priv(dev);
starfive_wdt_unlock(wdt);
/* disable watchdog, to be safe */
starfive_wdt_disable(wdt);
starfive_wdt_enable_reset(wdt);
ret = starfive_wdt_int_clr(wdt);
if (ret)
goto exit;
wdt->count = (timeout_ms / 1000) * wdt->freq;
if (wdt->variant->double_timeout)
wdt->count /= 2;
starfive_wdt_set_count(wdt, wdt->count);
starfive_wdt_enable(wdt);
exit:
starfive_wdt_lock(wdt);
return ret;
}
static int starfive_wdt_stop(struct udevice *dev)
{
struct starfive_wdt_priv *wdt = dev_get_priv(dev);
starfive_wdt_unlock(wdt);
starfive_wdt_disable(wdt);
starfive_wdt_lock(wdt);
return 0;
}
static int starfive_wdt_reset(struct udevice *dev)
{
int ret;
struct starfive_wdt_priv *wdt = dev_get_priv(dev);
starfive_wdt_unlock(wdt);
ret = starfive_wdt_int_clr(wdt);
if (ret)
goto exit;
starfive_wdt_set_reload_count(wdt, wdt->count);
exit:
starfive_wdt_lock(wdt);
return ret;
}
static const struct wdt_ops starfive_wdt_ops = {
.start = starfive_wdt_start,
.stop = starfive_wdt_stop,
.reset = starfive_wdt_reset,
};
static int starfive_wdt_probe(struct udevice *dev)
{
struct starfive_wdt_priv *wdt = dev_get_priv(dev);
int ret;
ret = starfive_wdt_enable_clock(wdt);
if (ret)
return ret;
ret = reset_deassert_bulk(wdt->rst);
if (ret)
goto err_reset;
wdt->variant = (const struct starfive_wdt_variant *)dev_get_driver_data(dev);
wdt->freq = clk_get_rate(wdt->core_clk);
if (!wdt->freq) {
ret = -EINVAL;
goto err_get_freq;
}
return 0;
err_get_freq:
reset_assert_bulk(wdt->rst);
err_reset:
starfive_wdt_disable_clock(wdt);
return ret;
}
static int starfive_wdt_of_to_plat(struct udevice *dev)
{
struct starfive_wdt_priv *wdt = dev_get_priv(dev);
wdt->base = (void *)dev_read_addr(dev);
if (!wdt->base)
return -ENODEV;
wdt->apb_clk = devm_clk_get(dev, "apb");
if (IS_ERR(wdt->apb_clk))
return -ENODEV;
wdt->core_clk = devm_clk_get(dev, "core");
if (IS_ERR(wdt->core_clk))
return -ENODEV;
wdt->rst = devm_reset_bulk_get(dev);
if (IS_ERR(wdt->rst))
return -ENODEV;
return 0;
}
static const struct udevice_id starfive_wdt_ids[] = {
{
.compatible = "starfive,jh7110-wdt",
.data = (ulong)&starfive_wdt_jh7110_variant
}, {
/* sentinel */
}
};
U_BOOT_DRIVER(starfive_wdt) = {
.name = "starfive_wdt",
.id = UCLASS_WDT,
.of_match = starfive_wdt_ids,
.priv_auto = sizeof(struct starfive_wdt_priv),
.probe = starfive_wdt_probe,
.of_to_plat = starfive_wdt_of_to_plat,
.ops = &starfive_wdt_ops,
};

2
include/bootflow.h
View file

@ -45,10 +45,12 @@ enum bootflow_state_t {
* CONFIG_OF_HAS_PRIOR_STAGE is enabled
* @BOOTFLOWF_STATIC_BUF: Indicates that @bflow->buf is statically set, rather
* than being allocated by malloc().
* @BOOTFLOWF_USE_BUILTIN_FDT : Indicates that current bootflow uses built-in FDT
*/
enum bootflow_flags_t {
BOOTFLOWF_USE_PRIOR_FDT = 1 << 0,
BOOTFLOWF_STATIC_BUF = 1 << 1,
BOOTFLOWF_USE_BUILTIN_FDT = 1 << 2,
};
/**

1
include/configs/colibri_imx7.h
View file

@ -101,7 +101,6 @@
UBI_BOOTCMD
#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC)
#define MODULE_EXTRA_ENV_SETTINGS \
"variant=-emmc\0" \
EMMC_ANDROID_BOOTCMD
#endif

1
include/configs/starfive-visionfive2.h
View file

@ -40,6 +40,7 @@
"kernel_comp_addr_r=0x88000000\0" \
"kernel_comp_size=0x4000000\0" \
"fdt_addr_r=0x46000000\0" \
"fdtoverlay_addr_r=0x45800000\0" \
"scriptaddr=0x43900000\0" \
"pxefile_addr_r=0x45900000\0" \
"ramdisk_addr_r=0x46100000\0" \

2
lib/Kconfig
View file

@ -1002,7 +1002,7 @@ config GENERATE_SMBIOS_TABLE
Check http://www.dmtf.org/standards/smbios for details.
See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in
See also SYSINFO_SMBIOS which allows SMBIOS values to be provided in
the devicetree.
endmenu

24
lib/efi/efi_app.c
View file

@ -12,18 +12,21 @@
#include <cpu_func.h>
#include <debug_uart.h>
#include <dm.h>
#include <efi.h>
#include <efi_api.h>
#include <errno.h>
#include <init.h>
#include <malloc.h>
#include <sysreset.h>
#include <uuid.h>
#include <asm/global_data.h>
#include <linux/err.h>
#include <linux/types.h>
#include <efi.h>
#include <efi_api.h>
#include <sysreset.h>
#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/root.h>
#include <mapmem.h>
DECLARE_GLOBAL_DATA_PTR;
@ -320,6 +323,19 @@ int dm_scan_other(bool pre_reloc_only)
return 0;
}
static void scan_tables(struct efi_system_table *sys_table)
{
efi_guid_t acpi = EFI_ACPI_TABLE_GUID;
uint i;
for (i = 0; i < sys_table->nr_tables; i++) {
struct efi_configuration_table *tab = &sys_table->tables[i];
if (!memcmp(&tab->guid, &acpi, sizeof(efi_guid_t)))
gd_set_acpi_start(map_to_sysmem(tab->table));
}
}
/**
* efi_main() - Start an EFI image
*
@ -354,6 +370,8 @@ efi_status_t EFIAPI efi_main(efi_handle_t image,
return ret;
}
scan_tables(priv->sys_table);
/*
* We could store the EFI memory map here, but it changes all the time,
* so this is only useful for debugging.

2
lib/efi_loader/Makefile
View file

@ -51,9 +51,7 @@ obj-y += efi_console.o
obj-y += efi_device_path.o
obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o
obj-$(CONFIG_EFI_DEVICE_PATH_UTIL) += efi_device_path_utilities.o
ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
obj-y += efi_dt_fixup.o
endif
obj-y += efi_file.o
obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o
obj-y += efi_image_loader.o

25
lib/efi_loader/efi_bootmgr.c
View file

@ -1262,8 +1262,6 @@ efi_status_t efi_env_set_load_options(efi_handle_t handle,
return ret;
}
#if !CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
/**
* copy_fdt() - Copy the device tree to a new location available to EFI
*
@ -1337,8 +1335,6 @@ static void *get_config_table(const efi_guid_t *guid)
return NULL;
}
#endif /* !CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) */
/**
* efi_install_fdt() - install device tree
*
@ -1358,18 +1354,15 @@ static void *get_config_table(const efi_guid_t *guid)
*/
efi_status_t efi_install_fdt(void *fdt)
{
struct bootm_headers img = { 0 };
efi_status_t ret;
/*
* The EBBR spec requires that we have either an FDT or an ACPI table
* but not both.
*/
#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
if (fdt) {
if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) && fdt)
log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n");
return EFI_SUCCESS;
}
#else
struct bootm_headers img = { 0 };
efi_status_t ret;
if (fdt == EFI_FDT_USE_INTERNAL) {
const char *fdt_opt;
@ -1402,6 +1395,12 @@ efi_status_t efi_install_fdt(void *fdt)
return EFI_LOAD_ERROR;
}
/* Create memory reservations as indicated by the device tree */
efi_carve_out_dt_rsv(fdt);
if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE))
return EFI_SUCCESS;
/* Prepare device tree for payload */
ret = copy_fdt(&fdt);
if (ret) {
@ -1414,9 +1413,6 @@ efi_status_t efi_install_fdt(void *fdt)
return EFI_LOAD_ERROR;
}
/* Create memory reservations as indicated by the device tree */
efi_carve_out_dt_rsv(fdt);
efi_try_purge_kaslr_seed(fdt);
if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
@ -1433,7 +1429,6 @@ efi_status_t efi_install_fdt(void *fdt)
log_err("ERROR: failed to install device tree\n");
return ret;
}
#endif /* GENERATE_ACPI_TABLE */
return EFI_SUCCESS;
}

27
lib/efi_loader/efi_boottime.c
View file

@ -1342,7 +1342,7 @@ static efi_status_t efi_disconnect_all_drivers
const efi_guid_t *protocol,
efi_handle_t child_handle)
{
efi_uintn_t number_of_drivers, tmp;
efi_uintn_t number_of_drivers;
efi_handle_t *driver_handle_buffer;
efi_status_t r, ret;
@ -1353,27 +1353,13 @@ static efi_status_t efi_disconnect_all_drivers
if (!number_of_drivers)
return EFI_SUCCESS;
tmp = number_of_drivers;
while (number_of_drivers) {
ret = EFI_CALL(efi_disconnect_controller(
r = EFI_CALL(efi_disconnect_controller(
handle,
driver_handle_buffer[--number_of_drivers],
child_handle));
if (ret != EFI_SUCCESS)
goto reconnect;
}
free(driver_handle_buffer);
return ret;
reconnect:
/* Reconnect all disconnected drivers */
for (; number_of_drivers < tmp; number_of_drivers++) {
r = EFI_CALL(efi_connect_controller(handle,
&driver_handle_buffer[number_of_drivers],
NULL, true));
if (r != EFI_SUCCESS)
EFI_PRINT("Failed to reconnect controller\n");
ret = r;
}
free(driver_handle_buffer);
@ -1412,6 +1398,13 @@ static efi_status_t efi_uninstall_protocol
r = efi_disconnect_all_drivers(handle, protocol, NULL);
if (r != EFI_SUCCESS) {
r = EFI_ACCESS_DENIED;
/*
* This will reconnect all controllers of the handle, even ones
* that were not connected before. This can be done better
* but we are following the EDKII implementation on this for
* now
*/
EFI_CALL(efi_connect_controller(handle, NULL, NULL, true));
goto out;
}
/* Close protocol */

5
scripts/Makefile.lib
View file

@ -339,7 +339,12 @@ cmd_capsule_esl_gen = \
$(shell sed "s:ESL_BIN_FILE:$(capsule_esl_path):" $(capsule_esl_input_file) > $@)
$(obj)/.capsule_esl.dtsi: FORCE
ifeq ($(CONFIG_EFI_CAPSULE_ESL_FILE),"")
$(error "CONFIG_EFI_CAPSULE_ESL_FILE is empty, EFI capsule authentication \
public key must be specified when CONFIG_EFI_CAPSULE_AUTHENTICATE is enabled")
else
$(call cmd_capsule_esl_gen)
endif
capsule_esl_input_file=$(srctree)/lib/efi_loader/capsule_esl.dtsi.in
capsule_esl_dtsi = .capsule_esl.dtsi

22
test/dm/clk_ccf.c
View file

@ -19,16 +19,18 @@
static int dm_test_clk_ccf(struct unit_test_state *uts)
{
struct clk *clk, *pclk;
struct udevice *dev;
struct udevice *dev, *test_dev;
long long rate;
int ret;
#if CONFIG_IS_ENABLED(CLK_CCF)
struct clk clk_ccf;
const char *clkname;
int clkid, i;
#endif
/* Get the device using the clk device */
ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &test_dev));
/* Test for clk_get_by_id() */
ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
@ -63,6 +65,9 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
rate = clk_get_parent_rate(clk);
ut_asserteq(rate, 60000000);
rate = clk_set_rate(clk, 60000000);
ut_asserteq(rate, -ENOSYS);
rate = clk_get_rate(clk);
ut_asserteq(rate, 60000000);
@ -87,6 +92,9 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
ut_asserteq_str("pll3_80m", pclk->dev->name);
ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);
rate = clk_set_rate(clk, 80000000);
ut_asserteq(rate, -ENOSYS);
rate = clk_get_rate(clk);
ut_asserteq(rate, 80000000);
@ -108,13 +116,23 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
rate = clk_get_rate(clk);
ut_asserteq(rate, 60000000);
rate = clk_set_rate(clk, 60000000);
ut_asserteq(rate, 60000000);
#if CONFIG_IS_ENABLED(CLK_CCF)
/* Test clk tree enable/disable */
ret = clk_get_by_index(test_dev, SANDBOX_CLK_TEST_ID_I2C_ROOT, &clk_ccf);
ut_assertok(ret);
ut_asserteq_str("clk-ccf", clk_ccf.dev->name);
ut_asserteq(clk_ccf.id, SANDBOX_CLK_I2C_ROOT);
ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
ut_assertok(ret);
ut_asserteq_str("i2c_root", clk->dev->name);
ut_asserteq(clk->id, SANDBOX_CLK_I2C_ROOT);
ret = clk_enable(clk);
ret = clk_enable(&clk_ccf);
ut_assertok(ret);
ret = sandbox_clk_enable_count(clk);