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Exynos5: ddr3: Choose between single or double channel config

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Add a 4G configuration and choose it based on the number of banks
declared in config file. A board with 4 SDRAM banks declared (as
per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Akshay Saraswat 2014-11-13 22:38:20 +05:30 committed by Minkyu Kang
parent 43581c8338
commit 0e03e82465
1 changed files with 10 additions and 0 deletions
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10
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
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@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
+ DMC_OFFSET);
pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
if (CONFIG_NR_DRAM_BANKS > 4) {
/* Need both controllers. */
mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
mem->chips_per_channel = 2;
mem->chips_to_configure = 2;
} else {
/* 2GB requires a single controller */
mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
}
/* Enable PAUSE for DREX */
setbits_le32(&clk->pause, ENABLE_BIT);