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Merge git://www.denx.de/git/u-boot-marvell

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This commit is contained in:
Tom Rini 2017-09-26 08:26:57 -04:00
commit 0cc8c3064d
21 changed files with 116 additions and 79 deletions
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16
arch/arm/mach-mvebu/cpu.c
View file

@ -62,6 +62,11 @@ int mvebu_soc_family(void)
case SOC_88F6820_ID:
case SOC_88F6828_ID:
return MVEBU_SOC_A38X;
case SOC_98DX3236_ID:
case SOC_98DX3336_ID:
case SOC_98DX4251_ID:
return MVEBU_SOC_MSYS;
}
return MVEBU_SOC_UNKNOWN;
@ -113,6 +118,8 @@ static const struct sar_freq_modes sar_freq_tab[] = {
{ 0x6, 0x0, 1200, 600, 600 },
{ 0x8, 0x0, 1332, 666, 666 },
{ 0xc, 0x0, 1600, 800, 800 },
{ 0x10, 0x0, 1866, 933, 933 },
{ 0x13, 0x0, 2000, 1000, 933 },
{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
};
#else
@ -208,6 +215,15 @@ int print_cpuinfo(void)
case SOC_88F6828_ID:
puts("MV88F6828-");
break;
case SOC_98DX3236_ID:
puts("98DX3236-");
break;
case SOC_98DX3336_ID:
puts("98DX3336-");
break;
case SOC_98DX4251_ID:
puts("98DX4251-");
break;
default:
puts("Unknown-");
break;

51
arch/arm/mach-mvebu/dram.c
View file

@ -179,11 +179,11 @@ static void dram_ecc_scrubbing(void)
reg_write(REG_SDRAM_CONFIG_ADDR, temp);
for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) {
size = mvebu_sdram_bs(cs) - 1;
size = mvebu_sdram_bs(cs);
if (size == 0)
continue;
total = (u64)size + 1;
total = (u64)size;
total_mem += (u32)(total / (1 << 30));
start_addr = 0;
mv_xor_init2(cs);
@ -194,7 +194,7 @@ static void dram_ecc_scrubbing(void)
size -= start_addr;
}
mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size,
mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size - 1,
SCRUB_MAGIC, SCRUB_MAGIC);
/* Wait for previous transfer completion */
@ -216,6 +216,35 @@ static int ecc_enabled(void)
return 0;
}
/* Return the width of the DRAM bus, or 0 for unknown. */
static int bus_width(void)
{
int full_width = 0;
if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS))
full_width = 1;
switch (mvebu_soc_family()) {
case MVEBU_SOC_AXP:
return full_width ? 64 : 32;
break;
case MVEBU_SOC_A375:
case MVEBU_SOC_A38X:
case MVEBU_SOC_MSYS:
return full_width ? 32 : 16;
default:
return 0;
}
}
static int cycle_mode(void)
{
int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR);
return (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK;
}
#else
static void dram_ecc_scrubbing(void)
{
@ -295,10 +324,26 @@ int dram_init_banksize(void)
void board_add_ram_info(int use_default)
{
struct sar_freq_modes sar_freq;
int mode;
int width;
get_sar_freq(&sar_freq);
printf(" (%d MHz, ", sar_freq.d_clk);
width = bus_width();
if (width)
printf("%d-bit, ", width);
mode = cycle_mode();
/* Mode 0 = Single cycle
* Mode 1 = Two cycles (2T)
* Mode 2 = Three cycles (3T)
*/
if (mode == 1)
printf("2T, ");
if (mode == 2)
printf("3T, ");
if (ecc_enabled())
printf("ECC");
else

3
arch/arm/mach-mvebu/include/mach/config.h
View file

@ -76,9 +76,6 @@
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MII /* expose smi ove miiphy interface */
#if !defined(CONFIG_ARMADA_375)
#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
#endif
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_ARP_TIMEOUT 200
#define CONFIG_NET_RETRY_COUNT 50

1
arch/arm/mach-mvebu/include/mach/cpu.h
View file

@ -65,6 +65,7 @@ enum {
MVEBU_SOC_AXP,
MVEBU_SOC_A375,
MVEBU_SOC_A38X,
MVEBU_SOC_MSYS,
MVEBU_SOC_UNKNOWN,
};

4
arch/arm/mach-mvebu/include/mach/soc.h
View file

@ -18,6 +18,9 @@
#define SOC_88F6810_ID 0x6810
#define SOC_88F6820_ID 0x6820
#define SOC_88F6828_ID 0x6828
#define SOC_98DX3236_ID 0xf410
#define SOC_98DX3336_ID 0xf400
#define SOC_98DX4251_ID 0xfc00
/* A375 revisions */
#define MV_88F67XX_A0_ID 0x3
@ -139,6 +142,7 @@
#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
#define BOOT_FROM_UART 0x28
#define BOOT_FROM_UART_ALT 0x3f
#define BOOT_FROM_SPI 0x32
#define BOOT_FROM_MMC 0x30
#define BOOT_FROM_MMC_ALT 0x31

3
arch/arm/mach-mvebu/spl.c
View file

@ -42,6 +42,9 @@ static u32 get_boot_device(void)
return BOOT_DEVICE_MMC1;
#endif
case BOOT_FROM_UART:
#ifdef BOOT_FROM_UART_ALT
case BOOT_FROM_UART_ALT:
#endif
return BOOT_DEVICE_UART;
case BOOT_FROM_SPI:
default:

20
board/solidrun/clearfog/README
View file

@ -16,3 +16,23 @@ $ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1
Please use the correct device node for your setup instead
of "/dev/sdX" here!
Boot from UART:
---------------
Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5)
to your host.
Set the SW1 DIP switches to UART boot (0: OFF, 1: ON):
ClearFog Base: 01001
ClearFog Pro: 11110
Run the following command to initiate U-Boot download:
./tools/kwboot -b u-boot-spl.kwb /dev/ttyUSBX
Use the correct UART device node for /dev/ttyUSBX.
When download finishes start your favorite terminal emulator
on /dev/ttyUSBX.

1
board/theadorable/MAINTAINERS
View file

@ -4,4 +4,3 @@ S: Maintained
F: board/theadorable/
F: include/configs/theadorable.h
F: configs/theadorable_debug_defconfig
F: configs/theadorable_defconfig

2
configs/clearfog_defconfig
View file

@ -35,8 +35,8 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_PCI=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000

2
configs/controlcenterdc_defconfig
View file

@ -46,8 +46,8 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000

2
configs/db-88f6820-amc_defconfig
View file

@ -47,8 +47,8 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_PCI=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=200000000

2
configs/db-88f6820-gp_defconfig
View file

@ -45,8 +45,8 @@ CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_PCI=y
CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0xd0012000

2
configs/db-mv784mp-gp_defconfig
View file

@ -44,8 +44,8 @@ CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_PCI=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000

2
configs/ds414_defconfig
View file

@ -38,8 +38,8 @@ CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_PCI=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000

2
configs/maxbcm_defconfig
View file

@ -32,8 +32,8 @@ CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2

2
configs/theadorable_debug_defconfig
View file

@ -51,8 +51,8 @@ CONFIG_DM_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_PCI=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000

54
configs/theadorable_defconfig
View file

@ -1,54 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_THEADORABLE=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_FPGA_ALTERA=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_VIDEO_MVEBU=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_REGEX=y
CONFIG_LIB_RAND=y

2
configs/turris_omnia_defconfig
View file

@ -33,8 +33,8 @@ CONFIG_MISC=y
CONFIG_ATSHA204A=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2

8
drivers/net/Kconfig
View file

@ -159,6 +159,14 @@ config FTMAC100
help
This MAC is present in Andestech SoCs.
config MVNETA
bool "Marvell Armada 385 network interface support"
depends on ARMADA_XP || ARMADA_38X
select PHYLIB
help
This driver supports the network interface units in the
Marvell ARMADA XP and 38X SoCs
config MVPP2
bool "Marvell Armada 375/7K/8K network interface support"
depends on ARMADA_375 || ARMADA_8K

1
include/configs/mvebu_armada-37xx.h
View file

@ -84,7 +84,6 @@
/*
* Ethernet Driver configuration
*/
#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_ARP_TIMEOUT 200
#define CONFIG_NET_RETRY_COUNT 50

1
scripts/config_whitelist.txt
View file

@ -1497,7 +1497,6 @@ CONFIG_MVEBU_MMC
CONFIG_MVGBE
CONFIG_MVGBE_PORTS
CONFIG_MVMFP_V2
CONFIG_MVNETA
CONFIG_MVS
CONFIG_MVSATA_IDE
CONFIG_MVSATA_IDE_USE_PORT0