From 08dcbc98236c4ea9eb4b9d4731a53022204c4809 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 1 Mar 2019 10:11:13 +1300 Subject: [PATCH] mv_ddr: ddr3: fix tRAS timimg parameter Based on the JEDEC standard JESD79-3F. The tRAS timings should include the highest speed bins at a given frequency. This is similar to commit 683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong comparison was used in the initial implementation. Signed-off-by: Chris Packham [https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/15] Signed-off-by: Chris Packham Signed-off-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr3_training_db.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c index 111a8586c6..b2f11a8399 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_db.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c @@ -420,13 +420,13 @@ unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_dd result = speed_bin_table_t_rcd_t_rp[index]; break; case SPEED_BIN_TRAS: - if (index < SPEED_BIN_DDR_1066G) + if (index <= SPEED_BIN_DDR_1066G) result = 37500; - else if (index < SPEED_BIN_DDR_1333J) + else if (index <= SPEED_BIN_DDR_1333J) result = 36000; - else if (index < SPEED_BIN_DDR_1600K) + else if (index <= SPEED_BIN_DDR_1600K) result = 35000; - else if (index < SPEED_BIN_DDR_1866M) + else if (index <= SPEED_BIN_DDR_1866M) result = 34000; else result = 33000;