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riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy

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Source hart information is not necessary in IPI, so we could
use single-bit-per-hart strategy to rearrange PLICSW mapping.

Bit 0 of Interrupt Pending Bits is hardwired to 0.
Therefore, we use bit 1 to send IPI to hart 0,
bit 2 to hart 1, ..., and so on.

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Randolph 2023-10-12 13:35:34 +08:00 committed by Leo Yu-Chi Liang
parent 5a348ccf02
commit 04b2123b4d
1 changed files with 11 additions and 13 deletions
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24
arch/riscv/lib/andes_plicsw.c
View file

@ -22,7 +22,7 @@
#include <linux/err.h> #include <linux/err.h>
/* pending register */ /* pending register */
#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) #define PENDING_REG(base) ((ulong)(base) + 0x1000)
/* enable register */ /* enable register */
#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
/* claim register */ /* claim register */
@ -30,10 +30,11 @@
/* priority register */ /* priority register */
#define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE) #define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE)
#define ENABLE_HART_IPI (0x01010101) /* Bit 0 of PLIC-SW pending array is hardwired to zero, so we start from bit 1 */
#define SEND_IPI_TO_HART(hart) (0x1 << (hart)) #define FIRST_AVAILABLE_BIT 0x2
#define SEND_IPI_TO_HART(hart) (FIRST_AVAILABLE_BIT << (hart))
#define PLICSW_PRIORITY_BASE 0x4 #define PLICSW_PRIORITY_BASE 0x4
#define PLICSW_INTERRUPT_PER_HART 0x8 #define PLICSW_INTERRUPT_PER_HART 0x1
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -41,9 +42,8 @@ static int enable_ipi(int hart)
{ {
unsigned int en; unsigned int en;
en = ENABLE_HART_IPI << hart; en = FIRST_AVAILABLE_BIT << hart;
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart)); writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw + 0x4, hart));
return 0; return 0;
} }
@ -75,7 +75,7 @@ int riscv_init_ipi(void)
ret = uclass_find_first_device(UCLASS_CPU, &dev); ret = uclass_find_first_device(UCLASS_CPU, &dev);
if (ret) if (ret)
return ret; return ret;
else if (!dev) if (!dev)
return -ENODEV; return -ENODEV;
ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
@ -105,10 +105,9 @@ int riscv_init_ipi(void)
int riscv_send_ipi(int hart) int riscv_send_ipi(int hart)
{ {
unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); unsigned int ipi = SEND_IPI_TO_HART(hart);
writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw, writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw));
gd->arch.boot_hart));
return 0; return 0;
} }
@ -125,10 +124,9 @@ int riscv_clear_ipi(int hart)
int riscv_get_ipi(int hart, int *pending) int riscv_get_ipi(int hart, int *pending)
{ {
unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); unsigned int ipi = SEND_IPI_TO_HART(hart);
*pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw, *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw));
gd->arch.boot_hart));
*pending = !!(*pending & ipi); *pending = !!(*pending & ipi);
return 0; return 0;