arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM642 SoC Family Main Domain peripherals
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*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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2021-09-10 21:37:43 +00:00
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#include <dt-bindings/phy/phy-cadence.h>
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#include <dt-bindings/phy/phy-ti.h>
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/ {
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serdes_refclk: clock-cmnrefclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
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&cbass_main {
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oc_sram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x00 0x70000000 0x00 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x70000000 0x200000>;
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2021-06-16 16:38:20 +00:00
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tfa-sram@1c0000 {
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reg = <0x1c0000 0x20000>;
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arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
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};
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2021-06-16 16:38:21 +00:00
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dmsc-sram@1e0000 {
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reg = <0x1e0000 0x1c000>;
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};
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sproxy-sram@1fc000 {
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reg = <0x1fc000 0x4000>;
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};
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arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
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};
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2021-09-10 21:37:43 +00:00
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main_conf: syscon@43000000 {
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compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
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reg = <0x0 0x43000000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x43000000 0x20000>;
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serdes_ln_ctrl: mux-controller {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
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};
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};
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arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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2023-01-24 09:43:25 +00:00
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<0x00 0x01840000 0x00 0xC0000>, /* GICR */
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<0x01 0x00000000 0x00 0x2000>, /* GICC */
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<0x01 0x00010000 0x00 0x1000>, /* GICH */
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<0x01 0x00020000 0x00 0x2000>; /* GICV */
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arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
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/*
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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2021-09-10 21:37:43 +00:00
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dmss: bus@48000000 {
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arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-ranges;
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2021-09-10 21:37:43 +00:00
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ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
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arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
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ti,sci-dev-id = <25>;
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secure_proxy_main: mailbox@4d000000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x4d000000 0x00 0x80000>,
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<0x00 0x4a600000 0x00 0x80000>,
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<0x00 0x4a400000 0x00 0x80000>;
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interrupt-names = "rx_012";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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};
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inta_main_dmss: interrupt-controller@48000000 {
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compatible = "ti,sci-inta";
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reg = <0x00 0x48000000 0x00 0x100000>;
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#interrupt-cells = <0>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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msi-controller;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <28>;
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ti,interrupt-ranges = <4 68 36>;
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ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
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};
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main_bcdma: dma-controller@485c0100 {
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compatible = "ti,am64-dmss-bcdma";
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reg = <0x00 0x485c0100 0x00 0x100>,
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<0x00 0x4c000000 0x00 0x20000>,
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<0x00 0x4a820000 0x00 0x20000>,
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<0x00 0x4aa40000 0x00 0x20000>,
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<0x00 0x4bc00000 0x00 0x100000>;
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reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
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msi-parent = <&inta_main_dmss>;
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#dma-cells = <3>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <26>;
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ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
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ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
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ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
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};
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main_pktdma: dma-controller@485c0000 {
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compatible = "ti,am64-dmss-pktdma";
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reg = <0x00 0x485c0000 0x00 0x100>,
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<0x00 0x4a800000 0x00 0x20000>,
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<0x00 0x4aa00000 0x00 0x40000>,
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<0x00 0x4b800000 0x00 0x400000>;
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reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
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msi-parent = <&inta_main_dmss>;
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#dma-cells = <2>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <30>;
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ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
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<0x24>, /* CPSW_TX_CHAN */
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<0x25>, /* SAUL_TX_0_CHAN */
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<0x26>, /* SAUL_TX_1_CHAN */
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<0x27>, /* ICSSG_0_TX_CHAN */
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<0x28>; /* ICSSG_1_TX_CHAN */
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ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
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<0x11>, /* RING_CPSW_TX_CHAN */
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<0x12>, /* RING_SAUL_TX_0_CHAN */
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<0x13>, /* RING_SAUL_TX_1_CHAN */
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<0x14>, /* RING_ICSSG_0_TX_CHAN */
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<0x15>; /* RING_ICSSG_1_TX_CHAN */
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ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
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<0x2b>, /* CPSW_RX_CHAN */
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<0x2d>, /* SAUL_RX_0_CHAN */
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<0x2f>, /* SAUL_RX_1_CHAN */
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<0x31>, /* SAUL_RX_2_CHAN */
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<0x33>, /* SAUL_RX_3_CHAN */
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<0x35>, /* ICSSG_0_RX_CHAN */
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<0x37>; /* ICSSG_1_RX_CHAN */
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ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
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<0x2c>, /* FLOW_CPSW_RX_CHAN */
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<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
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<0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
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<0x36>, /* FLOW_ICSSG_0_RX_CHAN */
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<0x38>; /* FLOW_ICSSG_1_RX_CHAN */
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};
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};
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2021-09-10 21:37:43 +00:00
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dmsc: system-controller@44043000 {
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
compatible = "ti,k2g-sci";
|
|
|
|
|
ti,host-id = <12>;
|
|
|
|
|
mbox-names = "rx", "tx";
|
2023-01-24 09:43:25 +00:00
|
|
|
mboxes = <&secure_proxy_main 12>,
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
<&secure_proxy_main 13>;
|
|
|
|
|
reg-names = "debug_messages";
|
|
|
|
|
reg = <0x00 0x44043000 0x00 0xfe0>;
|
|
|
|
|
|
|
|
|
|
k3_pds: power-controller {
|
|
|
|
|
compatible = "ti,sci-pm-domain";
|
|
|
|
|
#power-domain-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
2021-09-10 21:37:43 +00:00
|
|
|
k3_clks: clock-controller {
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
compatible = "ti,k2g-sci-clk";
|
|
|
|
|
#clock-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
k3_reset: reset-controller {
|
|
|
|
|
compatible = "ti,sci-reset";
|
|
|
|
|
#reset-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_pmx0: pinctrl@f4000 {
|
|
|
|
|
compatible = "pinctrl-single";
|
|
|
|
|
reg = <0x00 0xf4000 0x00 0x2d0>;
|
|
|
|
|
#pinctrl-cells = <1>;
|
|
|
|
|
pinctrl-single,register-width = <32>;
|
|
|
|
|
pinctrl-single,function-mask = <0xffffffff>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_conf: syscon@43000000 {
|
|
|
|
|
compatible = "syscon", "simple-mfd";
|
|
|
|
|
reg = <0x00 0x43000000 0x00 0x20000>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x00 0x00 0x43000000 0x20000>;
|
|
|
|
|
|
|
|
|
|
chipid@14 {
|
|
|
|
|
compatible = "ti,am654-chipid";
|
|
|
|
|
reg = <0x00000014 0x4>;
|
|
|
|
|
};
|
2021-05-10 14:36:12 +00:00
|
|
|
|
|
|
|
|
phy_gmii_sel: phy@4044 {
|
|
|
|
|
compatible = "ti,am654-phy-gmii-sel";
|
|
|
|
|
reg = <0x4044 0x8>;
|
|
|
|
|
#phy-cells = <1>;
|
|
|
|
|
};
|
2023-01-24 09:43:25 +00:00
|
|
|
|
|
|
|
|
epwm_tbclk: clock@4140 {
|
|
|
|
|
compatible = "ti,am64-epwm-tbclk", "syscon";
|
|
|
|
|
reg = <0x4130 0x4>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart0: serial@2800000 {
|
|
|
|
|
compatible = "ti,am64-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02800000 0x00 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 146 0>;
|
|
|
|
|
clock-names = "fclk";
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart1: serial@2810000 {
|
|
|
|
|
compatible = "ti,am64-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02810000 0x00 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 152 0>;
|
|
|
|
|
clock-names = "fclk";
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart2: serial@2820000 {
|
|
|
|
|
compatible = "ti,am64-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02820000 0x00 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 153 0>;
|
|
|
|
|
clock-names = "fclk";
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart3: serial@2830000 {
|
|
|
|
|
compatible = "ti,am64-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02830000 0x00 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 154 0>;
|
|
|
|
|
clock-names = "fclk";
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart4: serial@2840000 {
|
|
|
|
|
compatible = "ti,am64-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02840000 0x00 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 155 0>;
|
|
|
|
|
clock-names = "fclk";
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart5: serial@2850000 {
|
|
|
|
|
compatible = "ti,am64-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02850000 0x00 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 156 0>;
|
|
|
|
|
clock-names = "fclk";
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart6: serial@2860000 {
|
|
|
|
|
compatible = "ti,am64-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02860000 0x00 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 158 0>;
|
|
|
|
|
clock-names = "fclk";
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c0: i2c@20000000 {
|
|
|
|
|
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
|
|
|
|
reg = <0x00 0x20000000 0x00 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 102 2>;
|
|
|
|
|
clock-names = "fck";
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c1: i2c@20010000 {
|
|
|
|
|
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
|
|
|
|
reg = <0x00 0x20010000 0x00 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 103 2>;
|
|
|
|
|
clock-names = "fck";
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c2: i2c@20020000 {
|
|
|
|
|
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
|
|
|
|
reg = <0x00 0x20020000 0x00 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 104 2>;
|
|
|
|
|
clock-names = "fck";
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c3: i2c@20030000 {
|
|
|
|
|
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
|
|
|
|
reg = <0x00 0x20030000 0x00 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 105 2>;
|
|
|
|
|
clock-names = "fck";
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_spi0: spi@20100000 {
|
|
|
|
|
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x00 0x20100000 0x00 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 141 0>;
|
|
|
|
|
dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
|
|
|
|
|
dma-names = "tx0", "rx0";
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_spi1: spi@20110000 {
|
|
|
|
|
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
|
|
|
|
reg = <0x00 0x20110000 0x00 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 142 0>;
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_spi2: spi@20120000 {
|
|
|
|
|
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
|
|
|
|
reg = <0x00 0x20120000 0x00 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 143 0>;
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_spi3: spi@20130000 {
|
|
|
|
|
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
|
|
|
|
reg = <0x00 0x20130000 0x00 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 144 0>;
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_spi4: spi@20140000 {
|
|
|
|
|
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
|
|
|
|
reg = <0x00 0x20140000 0x00 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 145 0>;
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
|
|
|
|
|
2021-09-10 21:37:43 +00:00
|
|
|
main_gpio_intr: interrupt-controller@a00000 {
|
|
|
|
|
compatible = "ti,sci-intr";
|
|
|
|
|
reg = <0x00 0x00a00000 0x00 0x800>;
|
|
|
|
|
ti,intr-trigger-type = <1>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
interrupt-parent = <&gic500>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dev-id = <3>;
|
|
|
|
|
ti,interrupt-ranges = <0 32 16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_gpio0: gpio@600000 {
|
|
|
|
|
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
|
|
|
|
reg = <0x0 0x00600000 0x0 0x100>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-parent = <&main_gpio_intr>;
|
|
|
|
|
interrupts = <190>, <191>, <192>,
|
|
|
|
|
<193>, <194>, <195>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ti,ngpio = <87>;
|
|
|
|
|
ti,davinci-gpio-unbanked = <0>;
|
|
|
|
|
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 77 0>;
|
|
|
|
|
clock-names = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_gpio1: gpio@601000 {
|
|
|
|
|
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
|
|
|
|
reg = <0x0 0x00601000 0x0 0x100>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-parent = <&main_gpio_intr>;
|
|
|
|
|
interrupts = <180>, <181>, <182>,
|
|
|
|
|
<183>, <184>, <185>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ti,ngpio = <88>;
|
|
|
|
|
ti,davinci-gpio-unbanked = <0>;
|
|
|
|
|
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 78 0>;
|
|
|
|
|
clock-names = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
sdhci0: mmc@fa10000 {
|
|
|
|
|
compatible = "ti,am64-sdhci-8bit";
|
|
|
|
|
reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
|
|
|
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
|
|
|
|
|
clock-names = "clk_ahb", "clk_xin";
|
|
|
|
|
mmc-ddr-1_8v;
|
|
|
|
|
mmc-hs200-1_8v;
|
|
|
|
|
ti,trm-icp = <0x2>;
|
|
|
|
|
ti,otap-del-sel-legacy = <0x0>;
|
|
|
|
|
ti,otap-del-sel-mmc-hs = <0x0>;
|
|
|
|
|
ti,otap-del-sel-ddr52 = <0x6>;
|
|
|
|
|
ti,otap-del-sel-hs200 = <0x7>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdhci1: mmc@fa00000 {
|
|
|
|
|
compatible = "ti,am64-sdhci-4bit";
|
|
|
|
|
reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
|
|
|
|
|
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
|
|
|
|
|
clock-names = "clk_ahb", "clk_xin";
|
|
|
|
|
ti,trm-icp = <0x2>;
|
|
|
|
|
ti,otap-del-sel-legacy = <0x0>;
|
|
|
|
|
ti,otap-del-sel-sd-hs = <0xf>;
|
|
|
|
|
ti,otap-del-sel-sdr12 = <0xf>;
|
|
|
|
|
ti,otap-del-sel-sdr25 = <0xf>;
|
|
|
|
|
ti,otap-del-sel-sdr50 = <0xc>;
|
|
|
|
|
ti,otap-del-sel-sdr104 = <0x6>;
|
|
|
|
|
ti,otap-del-sel-ddr50 = <0x9>;
|
|
|
|
|
ti,clkbuf-sel = <0x7>;
|
|
|
|
|
};
|
2021-05-04 23:00:54 +00:00
|
|
|
|
2021-05-10 14:36:12 +00:00
|
|
|
cpsw3g: ethernet@8000000 {
|
|
|
|
|
compatible = "ti,am642-cpsw-nuss";
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
reg = <0x0 0x8000000 0x0 0x200000>;
|
|
|
|
|
reg-names = "cpsw_nuss";
|
|
|
|
|
ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
|
|
|
|
|
clocks = <&k3_clks 13 0>;
|
|
|
|
|
assigned-clocks = <&k3_clks 13 1>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 13 9>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
|
|
|
|
|
dmas = <&main_pktdma 0xC500 15>,
|
|
|
|
|
<&main_pktdma 0xC501 15>,
|
|
|
|
|
<&main_pktdma 0xC502 15>,
|
|
|
|
|
<&main_pktdma 0xC503 15>,
|
|
|
|
|
<&main_pktdma 0xC504 15>,
|
|
|
|
|
<&main_pktdma 0xC505 15>,
|
|
|
|
|
<&main_pktdma 0xC506 15>,
|
|
|
|
|
<&main_pktdma 0xC507 15>,
|
|
|
|
|
<&main_pktdma 0x4500 15>;
|
|
|
|
|
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
|
|
|
|
|
"tx7", "rx";
|
|
|
|
|
|
|
|
|
|
ethernet-ports {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
cpsw_port1: port@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
ti,mac-only;
|
|
|
|
|
label = "port1";
|
|
|
|
|
phys = <&phy_gmii_sel 1>;
|
2021-09-10 21:37:43 +00:00
|
|
|
mac-address = [00 00 00 00 00 00];
|
|
|
|
|
ti,syscon-efuse = <&main_conf 0x200>;
|
2021-05-10 14:36:12 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpsw_port2: port@2 {
|
|
|
|
|
reg = <2>;
|
|
|
|
|
ti,mac-only;
|
|
|
|
|
label = "port2";
|
|
|
|
|
phys = <&phy_gmii_sel 2>;
|
2021-09-10 21:37:43 +00:00
|
|
|
mac-address = [00 00 00 00 00 00];
|
2021-05-10 14:36:12 +00:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpsw3g_mdio: mdio@f00 {
|
|
|
|
|
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
|
|
|
|
reg = <0x0 0xf00 0x0 0x100>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clocks = <&k3_clks 13 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
bus_freq = <1000000>;
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
2021-05-10 14:36:12 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpts@3d000 {
|
|
|
|
|
compatible = "ti,j721e-cpts";
|
|
|
|
|
reg = <0x0 0x3d000 0x0 0x400>;
|
|
|
|
|
clocks = <&k3_clks 13 1>;
|
|
|
|
|
clock-names = "cpts";
|
|
|
|
|
interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "cpts";
|
|
|
|
|
ti,cpts-ext-ts-inputs = <4>;
|
|
|
|
|
ti,cpts-periodic-outputs = <2>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2023-01-24 09:43:25 +00:00
|
|
|
main_cpts0: cpts@39000000 {
|
2021-09-10 21:37:43 +00:00
|
|
|
compatible = "ti,j721e-cpts";
|
|
|
|
|
reg = <0x0 0x39000000 0x0 0x400>;
|
|
|
|
|
reg-names = "cpts";
|
|
|
|
|
power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 84 0>;
|
|
|
|
|
clock-names = "cpts";
|
|
|
|
|
assigned-clocks = <&k3_clks 84 0>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 84 8>;
|
|
|
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "cpts";
|
|
|
|
|
ti,cpts-periodic-outputs = <6>;
|
|
|
|
|
ti,cpts-ext-ts-inputs = <8>;
|
2021-05-04 23:00:54 +00:00
|
|
|
};
|
|
|
|
|
|
2023-01-24 09:43:25 +00:00
|
|
|
timesync_router: pinctrl@a40000 {
|
|
|
|
|
compatible = "pinctrl-single";
|
|
|
|
|
reg = <0x0 0xa40000 0x0 0x800>;
|
|
|
|
|
#pinctrl-cells = <1>;
|
|
|
|
|
pinctrl-single,register-width = <32>;
|
|
|
|
|
pinctrl-single,function-mask = <0x000107ff>;
|
|
|
|
|
};
|
|
|
|
|
|
2021-06-04 16:30:35 +00:00
|
|
|
usbss0: cdns-usb@f900000{
|
2021-09-10 21:37:43 +00:00
|
|
|
compatible = "ti,am64-usb";
|
2021-06-04 16:30:35 +00:00
|
|
|
reg = <0x00 0xf900000 0x00 0x100>;
|
|
|
|
|
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
|
|
|
|
|
clock-names = "ref", "lpm";
|
|
|
|
|
assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
|
|
|
|
|
assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
usb0: usb@f400000{
|
|
|
|
|
compatible = "cdns,usb3";
|
|
|
|
|
reg = <0x00 0xf400000 0x00 0x10000>,
|
|
|
|
|
<0x00 0xf410000 0x00 0x10000>,
|
|
|
|
|
<0x00 0xf420000 0x00 0x10000>;
|
|
|
|
|
reg-names = "otg",
|
|
|
|
|
"xhci",
|
|
|
|
|
"dev";
|
|
|
|
|
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
|
|
|
|
|
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
|
|
|
|
|
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
|
|
|
|
|
interrupt-names = "host",
|
|
|
|
|
"peripheral",
|
|
|
|
|
"otg";
|
|
|
|
|
maximum-speed = "super-speed";
|
|
|
|
|
dr_mode = "otg";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2021-09-10 21:37:43 +00:00
|
|
|
tscadc0: tscadc@28001000 {
|
|
|
|
|
compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
|
|
|
|
|
reg = <0x00 0x28001000 0x00 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 0 0>;
|
|
|
|
|
assigned-clocks = <&k3_clks 0 0>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 0 3>;
|
|
|
|
|
assigned-clock-rates = <60000000>;
|
2023-01-24 09:43:25 +00:00
|
|
|
clock-names = "fck";
|
2021-09-10 21:37:43 +00:00
|
|
|
|
|
|
|
|
adc {
|
|
|
|
|
#io-channel-cells = <1>;
|
|
|
|
|
compatible = "ti,am654-adc", "ti,am3359-adc";
|
|
|
|
|
};
|
2021-05-04 23:00:54 +00:00
|
|
|
};
|
2021-05-06 11:14:58 +00:00
|
|
|
|
2021-09-10 21:37:43 +00:00
|
|
|
fss: bus@fc00000 {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
reg = <0x00 0x0fc00000 0x00 0x70000>;
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
ospi0: spi@fc40000 {
|
|
|
|
|
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
|
|
|
|
reg = <0x00 0x0fc40000 0x00 0x100>,
|
|
|
|
|
<0x05 0x00000000 0x01 0x00000000>;
|
|
|
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
cdns,fifo-depth = <256>;
|
|
|
|
|
cdns,fifo-width = <4>;
|
|
|
|
|
cdns,trigger-address = <0x0>;
|
|
|
|
|
#address-cells = <0x1>;
|
|
|
|
|
#size-cells = <0x0>;
|
|
|
|
|
clocks = <&k3_clks 75 6>;
|
|
|
|
|
assigned-clocks = <&k3_clks 75 6>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 75 7>;
|
|
|
|
|
assigned-clock-rates = <166666666>;
|
|
|
|
|
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
};
|
2021-05-06 11:14:58 +00:00
|
|
|
};
|
|
|
|
|
|
2021-09-10 21:37:43 +00:00
|
|
|
hwspinlock: spinlock@2a000000 {
|
|
|
|
|
compatible = "ti,am64-hwspinlock";
|
|
|
|
|
reg = <0x00 0x2a000000 0x00 0x1000>;
|
|
|
|
|
#hwlock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mailbox0_cluster2: mailbox@29020000 {
|
|
|
|
|
compatible = "ti,am64-mailbox";
|
|
|
|
|
reg = <0x00 0x29020000 0x00 0x200>;
|
|
|
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#mbox-cells = <1>;
|
|
|
|
|
ti,mbox-num-users = <4>;
|
|
|
|
|
ti,mbox-num-fifos = <16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mailbox0_cluster3: mailbox@29030000 {
|
|
|
|
|
compatible = "ti,am64-mailbox";
|
|
|
|
|
reg = <0x00 0x29030000 0x00 0x200>;
|
|
|
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#mbox-cells = <1>;
|
|
|
|
|
ti,mbox-num-users = <4>;
|
|
|
|
|
ti,mbox-num-fifos = <16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mailbox0_cluster4: mailbox@29040000 {
|
|
|
|
|
compatible = "ti,am64-mailbox";
|
|
|
|
|
reg = <0x00 0x29040000 0x00 0x200>;
|
|
|
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#mbox-cells = <1>;
|
|
|
|
|
ti,mbox-num-users = <4>;
|
|
|
|
|
ti,mbox-num-fifos = <16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mailbox0_cluster5: mailbox@29050000 {
|
|
|
|
|
compatible = "ti,am64-mailbox";
|
|
|
|
|
reg = <0x00 0x29050000 0x00 0x200>;
|
|
|
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#mbox-cells = <1>;
|
|
|
|
|
ti,mbox-num-users = <4>;
|
|
|
|
|
ti,mbox-num-fifos = <16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mailbox0_cluster6: mailbox@29060000 {
|
|
|
|
|
compatible = "ti,am64-mailbox";
|
|
|
|
|
reg = <0x00 0x29060000 0x00 0x200>;
|
|
|
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#mbox-cells = <1>;
|
|
|
|
|
ti,mbox-num-users = <4>;
|
|
|
|
|
ti,mbox-num-fifos = <16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mailbox0_cluster7: mailbox@29070000 {
|
|
|
|
|
compatible = "ti,am64-mailbox";
|
|
|
|
|
reg = <0x00 0x29070000 0x00 0x200>;
|
|
|
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#mbox-cells = <1>;
|
|
|
|
|
ti,mbox-num-users = <4>;
|
|
|
|
|
ti,mbox-num-fifos = <16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_r5fss0: r5fss@78000000 {
|
|
|
|
|
compatible = "ti,am64-r5fss";
|
|
|
|
|
ti,cluster-mode = <0>;
|
2021-05-06 11:14:58 +00:00
|
|
|
#address-cells = <1>;
|
2021-09-10 21:37:43 +00:00
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x78000000 0x00 0x78000000 0x10000>,
|
|
|
|
|
<0x78100000 0x00 0x78100000 0x10000>,
|
|
|
|
|
<0x78200000 0x00 0x78200000 0x08000>,
|
|
|
|
|
<0x78300000 0x00 0x78300000 0x08000>;
|
|
|
|
|
power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
|
|
|
|
|
main_r5fss0_core0: r5f@78000000 {
|
|
|
|
|
compatible = "ti,am64-r5f";
|
|
|
|
|
reg = <0x78000000 0x00010000>,
|
|
|
|
|
<0x78100000 0x00010000>;
|
|
|
|
|
reg-names = "atcm", "btcm";
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dev-id = <121>;
|
|
|
|
|
ti,sci-proc-ids = <0x01 0xff>;
|
|
|
|
|
resets = <&k3_reset 121 1>;
|
|
|
|
|
firmware-name = "am64-main-r5f0_0-fw";
|
|
|
|
|
ti,atcm-enable = <1>;
|
|
|
|
|
ti,btcm-enable = <1>;
|
|
|
|
|
ti,loczrama = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_r5fss0_core1: r5f@78200000 {
|
|
|
|
|
compatible = "ti,am64-r5f";
|
|
|
|
|
reg = <0x78200000 0x00008000>,
|
|
|
|
|
<0x78300000 0x00008000>;
|
|
|
|
|
reg-names = "atcm", "btcm";
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dev-id = <122>;
|
|
|
|
|
ti,sci-proc-ids = <0x02 0xff>;
|
|
|
|
|
resets = <&k3_reset 122 1>;
|
|
|
|
|
firmware-name = "am64-main-r5f0_1-fw";
|
|
|
|
|
ti,atcm-enable = <1>;
|
|
|
|
|
ti,btcm-enable = <1>;
|
|
|
|
|
ti,loczrama = <1>;
|
|
|
|
|
};
|
2021-05-06 11:14:58 +00:00
|
|
|
};
|
|
|
|
|
|
2021-09-10 21:37:43 +00:00
|
|
|
main_r5fss1: r5fss@78400000 {
|
|
|
|
|
compatible = "ti,am64-r5fss";
|
|
|
|
|
ti,cluster-mode = <0>;
|
2021-05-06 11:14:58 +00:00
|
|
|
#address-cells = <1>;
|
2021-09-10 21:37:43 +00:00
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x78400000 0x00 0x78400000 0x10000>,
|
|
|
|
|
<0x78500000 0x00 0x78500000 0x10000>,
|
|
|
|
|
<0x78600000 0x00 0x78600000 0x08000>,
|
|
|
|
|
<0x78700000 0x00 0x78700000 0x08000>;
|
|
|
|
|
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
|
|
|
|
|
main_r5fss1_core0: r5f@78400000 {
|
|
|
|
|
compatible = "ti,am64-r5f";
|
|
|
|
|
reg = <0x78400000 0x00010000>,
|
|
|
|
|
<0x78500000 0x00010000>;
|
|
|
|
|
reg-names = "atcm", "btcm";
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dev-id = <123>;
|
|
|
|
|
ti,sci-proc-ids = <0x06 0xff>;
|
|
|
|
|
resets = <&k3_reset 123 1>;
|
|
|
|
|
firmware-name = "am64-main-r5f1_0-fw";
|
|
|
|
|
ti,atcm-enable = <1>;
|
|
|
|
|
ti,btcm-enable = <1>;
|
|
|
|
|
ti,loczrama = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_r5fss1_core1: r5f@78600000 {
|
|
|
|
|
compatible = "ti,am64-r5f";
|
|
|
|
|
reg = <0x78600000 0x00008000>,
|
|
|
|
|
<0x78700000 0x00008000>;
|
|
|
|
|
reg-names = "atcm", "btcm";
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dev-id = <124>;
|
|
|
|
|
ti,sci-proc-ids = <0x07 0xff>;
|
|
|
|
|
resets = <&k3_reset 124 1>;
|
|
|
|
|
firmware-name = "am64-main-r5f1_1-fw";
|
|
|
|
|
ti,atcm-enable = <1>;
|
|
|
|
|
ti,btcm-enable = <1>;
|
|
|
|
|
ti,loczrama = <1>;
|
|
|
|
|
};
|
2021-05-06 11:14:58 +00:00
|
|
|
};
|
|
|
|
|
|
2021-09-10 21:37:43 +00:00
|
|
|
serdes_wiz0: wiz@f000000 {
|
|
|
|
|
compatible = "ti,am64-wiz-10g";
|
2021-05-06 11:14:58 +00:00
|
|
|
#address-cells = <1>;
|
2021-09-10 21:37:43 +00:00
|
|
|
#size-cells = <1>;
|
|
|
|
|
power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
|
|
|
|
|
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
|
|
|
|
num-lanes = <1>;
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
|
|
|
|
|
|
|
|
|
|
assigned-clocks = <&k3_clks 162 1>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 162 5>;
|
|
|
|
|
|
|
|
|
|
serdes0: serdes@f000000 {
|
|
|
|
|
compatible = "ti,j721e-serdes-10g";
|
|
|
|
|
reg = <0x0f000000 0x00010000>;
|
|
|
|
|
reg-names = "torrent_phy";
|
|
|
|
|
resets = <&serdes_wiz0 0>;
|
|
|
|
|
reset-names = "torrent_reset";
|
|
|
|
|
clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
|
|
|
|
|
<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
|
|
|
|
|
clock-names = "refclk", "phy_en_refclk";
|
|
|
|
|
assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
|
|
|
|
|
<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
|
|
|
|
|
<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 162 1>,
|
|
|
|
|
<&k3_clks 162 1>,
|
|
|
|
|
<&k3_clks 162 1>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie0_rc: pcie@f102000 {
|
|
|
|
|
compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
|
|
|
|
|
reg = <0x00 0x0f102000 0x00 0x1000>,
|
|
|
|
|
<0x00 0x0f100000 0x00 0x400>,
|
|
|
|
|
<0x00 0x0d000000 0x00 0x00800000>,
|
|
|
|
|
<0x00 0x68000000 0x00 0x00001000>;
|
|
|
|
|
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
|
|
|
|
interrupt-names = "link_state";
|
|
|
|
|
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
|
|
|
|
|
max-link-speed = <2>;
|
|
|
|
|
num-lanes = <1>;
|
|
|
|
|
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
|
|
|
|
|
clock-names = "fck", "pcie_refclk";
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
bus-range = <0x0 0xff>;
|
|
|
|
|
cdns,no-bar-match-nbits = <64>;
|
|
|
|
|
vendor-id = <0x104c>;
|
|
|
|
|
device-id = <0xb010>;
|
|
|
|
|
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
|
|
|
|
ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
|
|
|
|
|
<0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
|
|
|
|
|
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
2021-09-10 21:37:43 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie0_ep: pcie-ep@f102000 {
|
|
|
|
|
compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
|
|
|
|
|
reg = <0x00 0x0f102000 0x00 0x1000>,
|
|
|
|
|
<0x00 0x0f100000 0x00 0x400>,
|
|
|
|
|
<0x00 0x0d000000 0x00 0x00800000>,
|
|
|
|
|
<0x00 0x68000000 0x00 0x08000000>;
|
|
|
|
|
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
|
|
|
|
interrupt-names = "link_state";
|
|
|
|
|
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
|
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
|
|
|
|
|
max-link-speed = <2>;
|
|
|
|
|
num-lanes = <1>;
|
|
|
|
|
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 114 0>;
|
2021-05-06 11:14:58 +00:00
|
|
|
clock-names = "fck";
|
2021-09-10 21:37:43 +00:00
|
|
|
max-functions = /bits/ 8 <1>;
|
2023-01-24 09:43:25 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epwm0: pwm@23000000 {
|
|
|
|
|
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x23000000 0x0 0x100>;
|
|
|
|
|
power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
|
|
|
|
|
clock-names = "tbclk", "fck";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epwm1: pwm@23010000 {
|
|
|
|
|
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x23010000 0x0 0x100>;
|
|
|
|
|
power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
|
|
|
|
|
clock-names = "tbclk", "fck";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epwm2: pwm@23020000 {
|
|
|
|
|
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x23020000 0x0 0x100>;
|
|
|
|
|
power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
|
|
|
|
|
clock-names = "tbclk", "fck";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epwm3: pwm@23030000 {
|
|
|
|
|
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x23030000 0x0 0x100>;
|
|
|
|
|
power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
|
|
|
|
|
clock-names = "tbclk", "fck";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epwm4: pwm@23040000 {
|
|
|
|
|
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x23040000 0x0 0x100>;
|
|
|
|
|
power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
|
|
|
|
|
clock-names = "tbclk", "fck";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epwm5: pwm@23050000 {
|
|
|
|
|
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x23050000 0x0 0x100>;
|
|
|
|
|
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
|
|
|
|
|
clock-names = "tbclk", "fck";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epwm6: pwm@23060000 {
|
|
|
|
|
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x23060000 0x0 0x100>;
|
|
|
|
|
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
|
|
|
|
|
clock-names = "tbclk", "fck";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epwm7: pwm@23070000 {
|
|
|
|
|
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x23070000 0x0 0x100>;
|
|
|
|
|
power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
|
|
|
|
|
clock-names = "tbclk", "fck";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epwm8: pwm@23080000 {
|
|
|
|
|
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x23080000 0x0 0x100>;
|
|
|
|
|
power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
|
|
|
|
|
clock-names = "tbclk", "fck";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ecap0: pwm@23100000 {
|
|
|
|
|
compatible = "ti,am64-ecap", "ti,am3352-ecap";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x23100000 0x0 0x60>;
|
|
|
|
|
power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 51 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ecap1: pwm@23110000 {
|
|
|
|
|
compatible = "ti,am64-ecap", "ti,am3352-ecap";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x23110000 0x0 0x60>;
|
|
|
|
|
power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 52 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ecap2: pwm@23120000 {
|
|
|
|
|
compatible = "ti,am64-ecap", "ti,am3352-ecap";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x23120000 0x0 0x60>;
|
|
|
|
|
power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 53 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
status = "disabled";
|
2021-05-06 11:14:58 +00:00
|
|
|
};
|
2022-10-26 11:15:55 +00:00
|
|
|
|
|
|
|
|
main_rti0: watchdog@e000000 {
|
2023-01-24 09:43:25 +00:00
|
|
|
compatible = "ti,j7-rti-wdt";
|
|
|
|
|
reg = <0x00 0xe000000 0x00 0x100>;
|
|
|
|
|
clocks = <&k3_clks 125 0>;
|
|
|
|
|
power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
assigned-clocks = <&k3_clks 125 0>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 125 2>;
|
2022-10-26 11:15:55 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_rti1: watchdog@e010000 {
|
2023-01-24 09:43:25 +00:00
|
|
|
compatible = "ti,j7-rti-wdt";
|
|
|
|
|
reg = <0x00 0xe010000 0x00 0x100>;
|
|
|
|
|
clocks = <&k3_clks 126 0>;
|
|
|
|
|
power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
assigned-clocks = <&k3_clks 126 0>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 126 2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg0: icssg@30000000 {
|
|
|
|
|
compatible = "ti,am642-icssg";
|
|
|
|
|
reg = <0x00 0x30000000 0x00 0x80000>;
|
|
|
|
|
power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x00 0x30000000 0x80000>;
|
|
|
|
|
|
|
|
|
|
icssg0_mem: memories@0 {
|
|
|
|
|
reg = <0x0 0x2000>,
|
|
|
|
|
<0x2000 0x2000>,
|
|
|
|
|
<0x10000 0x10000>;
|
|
|
|
|
reg-names = "dram0", "dram1", "shrdram2";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg0_cfg: cfg@26000 {
|
|
|
|
|
compatible = "ti,pruss-cfg", "syscon";
|
|
|
|
|
reg = <0x26000 0x200>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x26000 0x2000>;
|
|
|
|
|
|
|
|
|
|
clocks {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
icssg0_coreclk_mux: coreclk-mux@3c {
|
|
|
|
|
reg = <0x3c>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
|
|
|
|
|
<&k3_clks 81 20>; /* icssg0_iclk */
|
|
|
|
|
assigned-clocks = <&icssg0_coreclk_mux>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 81 20>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg0_iepclk_mux: iepclk-mux@30 {
|
|
|
|
|
reg = <0x30>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */
|
|
|
|
|
<&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */
|
|
|
|
|
assigned-clocks = <&icssg0_iepclk_mux>;
|
|
|
|
|
assigned-clock-parents = <&icssg0_coreclk_mux>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg0_mii_rt: mii-rt@32000 {
|
|
|
|
|
compatible = "ti,pruss-mii", "syscon";
|
|
|
|
|
reg = <0x32000 0x100>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg0_mii_g_rt: mii-g-rt@33000 {
|
|
|
|
|
compatible = "ti,pruss-mii-g", "syscon";
|
|
|
|
|
reg = <0x33000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg0_intc: interrupt-controller@20000 {
|
|
|
|
|
compatible = "ti,icssg-intc";
|
|
|
|
|
reg = <0x20000 0x2000>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <3>;
|
|
|
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "host_intr0", "host_intr1",
|
|
|
|
|
"host_intr2", "host_intr3",
|
|
|
|
|
"host_intr4", "host_intr5",
|
|
|
|
|
"host_intr6", "host_intr7";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pru0_0: pru@34000 {
|
|
|
|
|
compatible = "ti,am642-pru";
|
|
|
|
|
reg = <0x34000 0x3000>,
|
|
|
|
|
<0x22000 0x100>,
|
|
|
|
|
<0x22400 0x100>;
|
|
|
|
|
reg-names = "iram", "control", "debug";
|
|
|
|
|
firmware-name = "am64x-pru0_0-fw";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
rtu0_0: rtu@4000 {
|
|
|
|
|
compatible = "ti,am642-rtu";
|
|
|
|
|
reg = <0x4000 0x2000>,
|
|
|
|
|
<0x23000 0x100>,
|
|
|
|
|
<0x23400 0x100>;
|
|
|
|
|
reg-names = "iram", "control", "debug";
|
|
|
|
|
firmware-name = "am64x-rtu0_0-fw";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tx_pru0_0: txpru@a000 {
|
|
|
|
|
compatible = "ti,am642-tx-pru";
|
|
|
|
|
reg = <0xa000 0x1800>,
|
|
|
|
|
<0x25000 0x100>,
|
|
|
|
|
<0x25400 0x100>;
|
|
|
|
|
reg-names = "iram", "control", "debug";
|
|
|
|
|
firmware-name = "am64x-txpru0_0-fw";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pru0_1: pru@38000 {
|
|
|
|
|
compatible = "ti,am642-pru";
|
|
|
|
|
reg = <0x38000 0x3000>,
|
|
|
|
|
<0x24000 0x100>,
|
|
|
|
|
<0x24400 0x100>;
|
|
|
|
|
reg-names = "iram", "control", "debug";
|
|
|
|
|
firmware-name = "am64x-pru0_1-fw";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
rtu0_1: rtu@6000 {
|
|
|
|
|
compatible = "ti,am642-rtu";
|
|
|
|
|
reg = <0x6000 0x2000>,
|
|
|
|
|
<0x23800 0x100>,
|
|
|
|
|
<0x23c00 0x100>;
|
|
|
|
|
reg-names = "iram", "control", "debug";
|
|
|
|
|
firmware-name = "am64x-rtu0_1-fw";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tx_pru0_1: txpru@c000 {
|
|
|
|
|
compatible = "ti,am642-tx-pru";
|
|
|
|
|
reg = <0xc000 0x1800>,
|
|
|
|
|
<0x25800 0x100>,
|
|
|
|
|
<0x25c00 0x100>;
|
|
|
|
|
reg-names = "iram", "control", "debug";
|
|
|
|
|
firmware-name = "am64x-txpru0_1-fw";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg0_mdio: mdio@32400 {
|
|
|
|
|
compatible = "ti,davinci_mdio";
|
|
|
|
|
reg = <0x32400 0x100>;
|
|
|
|
|
clocks = <&k3_clks 62 3>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
bus_freq = <1000000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg1: icssg@30080000 {
|
|
|
|
|
compatible = "ti,am642-icssg";
|
|
|
|
|
reg = <0x00 0x30080000 0x00 0x80000>;
|
|
|
|
|
power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x00 0x30080000 0x80000>;
|
|
|
|
|
|
|
|
|
|
icssg1_mem: memories@0 {
|
|
|
|
|
reg = <0x0 0x2000>,
|
|
|
|
|
<0x2000 0x2000>,
|
|
|
|
|
<0x10000 0x10000>;
|
|
|
|
|
reg-names = "dram0", "dram1", "shrdram2";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg1_cfg: cfg@26000 {
|
|
|
|
|
compatible = "ti,pruss-cfg", "syscon";
|
|
|
|
|
reg = <0x26000 0x200>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x26000 0x2000>;
|
|
|
|
|
|
|
|
|
|
clocks {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
icssg1_coreclk_mux: coreclk-mux@3c {
|
|
|
|
|
reg = <0x3c>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
|
|
|
|
|
<&k3_clks 82 20>; /* icssg1_iclk */
|
|
|
|
|
assigned-clocks = <&icssg1_coreclk_mux>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 82 20>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg1_iepclk_mux: iepclk-mux@30 {
|
|
|
|
|
reg = <0x30>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */
|
|
|
|
|
<&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */
|
|
|
|
|
assigned-clocks = <&icssg1_iepclk_mux>;
|
|
|
|
|
assigned-clock-parents = <&icssg1_coreclk_mux>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg1_mii_rt: mii-rt@32000 {
|
|
|
|
|
compatible = "ti,pruss-mii", "syscon";
|
|
|
|
|
reg = <0x32000 0x100>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg1_mii_g_rt: mii-g-rt@33000 {
|
|
|
|
|
compatible = "ti,pruss-mii-g", "syscon";
|
|
|
|
|
reg = <0x33000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg1_intc: interrupt-controller@20000 {
|
|
|
|
|
compatible = "ti,icssg-intc";
|
|
|
|
|
reg = <0x20000 0x2000>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <3>;
|
|
|
|
|
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "host_intr0", "host_intr1",
|
|
|
|
|
"host_intr2", "host_intr3",
|
|
|
|
|
"host_intr4", "host_intr5",
|
|
|
|
|
"host_intr6", "host_intr7";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pru1_0: pru@34000 {
|
|
|
|
|
compatible = "ti,am642-pru";
|
|
|
|
|
reg = <0x34000 0x4000>,
|
|
|
|
|
<0x22000 0x100>,
|
|
|
|
|
<0x22400 0x100>;
|
|
|
|
|
reg-names = "iram", "control", "debug";
|
|
|
|
|
firmware-name = "am64x-pru1_0-fw";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
rtu1_0: rtu@4000 {
|
|
|
|
|
compatible = "ti,am642-rtu";
|
|
|
|
|
reg = <0x4000 0x2000>,
|
|
|
|
|
<0x23000 0x100>,
|
|
|
|
|
<0x23400 0x100>;
|
|
|
|
|
reg-names = "iram", "control", "debug";
|
|
|
|
|
firmware-name = "am64x-rtu1_0-fw";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tx_pru1_0: txpru@a000 {
|
|
|
|
|
compatible = "ti,am642-tx-pru";
|
|
|
|
|
reg = <0xa000 0x1800>,
|
|
|
|
|
<0x25000 0x100>,
|
|
|
|
|
<0x25400 0x100>;
|
|
|
|
|
reg-names = "iram", "control", "debug";
|
|
|
|
|
firmware-name = "am64x-txpru1_0-fw";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pru1_1: pru@38000 {
|
|
|
|
|
compatible = "ti,am642-pru";
|
|
|
|
|
reg = <0x38000 0x4000>,
|
|
|
|
|
<0x24000 0x100>,
|
|
|
|
|
<0x24400 0x100>;
|
|
|
|
|
reg-names = "iram", "control", "debug";
|
|
|
|
|
firmware-name = "am64x-pru1_1-fw";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
rtu1_1: rtu@6000 {
|
|
|
|
|
compatible = "ti,am642-rtu";
|
|
|
|
|
reg = <0x6000 0x2000>,
|
|
|
|
|
<0x23800 0x100>,
|
|
|
|
|
<0x23c00 0x100>;
|
|
|
|
|
reg-names = "iram", "control", "debug";
|
|
|
|
|
firmware-name = "am64x-rtu1_1-fw";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tx_pru1_1: txpru@c000 {
|
|
|
|
|
compatible = "ti,am642-tx-pru";
|
|
|
|
|
reg = <0xc000 0x1800>,
|
|
|
|
|
<0x25800 0x100>,
|
|
|
|
|
<0x25c00 0x100>;
|
|
|
|
|
reg-names = "iram", "control", "debug";
|
|
|
|
|
firmware-name = "am64x-txpru1_1-fw";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
icssg1_mdio: mdio@32400 {
|
|
|
|
|
compatible = "ti,davinci_mdio";
|
|
|
|
|
reg = <0x32400 0x100>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clocks = <&k3_clks 82 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
bus_freq = <1000000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_mcan0: can@20701000 {
|
|
|
|
|
compatible = "bosch,m_can";
|
|
|
|
|
reg = <0x00 0x20701000 0x00 0x200>,
|
|
|
|
|
<0x00 0x20708000 0x00 0x8000>;
|
|
|
|
|
reg-names = "m_can", "message_ram";
|
|
|
|
|
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 98 5>, <&k3_clks 98 0>;
|
|
|
|
|
clock-names = "hclk", "cclk";
|
|
|
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "int0", "int1";
|
|
|
|
|
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_mcan1: can@20711000 {
|
|
|
|
|
compatible = "bosch,m_can";
|
|
|
|
|
reg = <0x00 0x20711000 0x00 0x200>,
|
|
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|
|
<0x00 0x20718000 0x00 0x8000>;
|
|
|
|
|
reg-names = "m_can", "message_ram";
|
|
|
|
|
power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 99 5>, <&k3_clks 99 0>;
|
|
|
|
|
clock-names = "hclk", "cclk";
|
|
|
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "int0", "int1";
|
|
|
|
|
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
crypto: crypto@40900000 {
|
|
|
|
|
compatible = "ti,am64-sa2ul";
|
|
|
|
|
reg = <0x00 0x40900000 0x00 0x1200>;
|
|
|
|
|
power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>;
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
|
|
|
|
|
dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>,
|
|
|
|
|
<&main_pktdma 0x4003 0>;
|
|
|
|
|
dma-names = "tx", "rx1", "rx2";
|
|
|
|
|
|
|
|
|
|
rng: rng@40910000 {
|
|
|
|
|
compatible = "inside-secure,safexcel-eip76";
|
|
|
|
|
reg = <0x00 0x40910000 0x00 0x7d>;
|
|
|
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled"; /* Used by OP-TEE */
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpmc0: memory-controller@3b000000 {
|
|
|
|
|
compatible = "ti,am64-gpmc";
|
|
|
|
|
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 80 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
reg = <0x00 0x3b000000 0x00 0x400>,
|
|
|
|
|
<0x00 0x50000000 0x00 0x8000000>;
|
|
|
|
|
reg-names = "cfg", "data";
|
|
|
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
gpmc,num-cs = <3>;
|
|
|
|
|
gpmc,num-waitpins = <2>;
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
elm0: ecc@25010000 {
|
|
|
|
|
compatible = "ti,am64-elm";
|
|
|
|
|
reg = <0x00 0x25010000 0x00 0x2000>;
|
|
|
|
|
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 54 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
status = "disabled";
|
2022-10-26 11:15:55 +00:00
|
|
|
};
|
arm: dts: ti: Add Support for AM642 SoC
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
|
|
|
};
|
