2018-05-06 21:58:06 +00:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0 */
|
2014-11-06 06:39:28 +00:00
|
|
|
/*
|
|
|
|
* include/configs/gose.h
|
|
|
|
*
|
|
|
|
* Copyright (C) 2014 Renesas Electronics Corporation
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __GOSE_H
|
|
|
|
#define __GOSE_H
|
|
|
|
|
2014-11-10 05:34:07 +00:00
|
|
|
#include "rcar-gen2-common.h"
|
2014-11-06 06:39:28 +00:00
|
|
|
|
2018-04-23 18:24:10 +00:00
|
|
|
#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
|
|
|
|
#define STACK_AREA_SIZE 0x00100000
|
|
|
|
#define LOW_LEVEL_MERAM_STACK \
|
|
|
|
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
|
2014-11-06 06:39:28 +00:00
|
|
|
|
|
|
|
/* MEMORY */
|
2014-11-10 05:34:07 +00:00
|
|
|
#define RCAR_GEN2_SDRAM_BASE 0x40000000
|
2018-04-23 18:24:10 +00:00
|
|
|
#define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024)
|
|
|
|
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024)
|
2014-11-06 06:39:28 +00:00
|
|
|
|
2014-11-06 06:42:24 +00:00
|
|
|
/* SH Ether */
|
|
|
|
#define CONFIG_SH_ETHER_USE_PORT 0
|
|
|
|
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
|
|
|
|
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
|
|
|
|
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
|
|
|
|
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
|
2018-04-23 18:24:10 +00:00
|
|
|
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
|
2014-11-06 06:42:24 +00:00
|
|
|
|
2014-11-06 06:39:28 +00:00
|
|
|
/* Board Clock */
|
2014-12-02 07:52:24 +00:00
|
|
|
|
2018-04-23 18:24:10 +00:00
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
2018-11-26 23:19:03 +00:00
|
|
|
"bootm_size=0x10000000\0"
|
2018-04-23 18:24:10 +00:00
|
|
|
|
|
|
|
/* SPL support */
|
|
|
|
#define CONFIG_SPL_STACK 0xe6340000
|
|
|
|
#define CONFIG_SPL_MAX_SIZE 0x4000
|
2014-11-12 02:29:39 +00:00
|
|
|
|
2014-11-06 06:39:28 +00:00
|
|
|
#endif /* __GOSE_H */
|