mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
ARM: rmobile: Update M2-N Gose
The M2-N Gose port was broken since some time. This patch updates the M2-N Gose port to use modern frameworks, DM, DT probing, SPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
e6027e6f45
commit
49aefe300a
7 changed files with 551 additions and 187 deletions
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@ -8,3 +8,7 @@
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#include "r8a7793-gose.dts"
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#include "r8a7793-u-boot.dtsi"
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&scif0 {
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u-boot,dm-pre-reloc;
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};
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@ -42,6 +42,9 @@ config TARGET_GOSE
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bool "Gose board"
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select DM
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select DM_SERIAL
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select SUPPORT_SPL
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select USE_TINY_PRINTF
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select SPL_TINY_MEMSET
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config TARGET_KOELSCH
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bool "Koelsch board"
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@ -1,9 +1,13 @@
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#
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# board/renesas/alt/Makefile
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# board/renesas/gose/Makefile
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#
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# Copyright (C) 2014 Renesas Electronics Corporation
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#
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# SPDX-License-Identifier: GPL-2.0
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#
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obj-y := gose.o qos.o ../rcar-common/common.o
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ifdef CONFIG_SPL_BUILD
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obj-y := gose_spl.o
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else
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obj-y := gose.o qos.o
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endif
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@ -46,13 +46,7 @@ void s_init(void)
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qos_init();
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}
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#define TMU0_MSTP125 (1 << 25)
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#define SCIF0_MSTP721 (1 << 21)
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#define ETHER_MSTP813 (1 << 13)
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#define SDHI0_MSTP314 (1 << 14)
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#define SDHI1_MSTP312 (1 << 12)
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#define SDHI2_MSTP311 (1 << 11)
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#define TMU0_MSTP125 BIT(25)
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#define SD1CKCR 0xE6150078
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#define SD2CKCR 0xE615026C
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@ -60,143 +54,59 @@ void s_init(void)
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int board_early_init_f(void)
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{
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/* TMU0 */
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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/* SCIF0 */
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
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/* ETHER */
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mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
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/* SDHI */
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3,
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SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311);
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/*
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* SD0 clock is set to 97.5MHz by default.
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* Set SD1 and SD2 to the 97.5MHz as well.
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*/
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writel(SD_97500KHZ, SD1CKCR);
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writel(SD_97500KHZ, SD2CKCR);
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return 0;
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}
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#define PUPR5 0xE6060114
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#define PUPR5_ETH 0x3FFC0000
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#define PUPR5_ETH_MAGIC (1 << 27)
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#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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/* Init PFC controller */
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r8a7793_pinmux_init();
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/* ETHER Enable */
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gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
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gpio_request(GPIO_FN_ETH_RX_ER, NULL);
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gpio_request(GPIO_FN_ETH_RXD0, NULL);
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gpio_request(GPIO_FN_ETH_RXD1, NULL);
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gpio_request(GPIO_FN_ETH_LINK, NULL);
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gpio_request(GPIO_FN_ETH_REFCLK, NULL);
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gpio_request(GPIO_FN_ETH_MDIO, NULL);
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gpio_request(GPIO_FN_ETH_TXD1, NULL);
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gpio_request(GPIO_FN_ETH_TX_EN, NULL);
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gpio_request(GPIO_FN_ETH_TXD0, NULL);
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gpio_request(GPIO_FN_ETH_MDC, NULL);
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gpio_request(GPIO_FN_IRQ0, NULL);
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mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
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gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
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mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
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gpio_direction_output(GPIO_GP_5_22, 0);
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mdelay(20);
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gpio_set_value(GPIO_GP_5_22, 1);
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udelay(1);
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/* Force ethernet PHY out of reset */
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gpio_request(ETHERNET_PHY_RESET, "phy_reset");
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gpio_direction_output(ETHERNET_PHY_RESET, 0);
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mdelay(10);
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gpio_direction_output(ETHERNET_PHY_RESET, 1);
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return 0;
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}
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#define CXR24 0xEE7003C0 /* MAC address high register */
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#define CXR25 0xEE7003C8 /* MAC address low register */
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int board_eth_init(bd_t *bis)
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{
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int ret = -ENODEV;
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u32 val;
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unsigned char enetaddr[6];
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#ifdef CONFIG_SH_ETHER
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ret = sh_eth_initialize(bis);
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if (!eth_env_get_enetaddr("ethaddr", enetaddr))
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return ret;
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/* Set Mac address */
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val = enetaddr[0] << 24 | enetaddr[1] << 16 |
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enetaddr[2] << 8 | enetaddr[3];
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writel(val, CXR24);
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val = enetaddr[4] << 8 | enetaddr[5];
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writel(val, CXR25);
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#endif
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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int ret = -ENODEV;
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#ifdef CONFIG_SH_SDHI
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gpio_request(GPIO_FN_SD0_DATA0, NULL);
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gpio_request(GPIO_FN_SD0_DATA1, NULL);
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gpio_request(GPIO_FN_SD0_DATA2, NULL);
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gpio_request(GPIO_FN_SD0_DATA3, NULL);
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gpio_request(GPIO_FN_SD0_CLK, NULL);
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gpio_request(GPIO_FN_SD0_CMD, NULL);
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gpio_request(GPIO_FN_SD0_CD, NULL);
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gpio_request(GPIO_FN_SD2_DATA0, NULL);
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gpio_request(GPIO_FN_SD2_DATA1, NULL);
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gpio_request(GPIO_FN_SD2_DATA2, NULL);
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gpio_request(GPIO_FN_SD2_DATA3, NULL);
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gpio_request(GPIO_FN_SD2_CLK, NULL);
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gpio_request(GPIO_FN_SD2_CMD, NULL);
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gpio_request(GPIO_FN_SD2_CD, NULL);
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/* SDHI 0 */
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gpio_request(GPIO_GP_7_17, NULL);
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gpio_request(GPIO_GP_2_12, NULL);
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gpio_direction_output(GPIO_GP_7_17, 1); /* power on */
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gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
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SH_SDHI_QUIRK_16BIT_BUF);
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if (ret)
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return ret;
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/* SDHI 1 */
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gpio_request(GPIO_GP_7_18, NULL);
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gpio_request(GPIO_GP_2_13, NULL);
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gpio_direction_output(GPIO_GP_7_18, 1); /* power on */
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gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
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if (ret)
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return ret;
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/* SDHI 2 */
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gpio_request(GPIO_GP_7_19, NULL);
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gpio_request(GPIO_GP_2_26, NULL);
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gpio_direction_output(GPIO_GP_7_19, 1); /* power on */
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gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
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#endif
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return ret;
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}
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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if (fdtdec_setup_memory_size() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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/* KSZ8041RNLI */
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#define PHY_CONTROL1 0x1E
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#define PHY_LED_MODE 0xC0000
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#define PHY_LED_MODE_ACK 0x4000
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int board_phy_config(struct phy_device *phydev)
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{
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int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
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ret &= ~PHY_LED_MODE;
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ret |= PHY_LED_MODE_ACK;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
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return 0;
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}
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@ -207,22 +117,38 @@ const struct rmobile_sysinfo sysinfo = {
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void reset_cpu(ulong addr)
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{
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u8 val;
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struct udevice *dev;
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const u8 pmic_bus = 6;
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const u8 pmic_addr = 0x58;
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u8 data;
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int ret;
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i2c_set_bus_num(2); /* PowerIC connected to ch2 */
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i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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val |= 0x02;
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i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
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if (ret)
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hang();
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ret = dm_i2c_read(dev, 0x13, &data, 1);
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if (ret)
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hang();
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data |= BIT(1);
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ret = dm_i2c_write(dev, 0x13, &data, 1);
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if (ret)
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hang();
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}
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static const struct sh_serial_platdata serial_platdata = {
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.base = SCIF0_BASE,
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.type = PORT_SCIF,
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.clk = 14745600,
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.clk_mode = EXT_CLK,
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};
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enum env_location env_get_location(enum env_operation op, int prio)
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{
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const u32 load_magic = 0xb33fc0de;
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U_BOOT_DEVICE(gose_serials) = {
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.name = "serial_sh",
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.platdata = &serial_platdata,
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};
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/* Block environment access if loaded using JTAG */
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if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
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(op != ENVOP_INIT))
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return ENVL_UNKNOWN;
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if (prio)
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return ENVL_UNKNOWN;
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return ENVL_SPI_FLASH;
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}
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408
board/renesas/gose/gose_spl.c
Normal file
408
board/renesas/gose/gose_spl.c
Normal file
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@ -0,0 +1,408 @@
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/*
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* board/renesas/gose/gose_spl.c
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*
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <malloc.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <spl.h>
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#define TMU0_MSTP125 BIT(25)
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#define SCIF0_MSTP721 BIT(21)
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#define QSPI_MSTP917 BIT(17)
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#define SD2CKCR 0xE615026C
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#define SD_97500KHZ 0x7
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struct reg_config {
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u16 off;
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u32 val;
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};
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static void dbsc_wait(u16 reg)
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{
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static const u32 dbsc3_0_base = DBSC3_0_BASE;
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while (!(readl(dbsc3_0_base + reg) & BIT(0)))
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;
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}
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static void spl_init_sys(void)
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{
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u32 r0 = 0;
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writel(0xa5a5a500, 0xe6020004);
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writel(0xa5a5a500, 0xe6030004);
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asm volatile(
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/* ICIALLU - Invalidate I$ to PoU */
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"mcr 15, 0, %0, cr7, cr5, 0 \n"
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/* BPIALL - Invalidate branch predictors */
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"mcr 15, 0, %0, cr7, cr5, 6 \n"
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/* Set SCTLR[IZ] */
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"mrc 15, 0, %0, cr1, cr0, 0 \n"
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"orr %0, #0x1800 \n"
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"mcr 15, 0, %0, cr1, cr0, 0 \n"
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"isb sy \n"
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:"=r"(r0));
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}
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static void spl_init_pfc(void)
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{
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static const struct reg_config pfc_with_unlock[] = {
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{ 0x0090, 0x60000000 },
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{ 0x0094, 0x60000000 },
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{ 0x0098, 0x00800200 },
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{ 0x009c, 0x00000000 },
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{ 0x0020, 0x00000000 },
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{ 0x0024, 0x00000000 },
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{ 0x0028, 0x000244c8 },
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{ 0x002c, 0x00000000 },
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{ 0x0030, 0x00002400 },
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{ 0x0034, 0x01520000 },
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{ 0x0038, 0x00724003 },
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{ 0x003c, 0x00000000 },
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{ 0x0040, 0x00000000 },
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{ 0x0044, 0x00000000 },
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{ 0x0048, 0x00000000 },
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{ 0x004c, 0x00000000 },
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{ 0x0050, 0x00000000 },
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{ 0x0054, 0x00000000 },
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{ 0x0058, 0x00000000 },
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{ 0x005c, 0x00000000 },
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{ 0x0160, 0x00000000 },
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{ 0x0004, 0xffffffff },
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{ 0x0008, 0x00ec3fff },
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{ 0x000c, 0x3bc001e7 },
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{ 0x0010, 0x5bffffff },
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{ 0x0014, 0x1ffffffb },
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{ 0x0018, 0x01bffff0 },
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{ 0x001c, 0xcf7fffff },
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{ 0x0074, 0x0381fc00 },
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};
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static const struct reg_config pfc_without_unlock[] = {
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{ 0x0100, 0xffffffdf },
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{ 0x0104, 0xc883c3ff },
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{ 0x0108, 0x1201f3c9 },
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{ 0x010c, 0x00000000 },
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{ 0x0110, 0xffffeb04 },
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{ 0x0114, 0xc003ffff },
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{ 0x0118, 0x0800000f },
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{ 0x011c, 0x001800f0 },
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};
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static const u32 pfc_base = 0xe6060000;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
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writel(~pfc_with_unlock[i].val, pfc_base);
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writel(pfc_with_unlock[i].val,
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pfc_base | pfc_with_unlock[i].off);
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}
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for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
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writel(pfc_without_unlock[i].val,
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pfc_base | pfc_without_unlock[i].off);
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}
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static void spl_init_gpio(void)
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{
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static const u16 gpio_offs[] = {
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0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
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};
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static const struct reg_config gpio_set[] = {
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{ 0x2000, 0x04381000 },
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{ 0x5000, 0x00000000 },
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{ 0x5800, 0x000e0000 },
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};
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static const struct reg_config gpio_clr[] = {
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{ 0x1000, 0x00000000 },
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{ 0x2000, 0x04381010 },
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{ 0x3000, 0x00000000 },
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{ 0x4000, 0x00000000 },
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{ 0x5000, 0x00400000 },
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{ 0x5400, 0x00000000 },
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{ 0x5800, 0x000e0380 },
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};
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static const u32 gpio_base = 0xe6050000;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
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writel(0, gpio_base | 0x20 | gpio_offs[i]);
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for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
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writel(0, gpio_base | 0x00 | gpio_offs[i]);
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for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
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writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
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|
||||
for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
|
||||
writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
|
||||
}
|
||||
|
||||
static void spl_init_lbsc(void)
|
||||
{
|
||||
static const struct reg_config lbsc_config[] = {
|
||||
{ 0x00, 0x00000020 },
|
||||
{ 0x08, 0x00002020 },
|
||||
{ 0x30, 0x2a103320 },
|
||||
{ 0x38, 0xff70ff70 },
|
||||
};
|
||||
|
||||
static const u16 lbsc_offs[] = {
|
||||
0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
|
||||
};
|
||||
|
||||
static const u32 lbsc_base = 0xfec00200;
|
||||
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
|
||||
writel(lbsc_config[i].val,
|
||||
lbsc_base | lbsc_config[i].off);
|
||||
writel(lbsc_config[i].val,
|
||||
lbsc_base | (lbsc_config[i].off + 4));
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
|
||||
writel(0, lbsc_base | lbsc_offs[i]);
|
||||
}
|
||||
|
||||
static void spl_init_dbsc(void)
|
||||
{
|
||||
static const struct reg_config dbsc_config1[] = {
|
||||
{ 0x0280, 0x0000a55a },
|
||||
{ 0x0018, 0x21000000 },
|
||||
{ 0x0018, 0x11000000 },
|
||||
{ 0x0018, 0x10000000 },
|
||||
{ 0x0290, 0x00000001 },
|
||||
{ 0x02a0, 0x80000000 },
|
||||
{ 0x0290, 0x00000004 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config2[] = {
|
||||
{ 0x0290, 0x00000006 },
|
||||
{ 0x02a0, 0x0001c000 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config4[] = {
|
||||
{ 0x0290, 0x00000010 },
|
||||
{ 0x02a0, 0xf00464db },
|
||||
{ 0x0290, 0x00000061 },
|
||||
{ 0x02a0, 0x0000006d },
|
||||
{ 0x0290, 0x00000001 },
|
||||
{ 0x02a0, 0x00000073 },
|
||||
{ 0x0020, 0x00000007 },
|
||||
{ 0x0024, 0x0f030a02 },
|
||||
{ 0x0030, 0x00000001 },
|
||||
{ 0x00b0, 0x00000000 },
|
||||
{ 0x0040, 0x0000000b },
|
||||
{ 0x0044, 0x00000008 },
|
||||
{ 0x0048, 0x00000000 },
|
||||
{ 0x0050, 0x0000000b },
|
||||
{ 0x0054, 0x000c000b },
|
||||
{ 0x0058, 0x00000027 },
|
||||
{ 0x005c, 0x0000001c },
|
||||
{ 0x0060, 0x00000006 },
|
||||
{ 0x0064, 0x00000020 },
|
||||
{ 0x0068, 0x00000008 },
|
||||
{ 0x006c, 0x0000000c },
|
||||
{ 0x0070, 0x00000009 },
|
||||
{ 0x0074, 0x00000012 },
|
||||
{ 0x0078, 0x000000d0 },
|
||||
{ 0x007c, 0x00140005 },
|
||||
{ 0x0080, 0x00050004 },
|
||||
{ 0x0084, 0x70233005 },
|
||||
{ 0x0088, 0x000c0000 },
|
||||
{ 0x008c, 0x00000200 },
|
||||
{ 0x0090, 0x00000040 },
|
||||
{ 0x0100, 0x00000001 },
|
||||
{ 0x00c0, 0x00020001 },
|
||||
{ 0x00c8, 0x20042004 },
|
||||
{ 0x0380, 0x00020002 },
|
||||
{ 0x0390, 0x0000001f },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config5[] = {
|
||||
{ 0x0244, 0x00000011 },
|
||||
{ 0x0290, 0x00000003 },
|
||||
{ 0x02a0, 0x0300c561 },
|
||||
{ 0x0290, 0x00000023 },
|
||||
{ 0x02a0, 0x00fcdb60 },
|
||||
{ 0x0290, 0x00000011 },
|
||||
{ 0x02a0, 0x1000040b },
|
||||
{ 0x0290, 0x00000012 },
|
||||
{ 0x02a0, 0x9d9cbb66 },
|
||||
{ 0x0290, 0x00000013 },
|
||||
{ 0x02a0, 0x1a868400 },
|
||||
{ 0x0290, 0x00000014 },
|
||||
{ 0x02a0, 0x300214d8 },
|
||||
{ 0x0290, 0x00000015 },
|
||||
{ 0x02a0, 0x00000d70 },
|
||||
{ 0x0290, 0x00000016 },
|
||||
{ 0x02a0, 0x00000006 },
|
||||
{ 0x0290, 0x00000017 },
|
||||
{ 0x02a0, 0x00000018 },
|
||||
{ 0x0290, 0x0000001a },
|
||||
{ 0x02a0, 0x910035c7 },
|
||||
{ 0x0290, 0x00000004 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config6[] = {
|
||||
{ 0x0290, 0x00000001 },
|
||||
{ 0x02a0, 0x00000181 },
|
||||
{ 0x0018, 0x11000000 },
|
||||
{ 0x0290, 0x00000004 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config7[] = {
|
||||
{ 0x0290, 0x00000001 },
|
||||
{ 0x02a0, 0x0000fe01 },
|
||||
{ 0x0304, 0x00000000 },
|
||||
{ 0x00f4, 0x01004c20 },
|
||||
{ 0x00f8, 0x014000aa },
|
||||
{ 0x00e0, 0x00000140 },
|
||||
{ 0x00e4, 0x00081860 },
|
||||
{ 0x00e8, 0x00010000 },
|
||||
{ 0x0290, 0x00000004 },
|
||||
};
|
||||
|
||||
static const struct reg_config dbsc_config8[] = {
|
||||
{ 0x0014, 0x00000001 },
|
||||
{ 0x0010, 0x00000001 },
|
||||
{ 0x0280, 0x00000000 },
|
||||
};
|
||||
|
||||
static const u32 dbsc3_0_base = DBSC3_0_BASE;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
|
||||
writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
|
||||
|
||||
dbsc_wait(0x2a0);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
|
||||
writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
|
||||
writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
|
||||
|
||||
dbsc_wait(0x240);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
|
||||
writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
|
||||
|
||||
dbsc_wait(0x2a0);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
|
||||
writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
|
||||
|
||||
dbsc_wait(0x2a0);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
|
||||
writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
|
||||
|
||||
dbsc_wait(0x2a0);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
|
||||
writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
|
||||
|
||||
}
|
||||
|
||||
static void spl_init_qspi(void)
|
||||
{
|
||||
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
|
||||
|
||||
static const u32 qspi_base = 0xe6b10000;
|
||||
|
||||
writeb(0x08, qspi_base + 0x00);
|
||||
writeb(0x00, qspi_base + 0x01);
|
||||
writeb(0x06, qspi_base + 0x02);
|
||||
writeb(0x01, qspi_base + 0x0a);
|
||||
writeb(0x00, qspi_base + 0x0b);
|
||||
writeb(0x00, qspi_base + 0x0c);
|
||||
writeb(0x00, qspi_base + 0x0d);
|
||||
writeb(0x00, qspi_base + 0x0e);
|
||||
|
||||
writew(0xe080, qspi_base + 0x10);
|
||||
|
||||
writeb(0xc0, qspi_base + 0x18);
|
||||
writeb(0x00, qspi_base + 0x18);
|
||||
writeb(0x00, qspi_base + 0x08);
|
||||
writeb(0x48, qspi_base + 0x00);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
|
||||
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
|
||||
|
||||
/*
|
||||
* SD0 clock is set to 97.5MHz by default.
|
||||
* Set SD2 to the 97.5MHz as well.
|
||||
*/
|
||||
writel(SD_97500KHZ, SD2CKCR);
|
||||
|
||||
spl_init_sys();
|
||||
spl_init_pfc();
|
||||
spl_init_gpio();
|
||||
spl_init_lbsc();
|
||||
spl_init_dbsc();
|
||||
spl_init_qspi();
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
}
|
||||
|
||||
void board_boot_order(u32 *spl_boot_list)
|
||||
{
|
||||
const u32 jtag_magic = 0x1337c0de;
|
||||
const u32 load_magic = 0xb33fc0de;
|
||||
|
||||
/*
|
||||
* If JTAG probe sets special word at 0xe6300020, then it must
|
||||
* put U-Boot into RAM and SPL will start it from RAM.
|
||||
*/
|
||||
if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
|
||||
printf("JTAG boot detected!\n");
|
||||
|
||||
while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
|
||||
;
|
||||
|
||||
spl_boot_list[0] = BOOT_DEVICE_RAM;
|
||||
spl_boot_list[1] = BOOT_DEVICE_NONE;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* Boot from SPI NOR with YMODEM UART fallback. */
|
||||
spl_boot_list[0] = BOOT_DEVICE_SPI;
|
||||
spl_boot_list[1] = BOOT_DEVICE_UART;
|
||||
spl_boot_list[2] = BOOT_DEVICE_NONE;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
||||
|
|
@ -1,17 +1,37 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
|
||||
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
|
||||
# CONFIG_SPL_USE_ARCH_MEMSET is not set
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_TEXT_BASE=0xE6304000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_SYS_TEXT_BASE=0x50000000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_R8A7793=y
|
||||
CONFIG_TARGET_GOSE=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7793-gose-u-boot"
|
||||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
|
|
@ -19,21 +39,42 @@ CONFIG_CMD_USB=y
|
|||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_RENESAS=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_IIC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_RENESAS_SDHI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_SH_ETHER=y
|
||||
CONFIG_BAUDRATE=38400
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_PCI_RCAR_GEN2=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_PFC=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_SH_QSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_PCI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
|
|
|
|||
|
|
@ -14,21 +14,15 @@
|
|||
|
||||
#include "rcar-gen2-common.h"
|
||||
|
||||
/* STACK */
|
||||
#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
|
||||
#endif
|
||||
|
||||
#define STACK_AREA_SIZE 0xC000
|
||||
#define LOW_LEVEL_MERAM_STACK \
|
||||
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
|
||||
#define STACK_AREA_SIZE 0x00100000
|
||||
#define LOW_LEVEL_MERAM_STACK \
|
||||
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
|
||||
|
||||
/* MEMORY */
|
||||
#define RCAR_GEN2_SDRAM_BASE 0x40000000
|
||||
#define RCAR_GEN2_SDRAM_SIZE 0x40000000
|
||||
#define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000
|
||||
#define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024)
|
||||
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024)
|
||||
|
||||
/* SCIF */
|
||||
|
||||
|
|
@ -41,45 +35,29 @@
|
|||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
|
||||
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
|
||||
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
|
||||
|
||||
/* Board Clock */
|
||||
#define RMOBILE_XTAL_CLK 20000000u
|
||||
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
|
||||
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
|
||||
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SH
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
|
||||
#define CONFIG_SYS_I2C_SH_SPEED0 400000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED1 400000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED2 400000
|
||||
#define CONFIG_SH_I2C_DATA_HIGH 4
|
||||
#define CONFIG_SH_I2C_DATA_LOW 5
|
||||
#define CONFIG_SH_I2C_CLOCK 10000000
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0"
|
||||
|
||||
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_EHCI_RMOBILE
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
|
||||
/* Module stop status bits */
|
||||
/* INTC-RT */
|
||||
#define CONFIG_SMSTP0_ENA 0x00400000
|
||||
/* MSIF */
|
||||
#define CONFIG_SMSTP2_ENA 0x00002000
|
||||
/* INTC-SYS, IRQC */
|
||||
#define CONFIG_SMSTP4_ENA 0x00000180
|
||||
/* SCIF0 */
|
||||
#define CONFIG_SMSTP7_ENA 0x00200000
|
||||
|
||||
/* SDHI */
|
||||
#define CONFIG_SH_SDHI_FREQ 97500000
|
||||
/* SPL support */
|
||||
#define CONFIG_SPL_TEXT_BASE 0xe6300000
|
||||
#define CONFIG_SPL_STACK 0xe6340000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x4000
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_CONS_SCIF0
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ 65000000
|
||||
#endif
|
||||
|
||||
#endif /* __GOSE_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue