mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-14 07:13:03 +00:00
267 lines
4.3 KiB
Text
267 lines
4.3 KiB
Text
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 NXP
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* Copyright 2023 Variscite Ltd.
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*/
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#include "imx93-u-boot.dtsi"
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog3>;
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bootph-pre-ram;
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bootph-some-ram;
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};
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aliases {
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ethernet0 = &eqos;
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ethernet1 = &fec;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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&{/soc@0} {
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bootph-all;
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bootph-pre-ram;
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};
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&aips1 {
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bootph-pre-ram;
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bootph-all;
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};
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&aips2 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&aips3 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&iomuxc {
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bootph-pre-ram;
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bootph-some-ram;
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};
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®_usdhc2_vmmc {
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u-boot,off-on-delay-us = <20000>;
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl_reg_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_uart1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&gpio1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&gpio3 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&lpuart1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&usdhc1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&usdhc2 {
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bootph-pre-ram;
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bootph-some-ram;
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fsl,signal-voltage-switch-extra-delay-ms = <8>;
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};
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ðphy0 {
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reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
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reset-assert-us = <15000>;
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reset-deassert-us = <100000>;
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};
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ðphy1 {
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reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
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reset-assert-us = <15000>;
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reset-deassert-us = <100000>;
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};
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&s4muap {
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bootph-pre-ram;
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bootph-some-ram;
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status = "okay";
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};
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&clk {
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bootph-all;
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bootph-pre-ram;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-rates;
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};
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&osc_32k {
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bootph-all;
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bootph-pre-ram;
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};
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&osc_24m {
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bootph-all;
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bootph-pre-ram;
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};
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&clk_ext1 {
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bootph-all;
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bootph-pre-ram;
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};
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/*
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* The two nodes below won't be needed once nxp,pca9451a
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* support is added to the Linux kernel.
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*/
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&iomuxc {
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pinctrl_lpi2c3: lpi2c3grp {
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bootph-pre-ram;
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fsl,pins = <
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MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
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MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
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>;
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};
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};
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&lpi2c3 {
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bootph-pre-ram;
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bootph-some-ram;
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpi2c3>;
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pinctrl-1 = <&pinctrl_lpi2c3>;
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status = "okay";
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pmic@25 {
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bootph-pre-ram;
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bootph-some-ram;
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compatible = "nxp,pca9451a";
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reg = <0x25>;
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pinctrl-names = "default";
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regulators {
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bootph-pre-ram;
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buck1: BUCK1 {
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regulator-name = "BUCK1";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck2: BUCK2 {
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regulator-name = "BUCK2";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck4: BUCK4{
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regulator-name = "BUCK4";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5: BUCK5{
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regulator-name = "BUCK5";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6: BUCK6 {
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regulator-name = "BUCK6";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1: LDO1 {
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regulator-name = "LDO1";
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2: LDO2 {
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regulator-name = "LDO2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1150000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3: LDO3 {
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regulator-name = "LDO3";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4: LDO4 {
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regulator-name = "LDO4";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5: LDO5 {
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regulator-name = "LDO5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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