// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2022 NXP * Copyright 2023 Variscite Ltd. */ #include "imx93-u-boot.dtsi" / { wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog3>; bootph-pre-ram; bootph-some-ram; }; aliases { ethernet0 = &eqos; ethernet1 = &fec; }; firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; }; }; }; &{/soc@0} { bootph-all; bootph-pre-ram; }; &aips1 { bootph-pre-ram; bootph-all; }; &aips2 { bootph-pre-ram; bootph-some-ram; }; &aips3 { bootph-pre-ram; bootph-some-ram; }; &iomuxc { bootph-pre-ram; bootph-some-ram; }; ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; bootph-pre-ram; bootph-some-ram; }; &pinctrl_reg_usdhc2_vmmc { bootph-pre-ram; }; &pinctrl_uart1 { bootph-pre-ram; bootph-some-ram; }; &pinctrl_usdhc2 { bootph-pre-ram; bootph-some-ram; }; &gpio1 { bootph-pre-ram; bootph-some-ram; }; &gpio2 { bootph-pre-ram; bootph-some-ram; }; &gpio3 { bootph-pre-ram; bootph-some-ram; }; &gpio4 { bootph-pre-ram; bootph-some-ram; }; &lpuart1 { bootph-pre-ram; bootph-some-ram; }; &usdhc1 { bootph-pre-ram; bootph-some-ram; }; &usdhc2 { bootph-pre-ram; bootph-some-ram; fsl,signal-voltage-switch-extra-delay-ms = <8>; }; ðphy0 { reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; reset-assert-us = <15000>; reset-deassert-us = <100000>; }; ðphy1 { reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; reset-assert-us = <15000>; reset-deassert-us = <100000>; }; &s4muap { bootph-pre-ram; bootph-some-ram; status = "okay"; }; &clk { bootph-all; bootph-pre-ram; /delete-property/ assigned-clocks; /delete-property/ assigned-clock-rates; }; &osc_32k { bootph-all; bootph-pre-ram; }; &osc_24m { bootph-all; bootph-pre-ram; }; &clk_ext1 { bootph-all; bootph-pre-ram; }; /* * The two nodes below won't be needed once nxp,pca9451a * support is added to the Linux kernel. */ &iomuxc { pinctrl_lpi2c3: lpi2c3grp { bootph-pre-ram; fsl,pins = < MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e >; }; }; &lpi2c3 { bootph-pre-ram; bootph-some-ram; clock-frequency = <400000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_lpi2c3>; pinctrl-1 = <&pinctrl_lpi2c3>; status = "okay"; pmic@25 { bootph-pre-ram; bootph-some-ram; compatible = "nxp,pca9451a"; reg = <0x25>; pinctrl-names = "default"; regulators { bootph-pre-ram; buck1: BUCK1 { regulator-name = "BUCK1"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; }; buck2: BUCK2 { regulator-name = "BUCK2"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; }; buck4: BUCK4{ regulator-name = "BUCK4"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; buck5: BUCK5{ regulator-name = "BUCK5"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; buck6: BUCK6 { regulator-name = "BUCK6"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; ldo1: LDO1 { regulator-name = "LDO1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo2: LDO2 { regulator-name = "LDO2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; ldo3: LDO3 { regulator-name = "LDO3"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo4: LDO4 { regulator-name = "LDO4"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo5: LDO5 { regulator-name = "LDO5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; }; }; };