Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-08 14:14:32 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/arch/powerpc/cpu/mpc83xx/cpu_init.c

447 lines
12 KiB
C
Raw Normal View History

SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
/*
mpc83xx: USB: Reorganized its support The following patch reorganizes/reworks the USB support for mpc83xx as under:- * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to cpu/mpx83xx/cpu_init.c * Board specific usb_phy_type is read from the environment * Adds USB EHCI specific structure in include/usb/ehci-fsl.h * Copyrights revamped in most of the following files Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-05-25 11:53:16 +00:00
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
*/
#include <common.h>
common: Drop asm_offsets.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:07 +00:00
#include <asm-offsets.h>
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
#include <mpc83xx.h>
#include <ioports.h>
mpc83xx: USB: Reorganized its support The following patch reorganizes/reworks the USB support for mpc83xx as under:- * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to cpu/mpx83xx/cpu_init.c * Board specific usb_phy_type is read from the environment * Adds USB EHCI specific structure in include/usb/ehci-fsl.h * Copyrights revamped in most of the following files Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-05-25 11:53:16 +00:00
#include <asm/io.h>
board_f: powerpc: Move prt_83xx_rsr() to private code This function is called just before checkcpu() on MPX83xx. Move it to the code for that arch. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:27:27 +00:00
#include <asm/processor.h>
mpc83xx: remove unneeded extern declaration in cpu_init remove extern void qe_init(uint qe_base); extern void qe_reset(void); and include fsl_qe.h instead. Signed-off-by: Heiko Schocher <hs@denx.de> Series-changes: 2 - new in v2
2020-04-15 08:35:40 +00:00
#include <fsl_qe.h>
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_USB_EHCI_FSL
usb: Rename ehci-fsl.h to ehci-ci.h Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors. This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
2016-03-31 21:12:23 +00:00
#include <usb/ehci-ci.h>
mpc83xx: USB: Reorganized its support The following patch reorganizes/reworks the USB support for mpc83xx as under:- * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to cpu/mpx83xx/cpu_init.c * Board specific usb_phy_type is read from the environment * Adds USB EHCI specific structure in include/usb/ehci-fsl.h * Copyrights revamped in most of the following files Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-05-25 11:53:16 +00:00
#endif
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:11 +00:00
#include <linux/delay.h>
powerpc, qe: add DTS support for parallel I/O ports add DM support for parallel I/O ports on QUICC Engine Block Signed-off-by: Heiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Series-changes: 2 - remove RFC - fixed Codingstyle errors, therefore new patch powerpc, mpc83xx: fix codingstyle issues for qe_io.c - moved DM part to drivers/pinctrl Commit-notes: Open questions / discussion: - I let the old none DM based implementation in code so boards should work with old implementation. This should be removed if all boards are converted to DM/DTS. - Unfortunately linux DTS does not use "pinctrl-" properties, instead "pio-handle" properties. Even worser old U-Boot code initializes all pins defined in "const qe_iop_conf_t qe_iop_conf_tab[]" table in board code. As linux does the same I decided to also scan through all subnodes containing "pio-map" property and initialize them too. The proper solution would be to check for "pio-handle" when a device is probed. END
2020-02-03 09:23:53 +00:00
#ifdef CONFIG_QE
#include <fsl_qe.h>
#endif
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
mpc83xx: Migrate LBLAW_* to Kconfig The LBLAW_* values determine the window configuration of the memory controller. Hence, they must be known at compile time, and cannot be implemented in the DT mechanism. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-01-21 08:17:58 +00:00
#include "lblaw/lblaw.h"
mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to Kconfig Migrate the BR/OR settings to Kconfig. These must be known at compile time, so cannot be configured via DT. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-01-21 08:18:03 +00:00
#include "elbc/elbc.h"
mpc8308: Migrate system io config to Kconfig Migrate the system IO configuration setting to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-01-21 08:18:11 +00:00
#include "sysio/sysio.h"
mpc83xx: Migrate arbiter config to Kconfig Migrate the arbiter configuration to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-01-21 08:18:12 +00:00
#include "arbiter/arbiter.h"
mpc83xx: Migrate SPCR to Kconfig Migrate the SPCR setting to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-01-21 08:18:13 +00:00
#include "initreg/initreg.h"
mpc83xx: Migrate LBLAW_* to Kconfig The LBLAW_* values determine the window configuration of the memory controller. Hence, they must be known at compile time, and cannot be implemented in the DT mechanism. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-01-21 08:17:58 +00:00
GCC-4.x fixes: clean up global data pointer initialization for all boards.
2006-03-31 16:32:53 +00:00
DECLARE_GLOBAL_DATA_PTR;
mpc83xx: add QE ethernet support this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
2006-11-03 18:11:15 +00:00
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
int open_drain, int assign);
powerpc, qe: add DTS support for parallel I/O ports add DM support for parallel I/O ports on QUICC Engine Block Signed-off-by: Heiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Series-changes: 2 - remove RFC - fixed Codingstyle errors, therefore new patch powerpc, mpc83xx: fix codingstyle issues for qe_io.c - moved DM part to drivers/pinctrl Commit-notes: Open questions / discussion: - I let the old none DM based implementation in code so boards should work with old implementation. This should be removed if all boards are converted to DM/DTS. - Unfortunately linux DTS does not use "pinctrl-" properties, instead "pio-handle" properties. Even worser old U-Boot code initializes all pins defined in "const qe_iop_conf_t qe_iop_conf_tab[]" table in board code. As linux does the same I decided to also scan through all subnodes containing "pio-map" property and initialize them too. The proper solution would be to check for "pio-handle" when a device is probed. END
2020-02-03 09:23:53 +00:00
#if !defined(CONFIG_PINCTRL)
mpc83xx: add QE ethernet support this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
2006-11-03 18:11:15 +00:00
static void config_qe_ioports(void)
{
u8 port, pin;
int dir, open_drain, assign;
int i;
for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
port = qe_iop_conf_tab[i].port;
pin = qe_iop_conf_tab[i].pin;
dir = qe_iop_conf_tab[i].dir;
open_drain = qe_iop_conf_tab[i].open_drain;
assign = qe_iop_conf_tab[i].assign;
qe_config_iopin(port, pin, dir, open_drain, assign);
}
}
#endif
powerpc, qe: add DTS support for parallel I/O ports add DM support for parallel I/O ports on QUICC Engine Block Signed-off-by: Heiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Series-changes: 2 - remove RFC - fixed Codingstyle errors, therefore new patch powerpc, mpc83xx: fix codingstyle issues for qe_io.c - moved DM part to drivers/pinctrl Commit-notes: Open questions / discussion: - I let the old none DM based implementation in code so boards should work with old implementation. This should be removed if all boards are converted to DM/DTS. - Unfortunately linux DTS does not use "pinctrl-" properties, instead "pio-handle" properties. Even worser old U-Boot code initializes all pins defined in "const qe_iop_conf_t qe_iop_conf_tab[]" table in board code. As linux does the same I decided to also scan through all subnodes containing "pio-map" property and initialize them too. The proper solution would be to check for "pio-handle" when a device is probed. END
2020-02-03 09:23:53 +00:00
#endif
mpc83xx: add QE ethernet support this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
2006-11-03 18:11:15 +00:00
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
/*
* Breathe some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f (volatile immap_t * im)
{
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
__be32 sccr_mask =
#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-19 22:06:46 +00:00
SCCR_ENCCM |
mpc83xx: add support for more system clock performance controls System registers that are modified are the Arbiter Configuration Register (ACR), the System Priority Control Register (SPCR), and the System Clock Configuration Register (SCCR). Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com> Signed-off by: Joe D'Abbraccio <ljd015@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-16 18:06:16 +00:00
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-19 22:06:46 +00:00
SCCR_PCICM |
mpc83xx: add support for more system clock performance controls System registers that are modified are the Arbiter Configuration Register (ACR), the System Priority Control Register (SPCR), and the System Clock Configuration Register (SCCR). Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com> Signed-off by: Joe D'Abbraccio <ljd015@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-16 18:06:16 +00:00
#endif
mpc83xx: add support for setting PCIE clocks This patch adds support for setting PCIE clocks in cpu_init.c by providing CONFIG_SYS_SCCR_PCIEXP{1,2} in configuration. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-09-17 21:41:47 +00:00
#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
SCCR_PCIEXP1CM |
#endif
#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
SCCR_PCIEXP2CM |
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-19 22:06:46 +00:00
SCCR_TSECCM |
mpc83xx: Add support for the MPC8349E-mITX PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi <timur@freescale.com>
2006-11-01 00:44:42 +00:00
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-19 22:06:46 +00:00
SCCR_TSEC1CM |
mpc83xx: Add support for the MPC8349E-mITX PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi <timur@freescale.com>
2006-11-01 00:44:42 +00:00
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-19 22:06:46 +00:00
SCCR_TSEC2CM |
mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-02-28 05:51:42 +00:00
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-19 22:06:46 +00:00
SCCR_TSEC1ON |
Update SCCR programming in cpu_init_f() to support all 83xx processors Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the bitfields for all 83xx processors. The code to update some bitfields was compiled only on some processors. Now, the bitfields are programmed as long as the corresponding CFG_SCCR option is defined in the board header file. This means that the board header file should not define any CFG_SCCR macros for bitfields that don't exist on that processor, otherwise the SCCR will be programmed incorrectly. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-07-03 18:04:34 +00:00
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-19 22:06:46 +00:00
SCCR_TSEC2ON |
Update SCCR programming in cpu_init_f() to support all 83xx processors Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the bitfields for all 83xx processors. The code to update some bitfields was compiled only on some processors. Now, the bitfields are programmed as long as the corresponding CFG_SCCR option is defined in the board header file. This means that the board header file should not define any CFG_SCCR macros for bitfields that don't exist on that processor, otherwise the SCCR will be programmed incorrectly. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-07-03 18:04:34 +00:00
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-19 22:06:46 +00:00
SCCR_USBMPHCM |
mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-02-28 05:51:42 +00:00
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-19 22:06:46 +00:00
SCCR_USBDRCM |
mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-02-28 05:51:42 +00:00
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-19 22:06:46 +00:00
SCCR_SATACM |
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#endif
0;
__be32 sccr_val =
#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
(CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
mpc83xx: Add support for the MPC8349E-mITX PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi <timur@freescale.com>
2006-11-01 00:44:42 +00:00
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
(CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
#endif
mpc83xx: add support for setting PCIE clocks This patch adds support for setting PCIE clocks in cpu_init.c by providing CONFIG_SYS_SCCR_PCIEXP{1,2} in configuration. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-09-17 21:41:47 +00:00
#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
(CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
(CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
(CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
(CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
(CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
(CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
(CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
(CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
#endif
0;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
powerpc: mpc83xx: Enable pre-relocation malloc To enable DM on MPC83xx, we need pre-relocation malloc, which is implemented in this patch. Signed-off-by: Mario Six <mario.six@gdsys.cc> [York S: Fixed compiling warning for unused variable 'i'] Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-17 07:33:48 +00:00
/* global data region was cleared in start.S */
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
/* system performance tweaking */
clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
mpc83xx: Add support for the MPC8349E-mITX PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi <timur@freescale.com>
2006-11-01 00:44:42 +00:00
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
/* RSR - Reset Status Register - clear all status (4.6.1.3) */
ppc: Move reset_status to arch_global_data Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:56 +00:00
gd->arch.reset_status = __raw_readl(&im->reset.rsr);
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
__raw_writel(~(RSR_RES), &im->reset.rsr);
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
mpc83xx: Store and display Arbiter Event Register values Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-28 21:09:19 +00:00
/* AER - Arbiter Event Register - store status */
ppc: Move arbiter fields to arch_global_data Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:57 +00:00
gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
mpc83xx: Store and display Arbiter Event Register values Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-28 21:09:19 +00:00
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
/*
* RMR - Reset Mode Register
* contains checkstop reset enable (4.6.1.4)
*/
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
__raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
mpc83xx: boot time regression, move LCRR setup back to cpu_init_f Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields) moved the LCRR assignment to after relocation to RAM because of the potential problem with changing the local bus clock while executing from flash. This change unfortunately adversely affects the boot time, as running all code up to cpu_init_r can cause significant slowdown. E.G. on a 8347 board a bootup time increase of ~600ms has been observed: 0.020 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz 0.168 RS: 232 0.172 I2C: ready 0.176 DRAM: 64 MB 1.236 FLASH: 32 MB Versus: 0.016 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz 0.092 RS: 232 0.092 I2C: ready 0.096 DRAM: 64 MB 0.644 FLASH: 32 MB So far no boards have needed the late LCRR setup, so simply revert it for now - If it is needed at a later time, those boards can either do their own final LCRR setup in board code (E.G. in board_early_init_r), or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do the setup in cpu_init_r. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-12-08 21:20:34 +00:00
/* LCRR - Clock Ratio Register (10.3.1.16)
* write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
*/
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-06-17 16:37:20 +00:00
clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
__raw_readl(&im->im_lbc.lcrr);
mpc83xx: boot time regression, move LCRR setup back to cpu_init_f Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields) moved the LCRR assignment to after relocation to RAM because of the potential problem with changing the local bus clock while executing from flash. This change unfortunately adversely affects the boot time, as running all code up to cpu_init_r can cause significant slowdown. E.G. on a 8347 board a bootup time increase of ~600ms has been observed: 0.020 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz 0.168 RS: 232 0.172 I2C: ready 0.176 DRAM: 64 MB 1.236 FLASH: 32 MB Versus: 0.016 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz 0.092 RS: 232 0.092 I2C: ready 0.096 DRAM: 64 MB 0.644 FLASH: 32 MB So far no boards have needed the late LCRR setup, so simply revert it for now - If it is needed at a later time, those boards can either do their own final LCRR setup in board code (E.G. in board_early_init_r), or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do the setup in cpu_init_r. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-12-08 21:20:34 +00:00
isync();
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
/* Enable Time Base & Decrementer ( so we will have udelay() )*/
setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
/* System General Purpose Register */
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
#ifdef CONFIG_SYS_SICRH
mpc83xx: Introduce ARCH_MPC834* Replace CONFIG_MPC834* with proper CONFIG_ARCH_MPC834* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-01-21 08:17:27 +00:00
#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
fix system config overwrite @ MPC834x and MPC8313 During 83xx setup the "System I/O configuration register high" gets overwritten with user defined value if CFG_SICRH is defined. Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH must keep their reset value regardless of configuration. On my board (using RGMII) those bits are set after reset - yet it's unclear where they come from. The patch keeps both bits on MPC834x and MPC8313. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-06-23 09:40:56 +00:00
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
&im->sysconf.sicrh);
fix system config overwrite @ MPC834x and MPC8313 During 83xx setup the "System I/O configuration register high" gets overwritten with user defined value if CFG_SICRH is defined. Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH must keep their reset value regardless of configuration. On my board (using RGMII) those bits are set after reset - yet it's unclear where they come from. The patch keeps both bits on MPC834x and MPC8313. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-06-23 09:40:56 +00:00
#else
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
__raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
Make System IO Config Registers board configurable on MPC83xx Patch by Kumar Gala, 11 Jan 2006
2006-01-11 17:12:57 +00:00
#endif
fix system config overwrite @ MPC834x and MPC8313 During 83xx setup the "System I/O configuration register high" gets overwritten with user defined value if CFG_SICRH is defined. Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH must keep their reset value regardless of configuration. On my board (using RGMII) those bits are set after reset - yet it's unclear where they come from. The patch keeps both bits on MPC834x and MPC8313. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-06-23 09:40:56 +00:00
#endif
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
#ifdef CONFIG_SYS_SICRL
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
Make System IO Config Registers board configurable on MPC83xx Patch by Kumar Gala, 11 Jan 2006
2006-01-11 17:12:57 +00:00
#endif
mpc83xx: add support for mpc8309 This processor, though very similar to other members of the PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides yet another feature set than any supported sibling. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-10 22:13:08 +00:00
#ifdef CONFIG_SYS_GPR1
__raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
mpc83xx: Add support for the MPC832XEMDS board This patch supports DUART, ETH3/4 and PCI etc. Signed-off-by: Dave Liu <daveliu@freescale.com>
2006-12-07 13:13:15 +00:00
#endif
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
mpc83xx: Add the support of MPC837xEMDS board The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-09-18 04:37:57 +00:00
#endif
mpc83xx: Add support for the MPC832XEMDS board This patch supports DUART, ETH3/4 and PCI etc. Signed-off-by: Dave Liu <daveliu@freescale.com>
2006-12-07 13:13:15 +00:00
powerpc, qe: add DTS support for parallel I/O ports add DM support for parallel I/O ports on QUICC Engine Block Signed-off-by: Heiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Series-changes: 2 - remove RFC - fixed Codingstyle errors, therefore new patch powerpc, mpc83xx: fix codingstyle issues for qe_io.c - moved DM part to drivers/pinctrl Commit-notes: Open questions / discussion: - I let the old none DM based implementation in code so boards should work with old implementation. This should be removed if all boards are converted to DM/DTS. - Unfortunately linux DTS does not use "pinctrl-" properties, instead "pio-handle" properties. Even worser old U-Boot code initializes all pins defined in "const qe_iop_conf_t qe_iop_conf_tab[]" table in board code. As linux does the same I decided to also scan through all subnodes containing "pio-map" property and initialize them too. The proper solution would be to check for "pio-handle" when a device is probed. END
2020-02-03 09:23:53 +00:00
#if !defined(CONFIG_PINCTRL)
mpc83xx: add QE ethernet support this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
2006-11-03 18:11:15 +00:00
#ifdef CONFIG_QE
/* Config QE ioports */
config_qe_ioports();
#endif
powerpc, qe: add DTS support for parallel I/O ports add DM support for parallel I/O ports on QUICC Engine Block Signed-off-by: Heiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Series-changes: 2 - remove RFC - fixed Codingstyle errors, therefore new patch powerpc, mpc83xx: fix codingstyle issues for qe_io.c - moved DM part to drivers/pinctrl Commit-notes: Open questions / discussion: - I let the old none DM based implementation in code so boards should work with old implementation. This should be removed if all boards are converted to DM/DTS. - Unfortunately linux DTS does not use "pinctrl-" properties, instead "pio-handle" properties. Even worser old U-Boot code initializes all pins defined in "const qe_iop_conf_t qe_iop_conf_tab[]" table in board code. As linux does the same I decided to also scan through all subnodes containing "pio-map" property and initialize them too. The proper solution would be to check for "pio-handle" when a device is probed. END
2020-02-03 09:23:53 +00:00
#endif
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-06-17 16:37:20 +00:00
/* Set up preliminary BR/OR regs */
init_early_memctl_regs();
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-06-17 16:37:20 +00:00
/* Local Access window setup */
#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
#else
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-06-17 16:37:20 +00:00
#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
#endif
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
#endif
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
#endif
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
#endif
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
#endif
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
#endif
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
#endif
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
#endif
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
#ifdef CONFIG_SYS_GPIO1_PRELIM
im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
Allow config of GPIO direction & data registers at boot on 83xx Patch by Kumar Gala, 11 Jan 2006
2006-01-11 17:21:14 +00:00
#endif
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
#ifdef CONFIG_SYS_GPIO2_PRELIM
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
Allow config of GPIO direction & data registers at boot on 83xx Patch by Kumar Gala, 11 Jan 2006
2006-01-11 17:21:14 +00:00
#endif
mpc83xx: Introduce ARCH_MPC831* Replace CONFIG_MPC833* with proper CONFIG_ARCH_MPC833* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-01-21 08:17:25 +00:00
#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
mpc83xx: USB: Reorganized its support The following patch reorganizes/reworks the USB support for mpc83xx as under:- * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to cpu/mpx83xx/cpu_init.c * Board specific usb_phy_type is read from the environment * Adds USB EHCI specific structure in include/usb/ehci-fsl.h * Copyrights revamped in most of the following files Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-05-25 11:53:16 +00:00
uint32_t temp;
powerpc/usb:Differentiate USB controller base address Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2013-09-12 11:05:49 +00:00
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
mpc83xx: USB: Reorganized its support The following patch reorganizes/reworks the USB support for mpc83xx as under:- * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to cpu/mpx83xx/cpu_init.c * Board specific usb_phy_type is read from the environment * Adds USB EHCI specific structure in include/usb/ehci-fsl.h * Copyrights revamped in most of the following files Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-05-25 11:53:16 +00:00
/* Configure interface. */
mpc83xx: USB: fix: access of ehci struct elements It fixes the access to the 'ehci' struct elements for mpc83xx which should have been taken care of in 4ef01010aa4799c759d75e67007fdd3a38c88c8a Sorry about that. Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-06-24 04:38:40 +00:00
setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
mpc83xx: USB: Reorganized its support The following patch reorganizes/reworks the USB support for mpc83xx as under:- * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to cpu/mpx83xx/cpu_init.c * Board specific usb_phy_type is read from the environment * Adds USB EHCI specific structure in include/usb/ehci-fsl.h * Copyrights revamped in most of the following files Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-05-25 11:53:16 +00:00
/* Wait for clock to stabilize */
do {
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
temp = __raw_readl(&ehci->control);
mpc83xx: USB: Reorganized its support The following patch reorganizes/reworks the USB support for mpc83xx as under:- * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to cpu/mpx83xx/cpu_init.c * Board specific usb_phy_type is read from the environment * Adds USB EHCI specific structure in include/usb/ehci-fsl.h * Copyrights revamped in most of the following files Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-05-25 11:53:16 +00:00
udelay(1000);
} while (!(temp & PHY_CLK_VALID));
#endif
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
}
int cpu_init_r (void)
{
mpc83xx: add QE ethernet support this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
2006-11-03 18:11:15 +00:00
#ifdef CONFIG_QE
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-09-25 23:19:44 +00:00
mpc83xx: add QE ethernet support this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
2006-11-03 18:11:15 +00:00
qe_init(qe_base);
qe_reset();
#endif
* Patch by Eran Liberty Add support for the Freescale MPC8349ADS board.
2005-07-28 15:08:46 +00:00
return 0;
}
mpc83xx: Add support for the display of reset status 83xx processor family has many reset sources, such as power on reset, software hard reset, software soft reset, JTAG, bus monitor, software watchdog, check stop reset, external hard reset, external software reset. sometimes, to figure out the fault of system, we need to know the cause of reset early before the prompt of u-boot present. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-06-25 02:41:56 +00:00
mpc83xx: Store and display Arbiter Event Register values Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-28 21:09:19 +00:00
/*
* Print out the bus arbiter event
*/
#if defined(CONFIG_DISPLAY_AER_FULL)
static int print_83xx_arb_event(int force)
{
static char* event[] = {
"Address Time Out",
"Data Time Out",
"Address Only Transfer Type",
"External Control Word Transfer Type",
"Reserved Transfer Type",
"Transfer Error",
"reserved",
"reserved"
};
static char* master[] = {
"e300 Core Data Transaction",
"reserved",
"e300 Core Instruction Fetch",
"reserved",
"TSEC1",
"TSEC2",
"USB MPH",
"USB DR",
"Encryption Core",
"I2C Boot Sequencer",
"JTAG",
"reserved",
"eSDHC",
"PCI1",
"PCI2",
"DMA",
"QUICC Engine 00",
"QUICC Engine 01",
"QUICC Engine 10",
"QUICC Engine 11",
"reserved",
"reserved",
"reserved",
"reserved",
"SATA1",
"SATA2",
"SATA3",
"SATA4",
"reserved",
"PCI Express 1",
"PCI Express 2",
"TDM-DMAC"
};
static char *transfer[] = {
"Address-only, Clean Block",
"Address-only, lwarx reservation set",
"Single-beat or Burst write",
"reserved",
"Address-only, Flush Block",
"reserved",
"Burst write",
"reserved",
"Address-only, sync",
"Address-only, tlbsync",
"Single-beat or Burst read",
"Single-beat or Burst read",
"Address-only, Kill Block",
"Address-only, icbi",
"Burst read",
"reserved",
"Address-only, eieio",
"reserved",
"Single-beat write",
"reserved",
"ecowx - Illegal single-beat write",
"reserved",
"reserved",
"reserved",
"Address-only, TLB Invalidate",
"reserved",
"Single-beat or Burst read",
"reserved",
"eciwx - Illegal single-beat read",
"reserved",
"Burst read",
"reserved"
};
ppc: Move arbiter fields to arch_global_data Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:57 +00:00
int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
Coding Style cleanup: replace leading SPACEs by TABs Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
2013-10-04 15:43:24 +00:00
>> AEATR_EVENT_SHIFT;
ppc: Move arbiter fields to arch_global_data Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:57 +00:00
int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
Coding Style cleanup: replace leading SPACEs by TABs Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
2013-10-04 15:43:24 +00:00
>> AEATR_MSTR_ID_SHIFT;
ppc: Move arbiter fields to arch_global_data Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:57 +00:00
int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
Coding Style cleanup: replace leading SPACEs by TABs Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
2013-10-04 15:43:24 +00:00
>> AEATR_TBST_SHIFT;
ppc: Move arbiter fields to arch_global_data Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:57 +00:00
int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
Coding Style cleanup: replace leading SPACEs by TABs Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
2013-10-04 15:43:24 +00:00
>> AEATR_TSIZE_SHIFT;
ppc: Move arbiter fields to arch_global_data Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:57 +00:00
int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
Coding Style cleanup: replace leading SPACEs by TABs Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
2013-10-04 15:43:24 +00:00
>> AEATR_TTYPE_SHIFT;
mpc83xx: Store and display Arbiter Event Register values Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-28 21:09:19 +00:00
ppc: Move arbiter fields to arch_global_data Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:57 +00:00
if (!force && !gd->arch.arbiter_event_address)
mpc83xx: Store and display Arbiter Event Register values Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-28 21:09:19 +00:00
return 0;
puts("Arbiter Event Status:\n");
ppc: Move arbiter fields to arch_global_data Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:57 +00:00
printf(" Event Address: 0x%08lX\n",
gd->arch.arbiter_event_address);
mpc83xx: Store and display Arbiter Event Register values Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-28 21:09:19 +00:00
printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
ppc: Move arbiter fields to arch_global_data Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:57 +00:00
return gd->arch.arbiter_event_address;
mpc83xx: Store and display Arbiter Event Register values Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-28 21:09:19 +00:00
}
#elif defined(CONFIG_DISPLAY_AER_BRIEF)
static int print_83xx_arb_event(int force)
{
ppc: Move arbiter fields to arch_global_data Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:57 +00:00
if (!force && !gd->arch.arbiter_event_address)
mpc83xx: Store and display Arbiter Event Register values Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-28 21:09:19 +00:00
return 0;
printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
ppc: Move arbiter fields to arch_global_data Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:57 +00:00
gd->arch.arbiter_event_attributes,
gd->arch.arbiter_event_address);
mpc83xx: Store and display Arbiter Event Register values Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-28 21:09:19 +00:00
ppc: Move arbiter fields to arch_global_data Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:57 +00:00
return gd->arch.arbiter_event_address;
mpc83xx: Store and display Arbiter Event Register values Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-28 21:09:19 +00:00
}
#endif /* CONFIG_DISPLAY_AER_xxxx */
cpu: Add MPC83xx CPU driver Add a CPU driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-06 08:23:45 +00:00
#ifndef CONFIG_CPU_MPC83XX
mpc83xx: Add support for the display of reset status 83xx processor family has many reset sources, such as power on reset, software hard reset, software soft reset, JTAG, bus monitor, software watchdog, check stop reset, external hard reset, external software reset. sometimes, to figure out the fault of system, we need to know the cause of reset early before the prompt of u-boot present. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-06-25 02:41:56 +00:00
/*
* Figure out the cause of the reset
*/
int prt_83xx_rsr(void)
{
static struct {
ulong mask;
char *desc;
} bits[] = {
{
RSR_SWSR, "Software Soft"}, {
RSR_SWHR, "Software Hard"}, {
RSR_JSRS, "JTAG Soft"}, {
RSR_CSHR, "Check Stop"}, {
RSR_SWRS, "Software Watchdog"}, {
RSR_BMRS, "Bus Monitor"}, {
RSR_SRS, "External/Internal Soft"}, {
RSR_HRS, "External/Internal Hard"}
};
arch/powerpc: Simplify some calculations using ARRAY_SIZE() macro. Replace a number of array length calculations with the ARRAY_SIZE() macro, for clarity. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-23 10:49:21 +00:00
static int n = ARRAY_SIZE(bits);
ppc: Move reset_status to arch_global_data Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-13 20:48:56 +00:00
ulong rsr = gd->arch.reset_status;
mpc83xx: Add support for the display of reset status 83xx processor family has many reset sources, such as power on reset, software hard reset, software soft reset, JTAG, bus monitor, software watchdog, check stop reset, external hard reset, external software reset. sometimes, to figure out the fault of system, we need to know the cause of reset early before the prompt of u-boot present. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-06-25 02:41:56 +00:00
int i;
char *sep;
puts("Reset Status:");
sep = " ";
for (i = 0; i < n; i++)
if (rsr & bits[i].mask) {
printf("%s%s", sep, bits[i].desc);
sep = ", ";
}
mpc83xx: Store and display Arbiter Event Register values Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-28 21:09:19 +00:00
puts("\n");
#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
print_83xx_arb_event(rsr & RSR_BMRS);
#endif
puts("\n");
mpc83xx: Add support for the display of reset status 83xx processor family has many reset sources, such as power on reset, software hard reset, software soft reset, JTAG, bus monitor, software watchdog, check stop reset, external hard reset, external software reset. sometimes, to figure out the fault of system, we need to know the cause of reset early before the prompt of u-boot present. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-06-25 02:41:56 +00:00
return 0;
}
cpu: Add MPC83xx CPU driver Add a CPU driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-06 08:23:45 +00:00
#endif
Reference in a new issue Copy permalink