2019-08-27 06:26:08 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019 NXP
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*/
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#ifndef __IMX8MM_EVK_H
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#define __IMX8MM_EVK_H
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#include <linux/sizes.h>
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2020-05-10 17:40:09 +00:00
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#include <linux/stringify.h>
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2019-08-27 06:26:08 +00:00
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#include <asm/arch/imx-regs.h>
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2022-07-12 14:36:21 +00:00
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#define UBOOT_ITB_OFFSET 0x57C00
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#define FSPI_CONF_BLOCK_SIZE 0x1000
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#define UBOOT_ITB_OFFSET_FSPI \
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(UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE)
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#ifdef CONFIG_FSPI_CONF_HEADER
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_UBOOT_BASE \
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2022-07-12 14:36:21 +00:00
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(QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI)
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#else
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_UBOOT_BASE \
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2019-08-27 06:26:08 +00:00
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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2022-07-12 14:36:21 +00:00
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#endif
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2019-08-27 06:26:08 +00:00
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#ifdef CONFIG_SPL_BUILD
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/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
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#define CONFIG_MALLOC_F_ADDR 0x930000
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/* For RAW image gives a error info not panic */
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#endif
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2020-12-18 06:50:07 +00:00
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 2) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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2019-08-27 06:26:08 +00:00
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/* Initial environment variables */
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2022-12-04 15:03:50 +00:00
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#define CFG_EXTRA_ENV_SETTINGS \
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2020-12-18 06:50:07 +00:00
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BOOTENV \
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2021-08-23 14:25:30 +00:00
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"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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2019-12-16 19:09:22 +00:00
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"image=Image\0" \
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2019-12-11 17:31:03 +00:00
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"console=ttymxc1,115200\0" \
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2021-03-19 07:56:57 +00:00
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"fdt_addr_r=0x43000000\0" \
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2019-12-16 19:09:22 +00:00
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"boot_fit=no\0" \
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2021-03-19 07:56:57 +00:00
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"fdtfile=imx8mm-evk.dtb\0" \
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2019-08-27 06:26:08 +00:00
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"initrd_addr=0x43800000\0" \
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2020-08-21 13:39:43 +00:00
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"bootm_size=0x10000000\0" \
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2021-12-11 19:55:52 +00:00
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"mmcpart=1\0" \
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2022-04-15 04:23:41 +00:00
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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2019-08-27 06:26:08 +00:00
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/* Link Definitions */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_INIT_RAM_ADDR 0x40000000
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#define CFG_SYS_INIT_RAM_SIZE 0x200000
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2019-08-27 06:26:08 +00:00
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2022-11-16 18:10:37 +00:00
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#define CFG_SYS_SDRAM_BASE 0x40000000
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2019-08-27 06:26:08 +00:00
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
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2022-12-04 15:03:53 +00:00
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#define CFG_FEC_MXC_PHYADDR 0
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2019-10-22 03:30:04 +00:00
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2019-08-27 06:26:08 +00:00
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#endif
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