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https://github.com/AsahiLinux/u-boot
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96 lines
2.9 KiB
C
96 lines
2.9 KiB
C
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/*
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* Copyright Boundary Devices
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/kernel.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/lpddr4_define.h>
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/* MNT Reform2 */
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#define CFG_DDR_MB 4096
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#define CFG_DDR_RANK_BITS 1
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#define CFG_DDR_CHANNEL_CNT 2
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#ifdef WR_POST_EXT_3200
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#define CH2_VAL_INIT4 ((LPDDR4_MR3 << 16) | 0x00020008)
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#else
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#define CH2_VAL_INIT4 ((LPDDR4_MR3 << 16) | 8)
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#endif
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#if CFG_DDR_MB == 1024
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/* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */
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#define CH2_VAL_DDRC_ADDRMAP0_R0 0x0000001F
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#define CH2_VAL_DDRC_ADDRMAP6_R0 0x0F070707
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#elif CFG_DDR_MB == 2048
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/* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
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#define CH2_VAL_DDRC_ADDRMAP0_R0 0x0000001F
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#define CH2_VAL_DDRC_ADDRMAP6_R0 0x07070707
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/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
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#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000016
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#define CH2_VAL_DDRC_ADDRMAP6_R1 0x0F070707
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#elif CFG_DDR_MB == 3072
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/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
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#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000015
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#define CH2_VAL_DDRC_ADDRMAP6_R1 0x48080707
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#elif CFG_DDR_MB == 4096
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/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
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#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000017
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#define CH2_VAL_DDRC_ADDRMAP6_R1 0x07070707
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#else
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#error unsupported memory size
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#endif
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#define LPDDR4_CS_R0 0x1 /* 0 rank bits, 1 chip select */
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#define LPDDR4_CS_R1 0x3 /* 1 rank bit, 2 chip selects */
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#if (CFG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
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#ifdef CH2_VAL_DDRC_ADDRMAP0_R0
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#define CH2_LPDDR4_CS LPDDR4_CS_R0
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#define CH2_VAL_DDRC_ADDRMAP0 CH2_VAL_DDRC_ADDRMAP0_R0
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#define CH2_VAL_DDRC_ADDRMAP6 CH2_VAL_DDRC_ADDRMAP6_R0
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#else
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#error unsupported memory rank/size
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#endif
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/*
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* rank0 will succeed, even if really rank 1, so we need
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* to probe memory if rank0 succeeds
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*/
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#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
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#define CH2_LPDDR4_CS_NEW LPDDR4_CS_R1
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#define CH2_VAL_DDRC_ADDRMAP0_NEW CH2_VAL_DDRC_ADDRMAP0_R1
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#define CH2_VAL_DDRC_ADDRMAP6_NEW CH2_VAL_DDRC_ADDRMAP6_R1
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#endif
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#elif (CFG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
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#ifdef CH2_VAL_DDRC_ADDRMAP0_R1
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#define CH2_LPDDR4_CS LPDDR4_CS_R1
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#define CH2_VAL_DDRC_ADDRMAP0 CH2_VAL_DDRC_ADDRMAP0_R1
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#define CH2_VAL_DDRC_ADDRMAP6 CH2_VAL_DDRC_ADDRMAP6_R1
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#else
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#error unsupported memory rank/size
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#endif
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#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
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#define CH2_LPDDR4_CS_NEW LPDDR4_CS_R0
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#define CH2_VAL_DDRC_ADDRMAP0_NEW CH2_VAL_DDRC_ADDRMAP0_R0
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#define CH2_VAL_DDRC_ADDRMAP6_NEW CH2_VAL_DDRC_ADDRMAP6_R0
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#endif
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#else
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#error unsupported rank bits
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#endif
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#if (CFG_DDR_CHANNEL_CNT == 2)
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#if (CFG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
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#error unsupported options
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#endif
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#if (CFG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
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#error unsupported options
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#endif
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#endif
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