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u-boot/include/configs/socfpga_common.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*/
arm: socfpga: fix trivial header preprocessor for socfpga_common.h Replace__CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ with __CONFIG_SOCFPGA_COMMON_H__ as the file is now called socfpga_common.h Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-03 22:05:59 +00:00
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
common: Drop linux/stringify.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:09 +00:00
#include <linux/stringify.h>
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
/*
* High level configuration
*/
#define CONFIG_CLOCKS
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* Memory configurations
*/
#define PHYS_SDRAM_1 0x0
arm: socfpga: Add example UDC config Add example of an USB UDC configuration with DFU and UMS. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@altera.com> Acked-by: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2014-11-04 03:25:09 +00:00
#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
arm: socfpga: Add config and defconfig for Arria 10 Add config and defconfig for the Arria10 and update socfpga_common.h. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:46 +00:00
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
configs: socfpga: Change to use SOCFPGA_PHYS_OCRAM_SIZE macro Change to use SOCFPGA_PHYS_OCRAM_SIZE macro for onchip RAM size. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-06 08:55:19 +00:00
#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
configs: socfpga: Add CONFIG_SPL_PAD_TO Add CONFIG_SPL_PAD_TO for Gen5 and Arria 10. CONFIG_SPL_PAD_TO is set to size of OCRAM. This is preparation for image padding change in socfpgaimage. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-12-22 01:53:25 +00:00
#define CONFIG_SPL_PAD_TO 0x10000
arm: socfpga: Add config and defconfig for Arria 10 Add config and defconfig for the Arria10 and update socfpga_common.h. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:46 +00:00
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
configs: socfpga: Add CONFIG_SPL_PAD_TO Add CONFIG_SPL_PAD_TO for Gen5 and Arria 10. CONFIG_SPL_PAD_TO is set to size of OCRAM. This is preparation for image padding change in socfpgaimage. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-12-22 01:53:25 +00:00
#define CONFIG_SPL_PAD_TO 0x40000
arm: socfpga: put initial U-Boot stack into DDR If SPL post-reloc stage puts the stack into DDR, U-Boot should be able to do that, too. The reason to do so is that this way, U-Boot initial stack can be larger than SPL initial stack. In situations where we want to save the SPL in SRAM for next boot without reloading, this prevents overwriting the SPL DTB in SRAM if U-Boot stack usage gets too high. To achieve this, the malloc definition for a10 is moved up and sligthly changed to ensure CONFIG_SYS_INIT_RAM_SIZE is the remaining available size. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:04 +00:00
/* SPL memory allocation configuration, this is for FAT implementation */
#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
#endif
configs: socfpga: Change to use SOCFPGA_PHYS_OCRAM_SIZE macro Change to use SOCFPGA_PHYS_OCRAM_SIZE macro for onchip RAM size. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-06 08:55:19 +00:00
#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
CONFIG_SYS_SPL_MALLOC_SIZE)
arm: socfpga: put initial U-Boot stack into DDR If SPL post-reloc stage puts the stack into DDR, U-Boot should be able to do that, too. The reason to do so is that this way, U-Boot initial stack can be larger than SPL initial stack. In situations where we want to save the SPL in SRAM for next boot without reloading, this prevents overwriting the SPL DTB in SRAM if U-Boot stack usage gets too high. To achieve this, the malloc definition for a10 is moved up and sligthly changed to ensure CONFIG_SYS_INIT_RAM_SIZE is the remaining available size. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:04 +00:00
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE)
arm: socfpga: Add config and defconfig for Arria 10 Add config and defconfig for the Arria10 and update socfpga_common.h. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:46 +00:00
#endif
arm: socfpga: Fix bootcounter located at the end of internal SRAM Commit 768f23dc8ae3 ("ARM: socfpga: Put stack at the end of SRAM") broke those socfpga boards that keep the bootcounter at the end of the internal SRAM as the bootcounter needs 8 bytes by default and thus the very first SPL call to board_init_f_alloc_reserve overwrites the bootcounter. This patch allows to move the initial stack pointer down a bit by checking if CONFIG_SYS_BOOTCOUNT_ADDR is located in the internal SRAM area and then using this address as location for the start of the stack pointer. No new macros / defines are added by this approach. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-10-30 09:00:22 +00:00
/*
* Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
* SRAM as bootcounter storage. Make sure to not put the stack directly
* at this address to not overwrite the bootcounter by checking, if the
* bootcounter address is located in the internal SRAM.
*/
#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
(CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE)))
arm: socfpga: put initial U-Boot stack into DDR If SPL post-reloc stage puts the stack into DDR, U-Boot should be able to do that, too. The reason to do so is that this way, U-Boot initial stack can be larger than SPL initial stack. In situations where we want to save the SPL in SRAM for next boot without reloading, this prevents overwriting the SPL DTB in SRAM if U-Boot stack usage gets too high. To achieve this, the malloc definition for a10 is moved up and sligthly changed to ensure CONFIG_SYS_INIT_RAM_SIZE is the remaining available size. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:04 +00:00
#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
arm: socfpga: Fix bootcounter located at the end of internal SRAM Commit 768f23dc8ae3 ("ARM: socfpga: Put stack at the end of SRAM") broke those socfpga boards that keep the bootcounter at the end of the internal SRAM as the bootcounter needs 8 bytes by default and thus the very first SPL call to board_init_f_alloc_reserve overwrites the bootcounter. This patch allows to move the initial stack pointer down a bit by checking if CONFIG_SYS_BOOTCOUNT_ADDR is located in the internal SRAM area and then using this address as location for the start of the stack pointer. No new macros / defines are added by this approach. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-10-30 09:00:22 +00:00
#else
arm: socfpga: put initial U-Boot stack into DDR If SPL post-reloc stage puts the stack into DDR, U-Boot should be able to do that, too. The reason to do so is that this way, U-Boot initial stack can be larger than SPL initial stack. In situations where we want to save the SPL in SRAM for next boot without reloading, this prevents overwriting the SPL DTB in SRAM if U-Boot stack usage gets too high. To achieve this, the malloc definition for a10 is moved up and sligthly changed to ensure CONFIG_SYS_INIT_RAM_SIZE is the remaining available size. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:04 +00:00
#define CONFIG_SPL_STACK \
ARM: socfpga: Put stack at the end of SRAM The global data are in the .data section, so there's no point in reserving any space for it above stack. Put stack at the end of SRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-04-26 20:23:05 +00:00
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
arm: socfpga: Fix bootcounter located at the end of internal SRAM Commit 768f23dc8ae3 ("ARM: socfpga: Put stack at the end of SRAM") broke those socfpga boards that keep the bootcounter at the end of the internal SRAM as the bootcounter needs 8 bytes by default and thus the very first SPL call to board_init_f_alloc_reserve overwrites the bootcounter. This patch allows to move the initial stack pointer down a bit by checking if CONFIG_SYS_BOOTCOUNT_ADDR is located in the internal SRAM area and then using this address as location for the start of the stack pointer. No new macros / defines are added by this approach. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-10-30 09:00:22 +00:00
#endif
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
arm: socfpga: put initial U-Boot stack into DDR If SPL post-reloc stage puts the stack into DDR, U-Boot should be able to do that, too. The reason to do so is that this way, U-Boot initial stack can be larger than SPL initial stack. In situations where we want to save the SPL in SRAM for next boot without reloading, this prevents overwriting the SPL DTB in SRAM if U-Boot stack usage gets too high. To achieve this, the malloc definition for a10 is moved up and sligthly changed to ensure CONFIG_SYS_INIT_RAM_SIZE is the remaining available size. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:04 +00:00
/*
* U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
* phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
* in U-Boot pre-reloc is higher than in SPL.
*/
#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
#else
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
#endif
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
* U-Boot general configurations
*/
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
/*
* Cache
*/
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/*
* Ethernet on SoC (EMAC)
*/
ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGET This was never used, is not used anywhere and is just in the way by adding annoying ifdeffery. Get rid of it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-04-22 23:26:10 +00:00
#ifdef CONFIG_CMD_NET
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
#define CONFIG_DW_ALTDESCRIPTOR
#endif
/*
* FPGA Driver
*/
#ifdef CONFIG_CMD_FPGA
#define CONFIG_FPGA_COUNT 1
#endif
arm: socfpga: Enable all FPGA config support for Arria 10 Enable all FPGA config support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-26 05:05:44 +00:00
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
/*
* L4 OSC1 Timer 0
*/
ARM: socfpga: Convert Arria10 to timer framework Switch the Arria10 from ad-hoc hardcoded timer to timer framework and the DW APB timer driver. This allows the A10 to extract timer information, like timer rate, from clock framework and thus DT instead of having it hardcoded in U-Boot configuration files. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-18 14:00:31 +00:00
#ifndef CONFIG_TIMER
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
ARM: socfpga: Permit overriding the default timer frequency The default timer rate may be different than 25 MHz, permit overriding the default rate in board configuration file. Ultimatelly, this should be properly handled by a clock driver, however that is not available on Gen5 yet. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-02-15 13:10:02 +00:00
#ifndef CONFIG_SYS_TIMER_RATE
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
#define CONFIG_SYS_TIMER_RATE 25000000
ARM: socfpga: Convert Arria10 to timer framework Switch the Arria10 from ad-hoc hardcoded timer to timer framework and the DW APB timer driver. This allows the A10 to extract timer information, like timer rate, from clock framework and thus DT instead of having it hardcoded in U-Boot configuration files. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-18 14:00:31 +00:00
#endif
ARM: socfpga: Permit overriding the default timer frequency The default timer rate may be different than 25 MHz, permit overriding the default rate in board configuration file. Ultimatelly, this should be properly handled by a clock driver, however that is not available on Gen5 yet. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-02-15 13:10:02 +00:00
#endif
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
/*
* L4 Watchdog
*/
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ 25000
/*
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
#endif
arm: socfpga: Add support for Denali NAND controller Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
2015-12-20 03:00:46 +00:00
/*
* NAND Support
*/
#ifdef CONFIG_NAND_DENALI
ARM: socfpga: Add missing Denali NAND config options The Denali SPL shim won't build without these options set, set them accordingly to fix the build error and let the SPL shim to work correctly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-02-15 13:10:09 +00:00
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
arm: socfpga: Add support for Denali NAND controller Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
2015-12-20 03:00:46 +00:00
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
arm: socfpga: Add Cadence QSPI support to config header With this driver enabled for SoCFPGA, access to SPI NOR flash is supported. The configuration (page size, timing info) will be taken from the DT. See socrates as an example. This QSPI supports depends on DT. So QSPI is only enabled if CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-11-07 11:37:52 +00:00
/*
* QSPI support
*/
/* QSPI reference clock */
#ifndef __ASSEMBLY__
unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
#endif
arm: socfpga: config: Add USB support example Add example configuration stub for the DWC2 USB controller. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Pavel Machek <pavel@denx.de>
2014-10-24 21:34:25 +00:00
/*
* USB
*/
arm: socfpga: Add example UDC config Add example of an USB UDC configuration with DFU and UMS. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@altera.com> Acked-by: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2014-11-04 03:25:09 +00:00
/*
* USB Gadget (DFU, UMS)
*/
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
ARM: socfpga: Reduce the DFU buffer size There is no point in having such gargantuan buffer, it only requires huge malloc area. Reduce the DFU buffer size. Signed-off-by: Marek Vasut <marex@denx.de>
2016-10-29 19:15:56 +00:00
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
arm: socfpga: Add example UDC config Add example of an USB UDC configuration with DFU and UMS. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@altera.com> Acked-by: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2014-11-04 03:25:09 +00:00
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* USB IDs */
usb: gadget Move: CONFIG_G_DNL_* to Kconfig And also reformat defconfigs using "make savedefconfig" rule. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2016-04-13 11:20:30 +00:00
#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
arm: socfpga: Add example UDC config Add example of an USB UDC configuration with DFU and UMS. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@altera.com> Acked-by: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2014-11-04 03:25:09 +00:00
#endif
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
/*
* U-Boot environment
*/
arm: socfpga: Consolidate SDMMC environment Remove the duplication of SDMMC environment configuration from each boards' configuration header file into socfpga_common.h Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de>
2015-12-21 13:02:45 +00:00
/* Environment for SDMMC boot */
arm: socfpga: Enabling U-Boot environment support in QSPI Enabling the support of storing U-Boot environment within serial NOR flash. By default, its still store into SDMMC Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de>
2016-02-24 08:50:22 +00:00
/* Environment for QSPI boot */
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
/*
* SPL
arm: socfpga: Zap spl.h and ad-hoc related syms Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h contained various ad-hoc symbols, zap those symbols as well and rework the board configuration a little so it doesn't depend on them. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-16 10:25:40 +00:00
*
ARM: socfpga: Enable SPL memory allocation Enable memory allocation in SPL for preparation to enable FAT in SPL. Memory allocation is needed by FAT to work properly. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-12-05 07:58:04 +00:00
* SRAM Memory layout for gen 5:
arm: socfpga: Zap spl.h and ad-hoc related syms Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h contained various ad-hoc symbols, zap those symbols as well and rework the board configuration a little so it doesn't depend on them. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-16 10:25:40 +00:00
*
* 0xFFFF_0000 ...... Start of SRAM
* 0xFFFF_xxxx ...... Top of stack (grows down)
arm: socfpga: fix comment about SPL memory layout The comment about SPL memory layout for socfpga gen5 is outdated: the initial malloc memory is now at the end of the SRAM, gd is below it (see board_init_f_alloc_reserve). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:03 +00:00
* 0xFFFF_yyyy ...... Global Data
* 0xFFFF_zzzz ...... Malloc area
* 0xFFFF_FFFF ...... End of SRAM
ARM: socfpga: Enable SPL memory allocation Enable memory allocation in SPL for preparation to enable FAT in SPL. Memory allocation is needed by FAT to work properly. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-12-05 07:58:04 +00:00
*
* SRAM Memory layout for Arria 10:
* 0xFFE0_0000 ...... Start of SRAM (bottom)
* 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
* 0xFFEy_yyyy ...... Global Data
* 0xFFEz_zzzz ...... Malloc area (grows up to top)
* 0xFFE3_FFFF ...... End of SRAM (top)
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
*/
arm: socfpga: make SPL_TEXT_BASE overridable To boot from fpga on socfpga gen5, we need to set CONFIG_SPL_TEXT_BASE to 0xC0000000 (hps2fpgaslaves base address). Since converting CONFIG_SPL_TEXT_BASE to Kconfig hasn't been successful so far, let's make this value overridable in socfpga_common.h, so that we can have different board configs override this in socfpga_common.h. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-03-15 19:44:32 +00:00
#ifndef CONFIG_SPL_TEXT_BASE
arm: socfpga: Add config and defconfig for Arria 10 Add config and defconfig for the Arria10 and update socfpga_common.h. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:46 +00:00
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
arm: socfpga: make SPL_TEXT_BASE overridable To boot from fpga on socfpga gen5, we need to set CONFIG_SPL_TEXT_BASE to 0xC0000000 (hps2fpgaslaves base address). Since converting CONFIG_SPL_TEXT_BASE to Kconfig hasn't been successful so far, let's make this value overridable in socfpga_common.h, so that we can have different board configs override this in socfpga_common.h. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-03-15 19:44:32 +00:00
#endif
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
arm: socfpga: spl: Add support for booting from SD/MMC Add code and configuration options to support booting from RAW SD/MMC card as well as for ext4/vfat filesystems. Enable support for booting from SD/MMC card, but don't enable the filesystem support just yet to retain compatibility with old SoCFPGA card format. Signed-off-by: Marek Vasut <marex@denx.de>
2015-07-09 22:04:23 +00:00
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
spl: Kconfig: Replace CONFIG_SPL_EXT_SUPPORT to CONFIG_SPL_FS_EXT4 Replace CONFIG_SPL_EXT_SUPPORT to CONFIG_SPLY_FS_EXT4 so both obj-$(CONFIG_$(SPL_)FS_EXT4) and CONFIG_IS_ENABLED(FS_EXT4) can be used to control the build in both SPL and U-Boot. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-23 06:20:05 +00:00
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
ARM: socfpga: update CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to u-boot.img Bring cyclone5 / arria5 / arria10 in line with convention and use u-boot.img as CONFIG_SPL_FS_LOAD_PAYLOAD_NAME. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
2019-08-07 17:37:36 +00:00
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
arm: socfpga: Add distro boot to socfpga common header This adds a common environment and support for distro boot in the common socfpga header. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de> -- Changes in v5: - Per Frank, to support OpenSuse the ENV must be after the GPT Changes in v4: - Move env back to being right after the MBR Changes in v3: - fix spacing between asterix - remove verify=n as a default setting Changes in v2: - Remove unneeded CONFIG_BOOTFILE and fdt_addr - cleanup spacing in MMC env size common Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2017-04-13 14:30:29 +00:00
#endif
#else
#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
arm: socfpga: spl: Add support for booting from SD/MMC Add code and configuration options to support booting from RAW SD/MMC card as well as for ext4/vfat filesystems. Enable support for booting from SD/MMC card, but don't enable the filesystem support just yet to retain compatibility with old SoCFPGA card format. Signed-off-by: Marek Vasut <marex@denx.de>
2015-07-09 22:04:23 +00:00
#endif
#endif
arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
arm: socfpga: spl: Add support for booting from QSPI Add code and configuration options to support booting from QSPI NOR. Enable support for booting from QSPI NOR. Signed-off-by: Marek Vasut <marex@denx.de>
2015-07-21 05:50:03 +00:00
/* SPL QSPI boot support */
arm: socfpga: Add support for Denali NAND controller Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
2015-12-20 03:00:46 +00:00
/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB. Handle the difference. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-08 16:44:43 +00:00
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
arm: socfpga: Add support for Denali NAND controller Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
2015-12-20 03:00:46 +00:00
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB. Handle the difference. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-08 16:44:43 +00:00
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
#endif
arm: socfpga: Add support for Denali NAND controller Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
2015-12-20 03:00:46 +00:00
#endif
arm: socfpga: Add distro boot to socfpga common header This adds a common environment and support for distro boot in the common socfpga header. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de> -- Changes in v5: - Per Frank, to support OpenSuse the ENV must be after the GPT Changes in v4: - Move env back to being right after the MBR Changes in v3: - fix spacing between asterix - remove verify=n as a default setting Changes in v2: - Remove unneeded CONFIG_BOOTFILE and fdt_addr - cleanup spacing in MMC env size common Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2017-04-13 14:30:29 +00:00
/* Extra Environment */
#ifndef CONFIG_SPL_BUILD
arm: socfpga: allow configs without network support Currently, socfpga_common.h does not allow configurations without network support. This is because CONFIG_CMD_PXE is defined in this file and distro mode has DHCP hard-coded as available. Fix this by moving CONFIG_CMD_PXE and CONFIG_MENU to the defconfigs and by making DHCP optional in BOOT_TARGET_DEVICES(func). Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
2018-01-25 06:18:27 +00:00
#ifdef CONFIG_CMD_DHCP
#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
#else
#define BOOT_TARGET_DEVICES_DHCP(func)
#endif
xilinx: Only enable dist boot pxe when DHCP is enabled Otherwise, we see this: In file included from include/configs/zynq-common.h:183:0, from include/config.h:5, from include/common.h:21, from env/common.c:11: include/config_distro_bootcmd.h:319:2: error: expected ?}? before ?BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE? BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE ^ include/config_distro_bootcmd.h:319:2: note: in definition of macro ?BOOTENV_DEV_NAME_PXE? Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13 20:26:40 +00:00
#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
arm: socfpga: Add distro boot to socfpga common header This adds a common environment and support for distro boot in the common socfpga header. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de> -- Changes in v5: - Per Frank, to support OpenSuse the ENV must be after the GPT Changes in v4: - Move env back to being right after the MBR Changes in v3: - fix spacing between asterix - remove verify=n as a default setting Changes in v2: - Remove unneeded CONFIG_BOOTFILE and fdt_addr - cleanup spacing in MMC env size common Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2017-04-13 14:30:29 +00:00
#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else
#define BOOT_TARGET_DEVICES_PXE(func)
#endif
#ifdef CONFIG_CMD_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
#else
#define BOOT_TARGET_DEVICES_MMC(func)
#endif
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_PXE(func) \
arm: socfpga: allow configs without network support Currently, socfpga_common.h does not allow configurations without network support. This is because CONFIG_CMD_PXE is defined in this file and distro mode has DHCP hard-coded as available. Fix this by moving CONFIG_CMD_PXE and CONFIG_MENU to the defconfigs and by making DHCP optional in BOOT_TARGET_DEVICES(func). Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
2018-01-25 06:18:27 +00:00
BOOT_TARGET_DEVICES_DHCP(func)
arm: socfpga: Add distro boot to socfpga common header This adds a common environment and support for distro boot in the common socfpga header. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de> -- Changes in v5: - Per Frank, to support OpenSuse the ENV must be after the GPT Changes in v4: - Move env back to being right after the MBR Changes in v3: - fix spacing between asterix - remove verify=n as a default setting Changes in v2: - Remove unneeded CONFIG_BOOTFILE and fdt_addr - cleanup spacing in MMC env size common Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2017-04-13 14:30:29 +00:00
#include <config_distro_bootcmd.h>
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"bootm_size=0xa000000\0" \
"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
"fdt_addr_r=0x02000000\0" \
"scriptaddr=0x02100000\0" \
"pxefile_addr_r=0x02200000\0" \
"ramdisk_addr_r=0x02300000\0" \
arm: socfpga: gen5: deassert peripheral reset by default To keep the current behaviour of taking all peripherals out of reset before booting the OS before removing that code from socfpga gen5 SPL, this enables the new behaviour by default for all gen5 boards by adding the environment variable "socfpga_legacy_reset_compat=1" to the default environment. This can be overridden in board config files or by saving an environment without this variable enabled. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-03-01 19:12:31 +00:00
"socfpga_legacy_reset_compat=1\0" \
arm: socfpga: Add distro boot to socfpga common header This adds a common environment and support for distro boot in the common socfpga header. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de> -- Changes in v5: - Per Frank, to support OpenSuse the ENV must be after the GPT Changes in v4: - Move env back to being right after the MBR Changes in v3: - fix spacing between asterix - remove verify=n as a default setting Changes in v2: - Remove unneeded CONFIG_BOOTFILE and fdt_addr - cleanup spacing in MMC env size common Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2017-04-13 14:30:29 +00:00
BOOTENV
#endif
#endif
arm: socfpga: fix trivial header preprocessor for socfpga_common.h Replace__CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ with __CONFIG_SOCFPGA_COMMON_H__ as the file is now called socfpga_common.h Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-03 22:05:59 +00:00
#endif /* __CONFIG_SOCFPGA_COMMON_H__ */
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