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arm: socfpga: Add config and defconfig for Arria 10
Add config and defconfig for the Arria10 and update socfpga_common.h. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan
Marek Vasut
parent
8f4c80c4fd
commit
1b2594030d
3 changed files with 111 additions and 5 deletions
29
configs/socfpga_arria10_defconfig
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29
configs/socfpga_arria10_defconfig
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CONFIG_ARM=y
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
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CONFIG_IDENT_STRING="socfpga_arria10"
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
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CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
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CONFIG_SPL=y
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_IMLS is not set
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CONFIG_CMD_ASKENV=y
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CONFIG_CMD_GREPENV=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_DOS_PARTITION=y
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# CONFIG_SPL_DOS_PARTITION is not set
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DM_GPIO=y
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CONFIG_DWAPB_GPIO=y
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CONFIG_DM_MMC=y
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CONFIG_SYS_NS16550=y
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CONFIG_USE_TINY_PRINTF=y
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66
include/configs/socfpga_arria10_socdk.h
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66
include/configs/socfpga_arria10_socdk.h
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/*
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* Copyright (C) 2015-2017 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
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#define __CONFIG_SOCFGPA_ARRIA10_H__
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#include <asm/arch/base_addr_a10.h>
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/* U-Boot Commands */
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#define CONFIG_FAT_WRITE
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#define CONFIG_HW_WATCHDOG
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/* Booting Linux */
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#define CONFIG_LOADADDR 0x01000000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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/*
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* U-Boot general configurations
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*/
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/* Cache options */
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#define CONFIG_SYS_DCACHE_OFF
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/* Memory configurations */
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#define PHYS_SDRAM_1_SIZE 0x40000000
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/* Ethernet on SoC (EMAC) */
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_PHY_MICREL
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#define CONFIG_PHY_MICREL_KSZ9031
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#endif
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/*
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* U-Boot environment configurations
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*/
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#define CONFIG_ENV_IS_IN_MMC
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/*
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* arguments passed to the bootz command. The value of
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* CONFIG_BOOTARGS goes into the environment value "bootargs".
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* Do note the value will overide also the chosen node in FDT blob.
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*/
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#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
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/*
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* Serial / UART configurations
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*/
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
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/*
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* L4 OSC1 Timer 0
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*/
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/* reload value when timer count to zero */
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#define TIMER_LOAD_VAL 0xFFFFFFFF
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/*
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* Flash configurations
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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/* The rest of the configuration is shared */
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#include <configs/socfpga_common.h>
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#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */
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@ -32,9 +32,13 @@
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#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
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#endif
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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@ -101,13 +105,14 @@
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/*
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* FPGA Driver
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*/
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#ifdef CONFIG_TARGET_SOCFPGA_GEN5
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#ifdef CONFIG_CMD_FPGA
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#define CONFIG_FPGA
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#define CONFIG_FPGA_ALTERA
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#define CONFIG_FPGA_SOCFPGA
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#define CONFIG_FPGA_COUNT 1
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#endif
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#endif
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/*
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* L4 OSC1 Timer 0
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*/
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@ -207,11 +212,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_SYS_NS16550_CLK 1000000
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#else
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#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
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#define CONFIG_SYS_NS16550_CLK 100000000
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS
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#define CONFIG_SYS_NS16550_CLK 50000000
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#endif
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#define CONFIG_CONS_INDEX 1
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@ -298,7 +306,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
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*/
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
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#define CONFIG_SPL_MAX_SIZE (64 * 1024)
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#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
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#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#define CONFIG_SPL_BOARD_INIT
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#endif
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/* SPL SDMMC boot support */
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#ifdef CONFIG_SPL_MMC_SUPPORT
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