2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2015-09-02 18:54:16 +00:00
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* The file use ls102xa/timer.c as a reference.
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*/
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#include <common.h>
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2020-05-10 17:40:02 +00:00
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#include <init.h>
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2019-11-14 19:57:26 +00:00
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#include <time.h>
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2020-10-31 03:38:53 +00:00
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#include <asm/global_data.h>
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2015-09-02 18:54:16 +00:00
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#include <asm/io.h>
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#include <div64.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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2017-06-29 08:16:06 +00:00
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#include <asm/mach-imx/syscounter.h>
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2020-05-10 17:40:11 +00:00
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#include <linux/delay.h>
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2015-09-02 18:54:16 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* This function is intended for SHORT delays only.
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* It will overflow at around 10 seconds @ 400MHz,
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* or 20 seconds @ 200MHz.
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*/
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unsigned long usec2ticks(unsigned long usec)
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{
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ulong ticks;
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if (usec < 1000)
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ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
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else
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ticks = ((usec / 10) * (get_tbclk() / 100000));
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return ticks;
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}
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static inline unsigned long long tick_to_time(unsigned long long tick)
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{
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unsigned long freq;
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asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
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tick *= CONFIG_SYS_HZ;
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do_div(tick, freq);
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return tick;
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}
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static inline unsigned long long us_to_tick(unsigned long long usec)
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{
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unsigned long freq;
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asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
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usec = usec * freq + 999999;
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do_div(usec, 1000000);
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return usec;
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}
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2021-08-28 01:18:30 +00:00
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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2015-09-02 18:54:16 +00:00
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int timer_init(void)
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{
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struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
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unsigned long val, freq;
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2022-12-04 15:13:45 +00:00
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freq = CFG_SC_TIMER_CLK;
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imx: syscounter: make sure asm is volatile
Without the volatile attribute, compilers are entitled to optimize out
the same asm(). In the case of __udelay() in syscounter.c, it calls
`get_ticks()` twice, one for the starting time and the second in the
loop to check the current time. When compilers inline `get_ticks()`
they see the same `mrrc` instructions and optimize out the second one.
This leads to infinite loop since we don't get updated value from the
system counter.
Here is a portion of the disassembly of __udelay:
88: 428b cmp r3, r1
8a: f8ce 20a4 str.w r2, [lr, #164] ; 0xa4
8e: bf08 it eq
90: 4282 cmpeq r2, r0
92: f8ce 30a0 str.w r3, [lr, #160] ; 0xa0
96: d3f7 bcc.n 88 <__udelay+0x88>
98: e8bd 8cf0 ldmia.w sp!, {r4, r5, r6, r7, sl, fp, pc}
Note that final jump / loop at 96 to 88, we don't have any `mrrc`.
With a volatile attribute, the above changes to this:
8a: ec53 2f0e mrrc 15, 0, r2, r3, cr14
8e: 42ab cmp r3, r5
90: f8c1 20a4 str.w r2, [r1, #164] ; 0xa4
94: bf08 it eq
96: 42a2 cmpeq r2, r4
98: f8c1 30a0 str.w r3, [r1, #160] ; 0xa0
9c: d3f5 bcc.n 8a <__udelay+0x8a>
9e: e8bd 8cf0 ldmia.w sp!, {r4, r5, r6, r7, sl, fp, pc}
a2: bf00 nop
I'm advised[1] to put volatile on all asm(), so this commit also adds it
to the asm() in timer_init().
[1]: https://lists.denx.de/pipermail/u-boot/2018-March/322062.html
Signed-off-by: Yasushi SHOJI <yasushi.shoji@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-03-08 04:21:10 +00:00
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asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
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2015-09-02 18:54:16 +00:00
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writel(freq, &sctr->cntfid0);
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/* Enable system counter */
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val = readl(&sctr->cntcr);
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val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
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val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
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writel(val, &sctr->cntcr);
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gd->arch.tbl = 0;
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gd->arch.tbu = 0;
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2022-07-21 10:30:05 +00:00
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gd->arch.timer_rate_hz = freq;
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2015-09-02 18:54:16 +00:00
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return 0;
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}
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2018-09-05 10:56:05 +00:00
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#endif
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2015-09-02 18:54:16 +00:00
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unsigned long long get_ticks(void)
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{
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unsigned long long now;
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imx: syscounter: make sure asm is volatile
Without the volatile attribute, compilers are entitled to optimize out
the same asm(). In the case of __udelay() in syscounter.c, it calls
`get_ticks()` twice, one for the starting time and the second in the
loop to check the current time. When compilers inline `get_ticks()`
they see the same `mrrc` instructions and optimize out the second one.
This leads to infinite loop since we don't get updated value from the
system counter.
Here is a portion of the disassembly of __udelay:
88: 428b cmp r3, r1
8a: f8ce 20a4 str.w r2, [lr, #164] ; 0xa4
8e: bf08 it eq
90: 4282 cmpeq r2, r0
92: f8ce 30a0 str.w r3, [lr, #160] ; 0xa0
96: d3f7 bcc.n 88 <__udelay+0x88>
98: e8bd 8cf0 ldmia.w sp!, {r4, r5, r6, r7, sl, fp, pc}
Note that final jump / loop at 96 to 88, we don't have any `mrrc`.
With a volatile attribute, the above changes to this:
8a: ec53 2f0e mrrc 15, 0, r2, r3, cr14
8e: 42ab cmp r3, r5
90: f8c1 20a4 str.w r2, [r1, #164] ; 0xa4
94: bf08 it eq
96: 42a2 cmpeq r2, r4
98: f8c1 30a0 str.w r3, [r1, #160] ; 0xa0
9c: d3f5 bcc.n 8a <__udelay+0x8a>
9e: e8bd 8cf0 ldmia.w sp!, {r4, r5, r6, r7, sl, fp, pc}
a2: bf00 nop
I'm advised[1] to put volatile on all asm(), so this commit also adds it
to the asm() in timer_init().
[1]: https://lists.denx.de/pipermail/u-boot/2018-March/322062.html
Signed-off-by: Yasushi SHOJI <yasushi.shoji@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-03-08 04:21:10 +00:00
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asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
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2015-09-02 18:54:16 +00:00
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gd->arch.tbl = (unsigned long)(now & 0xffffffff);
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gd->arch.tbu = (unsigned long)(now >> 32);
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return now;
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}
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ulong get_timer(ulong base)
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{
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2018-10-05 09:33:52 +00:00
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return tick_to_time(get_ticks()) - base;
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2015-09-02 18:54:16 +00:00
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}
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2022-07-21 10:30:05 +00:00
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ulong timer_get_boot_us(void)
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{
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if (!gd->arch.timer_rate_hz)
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timer_init();
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return tick_to_time(get_ticks());
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}
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2015-09-02 18:54:16 +00:00
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void __udelay(unsigned long usec)
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{
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unsigned long long tmp;
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ulong tmo;
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tmo = us_to_tick(usec);
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tmp = get_ticks() + tmo; /* get current timestamp */
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while (get_ticks() < tmp) /* loop till event */
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/*NOP*/;
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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unsigned long freq;
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asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
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return freq;
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}
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