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u-boot/board/amcc/katmai/init.S

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[PATCH] Add support for the AMCC Katmai (440SPe) eval board Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 09:57:08 +00:00
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
Coding Style cleanup: remove trailing white space Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-07 11:07:26 +00:00
* SPDX-License-Identifier: GPL-2.0+
[PATCH] Add support for the AMCC Katmai (440SPe) eval board Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 09:57:08 +00:00
*/
#include <ppc_asm.tmpl>
#include <config.h>
Replace "#include <asm-$ARCH/$FILE>" with "#include <asm/$FILE>" The appropriate include/asm-$ARCH directory should already by symlinked to include/asm so using the whole "asm-$ARCH" path is unnecessary. This change should also allow us to move the include/asm-$ARCH directories into their appropriate lib/$ARCH/ directories. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 03:28:07 +00:00
#include <asm/mmu.h>
ppc4xx: Use common NS16550 driver for PPC4xx UART This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-20 14:05:31 +00:00
#include <asm/ppc4xx.h>
[PATCH] Add support for the AMCC Katmai (440SPe) eval board Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 09:57:08 +00:00
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
/**************************************************************************
* TLB table for revA
*************************************************************************/
.globl tlbtabA
tlbtabA:
tlbtab_start
ppc4xx: Small AMCC Katmai 440SPe update Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 09:07:18 +00:00
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
[PATCH] Add support for the AMCC Katmai (440SPe) eval board Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 09:57:08 +00:00
/*
* TLB entries for SDRAM are not needed on this platform.
* They are dynamically generated in the SPD DDR(2) detection
* routine.
*/
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
[PATCH] Add support for the AMCC Katmai (440SPe) eval board Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 09:57:08 +00:00
tlbtab_end
/**************************************************************************
* TLB table for revB
*
* Notice: revB of the 440SPe chip is very strict about PLB real addresses
* and ranges to be mapped for config space: it seems to only work with
* d_nnnn_nnnn range (hangs the core upon config transaction attempts when
* set otherwise) while revA uses c_nnnn_nnnn.
*************************************************************************/
.globl tlbtabB
tlbtabB:
tlbtab_start
ppc4xx: Small AMCC Katmai 440SPe update Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 09:07:18 +00:00
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
[PATCH] Add support for the AMCC Katmai (440SPe) eval board Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 09:57:08 +00:00
/*
* TLB entries for SDRAM are not needed on this platform.
* They are dynamically generated in the SPD DDR(2) detection
* routine.
*/
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
[PATCH] Add support for the AMCC Katmai (440SPe) eval board Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 09:57:08 +00:00
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
[PATCH] Add support for the AMCC Katmai (440SPe) eval board Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 09:57:08 +00:00
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG)
[PATCH] Add support for the AMCC Katmai (440SPe) eval board Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 09:57:08 +00:00
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
[PATCH] Add support for the AMCC Katmai (440SPe) eval board Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 09:57:08 +00:00
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
[PATCH] Add support for the AMCC Katmai (440SPe) eval board Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 09:57:08 +00:00
tlbtab_end
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