u-boot/arch/riscv/include/asm/cache.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2017 Andes Technology Corporation
 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
 */

#ifndef _ASM_RISCV_CACHE_H
#define _ASM_RISCV_CACHE_H

/* cache */
void	cache_flush(void);

/*
 * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
 * We use that value for aligning DMA buffers unless the board config has
 * specified an alternate cache line size.
 */
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN	32
#endif

#endif /* _ASM_RISCV_CACHE_H */
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-06 21:58:06 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
riscv: nx25: include: Add header files to support RISC-V Add header files for RISC-V. Cache, ptregs, data type and other definitions are included. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> 2017-12-26 05:55:51 +00:00			`/*`
			`* Copyright (C) 2017 Andes Technology Corporation`
			`* Rick Chen, Andes Technology Corporation <rick@andestech.com>`
			`*/`

			`#ifndef _ASM_RISCV_CACHE_H`
			`#define _ASM_RISCV_CACHE_H`

riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> 2018-11-07 01:34:06 +00:00			`/* cache */`
			`void cache_flush(void);`

riscv: nx25: include: Add header files to support RISC-V Add header files for RISC-V. Cache, ptregs, data type and other definitions are included. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> 2017-12-26 05:55:51 +00:00			`/*`
			`* The current upper bound for RISCV L1 data cache line sizes is 32 bytes.`
			`* We use that value for aligning DMA buffers unless the board config has`
			`* specified an alternate cache line size.`
			`*/`
			`#ifdef CONFIG_SYS_CACHELINE_SIZE`
			`#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE`
			`#else`
			`#define ARCH_DMA_MINALIGN 32`
			`#endif`

			`#endif /* _ASM_RISCV_CACHE_H */`