2014-07-30 05:08:14 +00:00
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menu "MIPS architecture"
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depends on MIPS
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config SYS_ARCH
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default "mips"
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2014-10-26 13:14:07 +00:00
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config SYS_CPU
|
2016-05-16 09:52:11 +00:00
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default "mips32" if CPU_MIPS32
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default "mips64" if CPU_MIPS64
|
2014-10-26 13:14:07 +00:00
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2014-07-30 05:08:14 +00:00
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choice
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prompt "Target select"
|
2015-05-12 19:46:23 +00:00
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optional
|
2014-07-30 05:08:14 +00:00
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config TARGET_QEMU_MIPS
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bool "Support qemu-mips"
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2014-10-26 13:14:07 +00:00
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_LITTLE_ENDIAN
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2014-10-26 13:14:07 +00:00
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
|
2014-10-26 13:14:07 +00:00
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select SUPPORTS_CPU_MIPS64_R1
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select SUPPORTS_CPU_MIPS64_R2
|
2014-07-30 05:08:14 +00:00
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config TARGET_MALTA
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bool "Support malta"
|
2016-05-17 06:43:28 +00:00
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select DM
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select DM_SERIAL
|
2016-01-29 13:54:52 +00:00
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select DYNAMIC_IO_PORT_BASE
|
2016-05-17 06:43:28 +00:00
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select OF_CONTROL
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select OF_ISA_BUS
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2014-10-26 13:14:07 +00:00
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_LITTLE_ENDIAN
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2014-10-26 13:14:07 +00:00
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
|
2016-05-16 09:52:14 +00:00
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select SUPPORTS_CPU_MIPS32_R6
|
2016-05-26 13:49:36 +00:00
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select SUPPORTS_CPU_MIPS64_R1
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select SUPPORTS_CPU_MIPS64_R2
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select SUPPORTS_CPU_MIPS64_R6
|
2015-01-18 21:00:18 +00:00
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select SWAP_IO_SPACE
|
2016-01-09 16:32:50 +00:00
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select MIPS_L1_CACHE_SHIFT_6
|
2014-07-30 05:08:14 +00:00
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config TARGET_VCT
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bool "Support vct"
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2014-10-26 13:14:07 +00:00
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select SUPPORTS_BIG_ENDIAN
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2014-10-26 13:14:07 +00:00
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
|
2015-01-29 01:28:02 +00:00
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select SYS_MIPS_CACHE_INIT_RAM_LOAD
|
2014-07-30 05:08:14 +00:00
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config TARGET_DBAU1X00
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bool "Support dbau1x00"
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2014-10-26 13:14:07 +00:00
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_LITTLE_ENDIAN
|
2014-10-26 13:14:07 +00:00
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
|
2015-01-29 01:28:02 +00:00
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select SYS_MIPS_CACHE_INIT_RAM_LOAD
|
2015-12-26 18:55:37 +00:00
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select MIPS_TUNE_4KC
|
2014-07-30 05:08:14 +00:00
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config TARGET_PB1X00
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bool "Support pb1x00"
|
2014-10-26 13:14:07 +00:00
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select SUPPORTS_LITTLE_ENDIAN
|
2014-10-26 13:14:07 +00:00
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
|
2015-01-29 01:28:02 +00:00
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select SYS_MIPS_CACHE_INIT_RAM_LOAD
|
2015-12-26 18:55:37 +00:00
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select MIPS_TUNE_4KC
|
2014-07-30 05:08:14 +00:00
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|
|
2016-03-16 08:59:52 +00:00
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|
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config ARCH_ATH79
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bool "Support QCA/Atheros ath79"
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select OF_CONTROL
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select DM
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|
2016-01-28 10:00:10 +00:00
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config MACH_PIC32
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bool "Support Microchip PIC32"
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select OF_CONTROL
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select DM
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|
2016-07-29 14:11:20 +00:00
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config TARGET_XILFPGA
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bool "Support Imagination Xilfpga"
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select OF_CONTROL
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select DM
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select DM_SERIAL
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select DM_GPIO
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select DM_ETH
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select SUPPORTS_LITTLE_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select MIPS_L1_CACHE_SHIFT_4
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help
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|
This supports IMGTEC MIPSfpga platform
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|
2014-07-30 05:08:14 +00:00
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endchoice
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source "board/dbau1x00/Kconfig"
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source "board/imgtec/malta/Kconfig"
|
2016-07-29 14:11:20 +00:00
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source "board/imgtec/xilfpga/Kconfig"
|
2014-07-30 05:08:14 +00:00
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|
source "board/micronas/vct/Kconfig"
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source "board/pb1x00/Kconfig"
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source "board/qemu-mips/Kconfig"
|
2016-03-16 08:59:52 +00:00
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|
|
source "arch/mips/mach-ath79/Kconfig"
|
2016-01-28 10:00:10 +00:00
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|
|
source "arch/mips/mach-pic32/Kconfig"
|
2014-07-30 05:08:14 +00:00
|
|
|
|
2014-10-26 13:14:07 +00:00
|
|
|
if MIPS
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choice
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prompt "Endianness selection"
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help
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|
Some MIPS boards can be configured for either little or big endian
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|
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byte order. These modes require different U-Boot images. In general there
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is one preferred byteorder for a particular system but some systems are
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just as commonly used in the one or the other endianness.
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config SYS_BIG_ENDIAN
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bool "Big endian"
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depends on SUPPORTS_BIG_ENDIAN
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|
|
config SYS_LITTLE_ENDIAN
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|
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bool "Little endian"
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|
depends on SUPPORTS_LITTLE_ENDIAN
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endchoice
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|
2014-10-26 13:14:07 +00:00
|
|
|
choice
|
|
|
|
prompt "CPU selection"
|
|
|
|
default CPU_MIPS32_R2
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|
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|
|
config CPU_MIPS32_R1
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bool "MIPS32 Release 1"
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|
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|
depends on SUPPORTS_CPU_MIPS32_R1
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|
|
|
select 32BIT
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|
|
|
help
|
2016-05-16 09:52:12 +00:00
|
|
|
Choose this option to build an U-Boot for release 1 through 5 of the
|
2014-10-26 13:14:07 +00:00
|
|
|
MIPS32 architecture.
|
|
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|
|
config CPU_MIPS32_R2
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bool "MIPS32 Release 2"
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|
depends on SUPPORTS_CPU_MIPS32_R2
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|
|
|
select 32BIT
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|
|
|
help
|
2016-05-16 09:52:12 +00:00
|
|
|
Choose this option to build an U-Boot for release 2 through 5 of the
|
|
|
|
MIPS32 architecture.
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|
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|
|
config CPU_MIPS32_R6
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|
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bool "MIPS32 Release 6"
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|
|
|
depends on SUPPORTS_CPU_MIPS32_R6
|
|
|
|
select 32BIT
|
|
|
|
help
|
|
|
|
Choose this option to build an U-Boot for release 6 or later of the
|
2014-10-26 13:14:07 +00:00
|
|
|
MIPS32 architecture.
|
|
|
|
|
|
|
|
config CPU_MIPS64_R1
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|
|
|
bool "MIPS64 Release 1"
|
|
|
|
depends on SUPPORTS_CPU_MIPS64_R1
|
|
|
|
select 64BIT
|
|
|
|
help
|
2016-05-16 09:52:12 +00:00
|
|
|
Choose this option to build a kernel for release 1 through 5 of the
|
2014-10-26 13:14:07 +00:00
|
|
|
MIPS64 architecture.
|
|
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|
|
|
|
|
config CPU_MIPS64_R2
|
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|
|
bool "MIPS64 Release 2"
|
|
|
|
depends on SUPPORTS_CPU_MIPS64_R2
|
|
|
|
select 64BIT
|
|
|
|
help
|
2016-05-16 09:52:12 +00:00
|
|
|
Choose this option to build a kernel for release 2 through 5 of the
|
|
|
|
MIPS64 architecture.
|
|
|
|
|
|
|
|
config CPU_MIPS64_R6
|
|
|
|
bool "MIPS64 Release 6"
|
|
|
|
depends on SUPPORTS_CPU_MIPS64_R6
|
|
|
|
select 64BIT
|
|
|
|
help
|
|
|
|
Choose this option to build a kernel for release 6 or later of the
|
2014-10-26 13:14:07 +00:00
|
|
|
MIPS64 architecture.
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
2015-01-14 20:44:13 +00:00
|
|
|
menu "OS boot interface"
|
|
|
|
|
|
|
|
config MIPS_BOOT_CMDLINE_LEGACY
|
|
|
|
bool "Hand over legacy command line to Linux kernel"
|
|
|
|
default y
|
|
|
|
help
|
|
|
|
Enable this option if you want U-Boot to hand over the Yamon-style
|
|
|
|
command line to the kernel. All bootargs will be prepared as argc/argv
|
|
|
|
compatible list. The argument count (argc) is stored in register $a0.
|
|
|
|
The address of the argument list (argv) is stored in register $a1.
|
|
|
|
|
2015-01-14 20:44:13 +00:00
|
|
|
config MIPS_BOOT_ENV_LEGACY
|
|
|
|
bool "Hand over legacy environment to Linux kernel"
|
|
|
|
default y
|
|
|
|
help
|
|
|
|
Enable this option if you want U-Boot to hand over the Yamon-style
|
|
|
|
environment to the kernel. Information like memory size, initrd
|
|
|
|
address and size will be prepared as zero-terminated key/value list.
|
2016-05-04 08:47:31 +00:00
|
|
|
The address of the environment is stored in register $a2.
|
2015-01-14 20:44:13 +00:00
|
|
|
|
2015-01-14 20:44:13 +00:00
|
|
|
config MIPS_BOOT_FDT
|
2015-02-22 15:58:30 +00:00
|
|
|
bool "Hand over a flattened device tree to Linux kernel"
|
2015-01-14 20:44:13 +00:00
|
|
|
default n
|
|
|
|
help
|
|
|
|
Enable this option if you want U-Boot to hand over a flattened
|
2015-02-22 15:58:30 +00:00
|
|
|
device tree to the kernel. According to UHI register $a0 will be set
|
|
|
|
to -2 and the FDT address is stored in $a1.
|
2015-01-14 20:44:13 +00:00
|
|
|
|
2015-01-14 20:44:13 +00:00
|
|
|
endmenu
|
|
|
|
|
2014-10-26 13:14:07 +00:00
|
|
|
config SUPPORTS_BIG_ENDIAN
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SUPPORTS_LITTLE_ENDIAN
|
|
|
|
bool
|
|
|
|
|
2014-10-26 13:14:07 +00:00
|
|
|
config SUPPORTS_CPU_MIPS32_R1
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SUPPORTS_CPU_MIPS32_R2
|
|
|
|
bool
|
|
|
|
|
2016-05-16 09:52:12 +00:00
|
|
|
config SUPPORTS_CPU_MIPS32_R6
|
|
|
|
bool
|
|
|
|
|
2014-10-26 13:14:07 +00:00
|
|
|
config SUPPORTS_CPU_MIPS64_R1
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SUPPORTS_CPU_MIPS64_R2
|
|
|
|
bool
|
|
|
|
|
2016-05-16 09:52:12 +00:00
|
|
|
config SUPPORTS_CPU_MIPS64_R6
|
|
|
|
bool
|
|
|
|
|
2015-01-18 20:59:35 +00:00
|
|
|
config CPU_MIPS32
|
|
|
|
bool
|
2016-05-16 09:52:12 +00:00
|
|
|
default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
|
2015-01-18 20:59:35 +00:00
|
|
|
|
|
|
|
config CPU_MIPS64
|
|
|
|
bool
|
2016-05-16 09:52:12 +00:00
|
|
|
default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
|
2015-01-18 20:59:35 +00:00
|
|
|
|
2015-12-26 18:55:37 +00:00
|
|
|
config MIPS_TUNE_4KC
|
|
|
|
bool
|
|
|
|
|
|
|
|
config MIPS_TUNE_14KC
|
|
|
|
bool
|
|
|
|
|
|
|
|
config MIPS_TUNE_24KC
|
|
|
|
bool
|
|
|
|
|
2016-05-27 13:39:39 +00:00
|
|
|
config MIPS_TUNE_34KC
|
|
|
|
bool
|
|
|
|
|
2016-05-06 18:10:33 +00:00
|
|
|
config MIPS_TUNE_74KC
|
|
|
|
bool
|
|
|
|
|
2014-10-26 13:14:07 +00:00
|
|
|
config 32BIT
|
|
|
|
bool
|
|
|
|
|
|
|
|
config 64BIT
|
|
|
|
bool
|
|
|
|
|
2015-01-18 21:00:18 +00:00
|
|
|
config SWAP_IO_SPACE
|
|
|
|
bool
|
|
|
|
|
2015-01-29 01:28:02 +00:00
|
|
|
config SYS_MIPS_CACHE_INIT_RAM_LOAD
|
|
|
|
bool
|
|
|
|
|
2016-05-27 13:28:04 +00:00
|
|
|
config SYS_DCACHE_SIZE
|
|
|
|
int
|
|
|
|
default 0
|
|
|
|
help
|
|
|
|
The total size of the L1 Dcache, if known at compile time.
|
|
|
|
|
2016-05-27 13:28:05 +00:00
|
|
|
config SYS_DCACHE_LINE_SIZE
|
2016-06-09 12:09:52 +00:00
|
|
|
int
|
2016-05-27 13:28:05 +00:00
|
|
|
default 0
|
|
|
|
help
|
|
|
|
The size of L1 Dcache lines, if known at compile time.
|
|
|
|
|
2016-05-27 13:28:04 +00:00
|
|
|
config SYS_ICACHE_SIZE
|
|
|
|
int
|
|
|
|
default 0
|
|
|
|
help
|
|
|
|
The total size of the L1 ICache, if known at compile time.
|
|
|
|
|
2016-05-27 13:28:05 +00:00
|
|
|
config SYS_ICACHE_LINE_SIZE
|
2016-05-27 13:28:04 +00:00
|
|
|
int
|
|
|
|
default 0
|
|
|
|
help
|
2016-05-27 13:28:05 +00:00
|
|
|
The size of L1 Icache lines, if known at compile time.
|
2016-05-27 13:28:04 +00:00
|
|
|
|
|
|
|
config SYS_CACHE_SIZE_AUTO
|
|
|
|
def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
|
2016-05-27 13:28:05 +00:00
|
|
|
SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
|
2016-05-27 13:28:04 +00:00
|
|
|
help
|
|
|
|
Select this (or let it be auto-selected by not defining any cache
|
|
|
|
sizes) in order to allow U-Boot to automatically detect the sizes
|
|
|
|
of caches at runtime. This has a small cost in code size & runtime
|
|
|
|
so if you know the cache configuration for your system at compile
|
|
|
|
time it would be beneficial to configure it.
|
|
|
|
|
2016-01-09 16:32:50 +00:00
|
|
|
config MIPS_L1_CACHE_SHIFT_4
|
|
|
|
bool
|
|
|
|
|
|
|
|
config MIPS_L1_CACHE_SHIFT_5
|
|
|
|
bool
|
|
|
|
|
|
|
|
config MIPS_L1_CACHE_SHIFT_6
|
|
|
|
bool
|
|
|
|
|
|
|
|
config MIPS_L1_CACHE_SHIFT_7
|
|
|
|
bool
|
|
|
|
|
|
|
|
config MIPS_L1_CACHE_SHIFT
|
|
|
|
int
|
|
|
|
default "7" if MIPS_L1_CACHE_SHIFT_7
|
|
|
|
default "6" if MIPS_L1_CACHE_SHIFT_6
|
|
|
|
default "5" if MIPS_L1_CACHE_SHIFT_5
|
|
|
|
default "4" if MIPS_L1_CACHE_SHIFT_4
|
|
|
|
default "5"
|
|
|
|
|
2016-01-29 13:54:52 +00:00
|
|
|
config DYNAMIC_IO_PORT_BASE
|
|
|
|
bool
|
|
|
|
|
2014-10-26 13:14:07 +00:00
|
|
|
endif
|
|
|
|
|
2014-07-30 05:08:14 +00:00
|
|
|
endmenu
|