2014-09-04 22:27:35 +00:00
|
|
|
#include <dt-bindings/clock/tegra124-car.h>
|
2014-06-12 05:29:52 +00:00
|
|
|
#include <dt-bindings/gpio/tegra-gpio.h>
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
|
2014-01-24 19:46:17 +00:00
|
|
|
#include "skeleton.dtsi"
|
|
|
|
|
|
|
|
/ {
|
|
|
|
compatible = "nvidia,tegra124";
|
|
|
|
|
|
|
|
tegra_car: clock@60006000 {
|
|
|
|
compatible = "nvidia,tegra124-car";
|
|
|
|
reg = <0x60006000 0x1000>;
|
|
|
|
#clock-cells = <1>;
|
|
|
|
};
|
|
|
|
|
|
|
|
apbdma: dma@60020000 {
|
|
|
|
compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
|
|
|
|
reg = <0x60020000 0x1400>;
|
|
|
|
interrupts = <0 104 0x04
|
|
|
|
0 105 0x04
|
|
|
|
0 106 0x04
|
|
|
|
0 107 0x04
|
|
|
|
0 108 0x04
|
|
|
|
0 109 0x04
|
|
|
|
0 110 0x04
|
|
|
|
0 111 0x04
|
|
|
|
0 112 0x04
|
|
|
|
0 113 0x04
|
|
|
|
0 114 0x04
|
|
|
|
0 115 0x04
|
|
|
|
0 116 0x04
|
|
|
|
0 117 0x04
|
|
|
|
0 118 0x04
|
|
|
|
0 119 0x04
|
|
|
|
0 128 0x04
|
|
|
|
0 129 0x04
|
|
|
|
0 130 0x04
|
|
|
|
0 131 0x04
|
|
|
|
0 132 0x04
|
|
|
|
0 133 0x04
|
|
|
|
0 134 0x04
|
|
|
|
0 135 0x04
|
|
|
|
0 136 0x04
|
|
|
|
0 137 0x04
|
|
|
|
0 138 0x04
|
|
|
|
0 139 0x04
|
|
|
|
0 140 0x04
|
|
|
|
0 141 0x04
|
|
|
|
0 142 0x04
|
|
|
|
0 143 0x04>;
|
|
|
|
};
|
|
|
|
|
|
|
|
gpio: gpio@6000d000 {
|
|
|
|
compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
|
|
|
|
reg = <0x6000d000 0x1000>;
|
2014-06-12 05:29:52 +00:00
|
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
2014-01-24 19:46:17 +00:00
|
|
|
#gpio-cells = <2>;
|
|
|
|
gpio-controller;
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c@7000c000 {
|
|
|
|
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
|
|
|
reg = <0x7000c000 0x100>;
|
|
|
|
interrupts = <0 38 0x04>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
clocks = <&tegra_car 12>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c@7000c400 {
|
|
|
|
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
|
|
|
reg = <0x7000c400 0x100>;
|
|
|
|
interrupts = <0 84 0x04>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
clocks = <&tegra_car 54>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c@7000c500 {
|
|
|
|
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
|
|
|
reg = <0x7000c500 0x100>;
|
|
|
|
interrupts = <0 92 0x04>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
clocks = <&tegra_car 67>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c@7000c700 {
|
|
|
|
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
|
|
|
reg = <0x7000c700 0x100>;
|
|
|
|
interrupts = <0 120 0x04>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
clocks = <&tegra_car 103>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c@7000d000 {
|
|
|
|
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
|
|
|
reg = <0x7000d000 0x100>;
|
|
|
|
interrupts = <0 53 0x04>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
clocks = <&tegra_car 47>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c@7000d100 {
|
|
|
|
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
|
|
|
reg = <0x7000d100 0x100>;
|
|
|
|
interrupts = <0 53 0x04>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
clocks = <&tegra_car 47>;
|
|
|
|
status = "disabled";
|
2014-09-04 22:27:35 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
uarta: serial@70006000 {
|
|
|
|
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
|
|
|
reg = <0x70006000 0x40>;
|
|
|
|
reg-shift = <2>;
|
|
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&tegra_car TEGRA124_CLK_UARTA>;
|
|
|
|
resets = <&tegra_car 6>;
|
|
|
|
reset-names = "serial";
|
|
|
|
dmas = <&apbdma 8>, <&apbdma 8>;
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
uartb: serial@70006040 {
|
|
|
|
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
|
|
|
reg = <0x70006040 0x40>;
|
|
|
|
reg-shift = <2>;
|
|
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&tegra_car TEGRA124_CLK_UARTB>;
|
|
|
|
resets = <&tegra_car 7>;
|
|
|
|
reset-names = "serial";
|
|
|
|
dmas = <&apbdma 9>, <&apbdma 9>;
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
uartc: serial@70006200 {
|
|
|
|
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
|
|
|
reg = <0x70006200 0x40>;
|
|
|
|
reg-shift = <2>;
|
|
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&tegra_car TEGRA124_CLK_UARTC>;
|
|
|
|
resets = <&tegra_car 55>;
|
|
|
|
reset-names = "serial";
|
|
|
|
dmas = <&apbdma 10>, <&apbdma 10>;
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
uartd: serial@70006300 {
|
|
|
|
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
|
|
|
reg = <0x70006300 0x40>;
|
|
|
|
reg-shift = <2>;
|
|
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&tegra_car TEGRA124_CLK_UARTD>;
|
|
|
|
resets = <&tegra_car 65>;
|
|
|
|
reset-names = "serial";
|
|
|
|
dmas = <&apbdma 19>, <&apbdma 19>;
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
uarte: serial@70006400 {
|
|
|
|
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
|
|
|
reg = <0x70006400 0x40>;
|
|
|
|
reg-shift = <2>;
|
|
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&tegra_car TEGRA124_CLK_UARTE>;
|
|
|
|
resets = <&tegra_car 66>;
|
|
|
|
reset-names = "serial";
|
|
|
|
dmas = <&apbdma 20>, <&apbdma 20>;
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
status = "disabled";
|
2014-01-24 19:46:17 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
spi@7000d400 {
|
|
|
|
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
|
|
reg = <0x7000d400 0x200>;
|
|
|
|
interrupts = <0 59 0x04>;
|
|
|
|
nvidia,dma-request-selector = <&apbdma 15>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
clocks = <&tegra_car 41>;
|
|
|
|
};
|
|
|
|
|
|
|
|
spi@7000d600 {
|
|
|
|
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
|
|
reg = <0x7000d600 0x200>;
|
|
|
|
interrupts = <0 82 0x04>;
|
|
|
|
nvidia,dma-request-selector = <&apbdma 16>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
clocks = <&tegra_car 44>;
|
|
|
|
};
|
|
|
|
|
|
|
|
spi@7000d800 {
|
|
|
|
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
|
|
reg = <0x7000d800 0x200>;
|
|
|
|
interrupts = <0 83 0x04>;
|
|
|
|
nvidia,dma-request-selector = <&apbdma 17>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
clocks = <&tegra_car 46>;
|
|
|
|
};
|
|
|
|
|
|
|
|
spi@7000da00 {
|
|
|
|
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
|
|
reg = <0x7000da00 0x200>;
|
|
|
|
interrupts = <0 93 0x04>;
|
|
|
|
nvidia,dma-request-selector = <&apbdma 18>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
clocks = <&tegra_car 68>;
|
|
|
|
};
|
|
|
|
|
|
|
|
spi@7000dc00 {
|
|
|
|
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
|
|
reg = <0x7000dc00 0x200>;
|
|
|
|
interrupts = <0 94 0x04>;
|
|
|
|
nvidia,dma-request-selector = <&apbdma 27>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
clocks = <&tegra_car 104>;
|
|
|
|
};
|
|
|
|
|
|
|
|
spi@7000de00 {
|
|
|
|
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
|
|
reg = <0x7000de00 0x200>;
|
|
|
|
interrupts = <0 79 0x04>;
|
|
|
|
nvidia,dma-request-selector = <&apbdma 28>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
clocks = <&tegra_car 105>;
|
|
|
|
};
|
|
|
|
|
|
|
|
sdhci@700b0000 {
|
|
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
|
|
reg = <0x700b0000 0x200>;
|
|
|
|
interrupts = <0 14 0x04>;
|
|
|
|
clocks = <&tegra_car 14>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
sdhci@700b0200 {
|
|
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
|
|
reg = <0x700b0200 0x200>;
|
|
|
|
interrupts = <0 15 0x04>;
|
|
|
|
clocks = <&tegra_car 9>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
sdhci@700b0400 {
|
|
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
|
|
reg = <0x700b0400 0x200>;
|
|
|
|
interrupts = <0 19 0x04>;
|
|
|
|
clocks = <&tegra_car 69>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
sdhci@700b0600 {
|
|
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
|
|
reg = <0x700b0600 0x200>;
|
|
|
|
interrupts = <0 31 0x04>;
|
|
|
|
clocks = <&tegra_car 15>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
usb@7d000000 {
|
|
|
|
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
|
|
|
|
reg = <0x7d000000 0x4000>;
|
|
|
|
interrupts = < 52 >;
|
|
|
|
phy_type = "utmi";
|
|
|
|
clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
usb@7d004000 {
|
|
|
|
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
|
|
|
|
reg = <0x7d004000 0x4000>;
|
|
|
|
interrupts = < 53 >;
|
|
|
|
phy_type = "hsic";
|
|
|
|
clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
usb@7d008000 {
|
|
|
|
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
|
|
|
|
reg = <0x7d008000 0x4000>;
|
|
|
|
interrupts = < 129 >;
|
|
|
|
phy_type = "utmi";
|
|
|
|
clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
};
|