2012-09-13 03:18:20 +00:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2012 Freescale Semiconductor, Inc.
|
|
|
|
*
|
|
|
|
* Configuration settings for the Freescale i.MX6Q SabreSD board.
|
|
|
|
*
|
2013-07-08 07:37:19 +00:00
|
|
|
* SPDX-License-Identifier: GPL-2.0+
|
2012-09-13 03:18:20 +00:00
|
|
|
*/
|
|
|
|
|
2017-06-01 15:59:52 +00:00
|
|
|
#ifndef __MX6SABRESD_CONFIG_H
|
|
|
|
#define __MX6SABRESD_CONFIG_H
|
2012-09-13 03:18:20 +00:00
|
|
|
|
2014-11-12 22:27:44 +00:00
|
|
|
#ifdef CONFIG_SPL
|
|
|
|
#include "imx6_spl.h"
|
|
|
|
#endif
|
|
|
|
|
2012-09-13 03:18:20 +00:00
|
|
|
#define CONFIG_MACH_TYPE 3980
|
2012-09-24 08:09:32 +00:00
|
|
|
#define CONFIG_MXC_UART_BASE UART1_BASE
|
2016-10-18 02:12:39 +00:00
|
|
|
#define CONSOLE_DEV "ttymxc0"
|
2012-09-13 03:18:20 +00:00
|
|
|
|
2014-01-06 15:27:20 +00:00
|
|
|
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
|
|
|
|
2013-06-04 07:00:15 +00:00
|
|
|
#include "mx6sabre_common.h"
|
2012-09-26 11:37:01 +00:00
|
|
|
|
2016-10-11 14:09:27 +00:00
|
|
|
/* Falcon Mode */
|
2017-01-21 00:55:53 +00:00
|
|
|
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
|
|
|
|
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
|
2016-10-11 14:09:27 +00:00
|
|
|
#define CONFIG_CMD_SPL
|
|
|
|
#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
|
|
|
|
#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
|
|
|
|
|
|
|
|
/* Falcon Mode - MMC support: args@1MB kernel@2MB */
|
|
|
|
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
|
|
|
|
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
|
|
|
|
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
|
|
|
|
|
2012-12-30 14:14:59 +00:00
|
|
|
#define CONFIG_SYS_FSL_USDHC_NUM 3
|
|
|
|
#if defined(CONFIG_ENV_IS_IN_MMC)
|
2013-01-10 09:00:53 +00:00
|
|
|
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
|
2012-12-30 14:14:59 +00:00
|
|
|
#endif
|
|
|
|
|
2014-03-23 21:45:41 +00:00
|
|
|
#define CONFIG_CMD_PCI
|
|
|
|
#ifdef CONFIG_CMD_PCI
|
|
|
|
#define CONFIG_PCI_SCAN_SHOW
|
|
|
|
#define CONFIG_PCIE_IMX
|
|
|
|
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
|
|
|
|
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
|
|
|
|
#endif
|
|
|
|
|
2014-05-09 16:15:42 +00:00
|
|
|
/* I2C Configs */
|
|
|
|
#define CONFIG_SYS_I2C
|
|
|
|
#define CONFIG_SYS_I2C_MXC
|
2015-09-21 20:43:38 +00:00
|
|
|
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
|
|
|
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
2015-03-20 17:20:40 +00:00
|
|
|
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
2014-05-09 16:15:42 +00:00
|
|
|
#define CONFIG_SYS_I2C_SPEED 100000
|
|
|
|
|
|
|
|
/* PMIC */
|
|
|
|
#define CONFIG_POWER
|
|
|
|
#define CONFIG_POWER_I2C
|
|
|
|
#define CONFIG_POWER_PFUZE100
|
|
|
|
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
|
|
|
|
|
2014-12-02 01:55:27 +00:00
|
|
|
/* USB Configs */
|
|
|
|
#ifdef CONFIG_CMD_USB
|
|
|
|
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
|
|
|
#define CONFIG_USB_HOST_ETHER
|
|
|
|
#define CONFIG_USB_ETHER_ASIX
|
|
|
|
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
|
|
|
#define CONFIG_MXC_USB_FLAGS 0
|
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
|
|
|
|
#endif
|
|
|
|
|
2017-06-01 15:59:52 +00:00
|
|
|
#endif /* __MX6SABRESD_CONFIG_H */
|