Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-19 11:18:28 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/board/prodrive/alpr/init.S

54 lines
1.8 KiB
ArmAsm
Raw Normal View History

Add initial support for the ALPR board from Prodrive NAND needs some additional testing Patch by Heiko Schocher, 15 Aug 2006
2006-08-15 12:22:35 +00:00
/*
Update ALPR code (NAND support working now) Patch by Stefan Roese, 07 Oct 2006
2006-10-07 09:35:25 +00:00
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-07-08 07:37:19 +00:00
* SPDX-License-Identifier: GPL-2.0+
Update ALPR code (NAND support working now) Patch by Stefan Roese, 07 Oct 2006
2006-10-07 09:35:25 +00:00
*/
Add initial support for the ALPR board from Prodrive NAND needs some additional testing Patch by Heiko Schocher, 15 Aug 2006
2006-08-15 12:22:35 +00:00
Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-26 12:34:52 +00:00
#include <asm-offsets.h>
Add initial support for the ALPR board from Prodrive NAND needs some additional testing Patch by Heiko Schocher, 15 Aug 2006
2006-08-15 12:22:35 +00:00
#include <ppc_asm.tmpl>
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
#include <asm/mmu.h>
Add initial support for the ALPR board from Prodrive NAND needs some additional testing Patch by Heiko Schocher, 15 Aug 2006
2006-08-15 12:22:35 +00:00
#include <config.h>
ppc4xx: Use common NS16550 driver for PPC4xx UART This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-20 14:05:31 +00:00
#include <asm/ppc4xx.h>
Add initial support for the ALPR board from Prodrive NAND needs some additional testing Patch by Heiko Schocher, 15 Aug 2006
2006-08-15 12:22:35 +00:00
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
Update ALPR code (NAND support working now) Patch by Stefan Roese, 07 Oct 2006
2006-10-07 09:35:25 +00:00
.section .bootpg,"ax"
.globl tlbtab
Add initial support for the ALPR board from Prodrive NAND needs some additional testing Patch by Heiko Schocher, 15 Aug 2006
2006-08-15 12:22:35 +00:00
tlbtab:
Update ALPR code (NAND support working now) Patch by Stefan Roese, 07 Oct 2006
2006-10-07 09:35:25 +00:00
tlbtab_start
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG )
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
ppc4xx: Enable cache support on the ALPR board Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
2008-03-17 08:27:56 +00:00
#ifdef CONFIG_4xx_DCACHE
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G)
ppc4xx: Enable cache support on the ALPR board Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
2008-03-17 08:27:56 +00:00
#else
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG)
ppc4xx: Enable cache support on the ALPR board Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
2008-03-17 08:27:56 +00:00
#endif
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
ppc4xx: Enable cache support on the ALPR board Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
2008-03-17 08:27:56 +00:00
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
ppc4xx: Enable cache support on the ALPR board Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
2008-03-17 08:27:56 +00:00
#endif
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
Update ALPR code (NAND support working now) Patch by Stefan Roese, 07 Oct 2006
2006-10-07 09:35:25 +00:00
/* PCI */
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG)
Update ALPR code (NAND support working now) Patch by Stefan Roese, 07 Oct 2006
2006-10-07 09:35:25 +00:00
/* NAND */
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG)
Update ALPR code (NAND support working now) Patch by Stefan Roese, 07 Oct 2006
2006-10-07 09:35:25 +00:00
tlbtab_end
Reference in a new issue Copy permalink