2005-07-28 15:08:46 +00:00
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#
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2006-09-01 17:49:50 +00:00
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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2006-10-08 22:42:01 +00:00
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#
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2005-07-28 15:08:46 +00:00
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# Copyright 2004 Freescale Semiconductor, Inc.
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#
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2013-07-08 07:37:19 +00:00
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# SPDX-License-Identifier: GPL-2.0+
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2005-07-28 15:08:46 +00:00
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#
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2012-12-06 13:33:17 +00:00
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MINIMAL=
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_INIT_MINIMAL
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MINIMAL=y
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endif
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endif
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2013-10-17 08:35:04 +00:00
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extra-y = start.o
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2005-07-28 15:08:46 +00:00
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2012-12-06 13:33:17 +00:00
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ifdef MINIMAL
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2013-10-17 08:35:04 +00:00
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obj-y += spl_minimal.o
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2012-12-06 13:33:17 +00:00
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else
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2013-10-17 08:35:04 +00:00
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obj-y += traps.o
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obj-y += cpu.o
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obj-y += cpu_init.o
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obj-y += speed.o
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obj-y += interrupts.o
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obj-y += ecc.o
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obj-$(CONFIG_QE) += qe_io.o
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obj-$(CONFIG_FSL_SERDES) += serdes.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_PCIE) += pcie.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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2008-03-24 14:40:27 +00:00
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2012-05-25 14:14:46 +00:00
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# Stub implementations of cache management functions for USB
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2013-10-17 08:35:04 +00:00
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obj-y += cache.o
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2012-05-25 14:14:46 +00:00
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2011-08-26 18:32:44 +00:00
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ifdef CONFIG_FSL_DDR2
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2013-10-17 08:35:04 +00:00
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obj-$(CONFIG_MPC8349) += ddr-gen2.o
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SRCS += $(obj)ddr-gen2.c
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2011-08-26 18:32:44 +00:00
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else
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2013-10-17 08:35:04 +00:00
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obj-y += spd_sdram.o
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2011-08-26 18:32:44 +00:00
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endif
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2013-10-17 08:35:04 +00:00
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obj-$(CONFIG_FSL_DDR2) += law.o
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2011-08-26 18:32:44 +00:00
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2012-12-06 13:33:17 +00:00
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endif # not minimal
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2011-08-26 18:32:44 +00:00
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$(obj)ddr-gen1.c:
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ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c
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$(obj)ddr-gen2.c:
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ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c
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$(obj)ddr-gen3.c:
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ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c
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