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u-boot/arch/arm/mach-k3/arm64-mmu.c

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armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
// SPDX-License-Identifier: GPL-2.0+
/*
* K3: ARM64 MMU setup
*
armv8: K3: j7200: Add custom MMU support The A72 U-Boot code can load and boot a number of the available R5FSS Cores on the J7200 SoC. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. The J7200 SoC has less number of remote processors compared to J721E, so use less memory for the remote processors. So, a separate table based on the current J721E table is added for J7200 SoCs, and selected using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol. Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-17 23:15:09 +00:00
* Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
* Lokesh Vutla <lokeshvutla@ti.com>
armv8: K3: j7200: Add custom MMU support The A72 U-Boot code can load and boot a number of the available R5FSS Cores on the J7200 SoC. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. The J7200 SoC has less number of remote processors compared to J721E, so use less memory for the remote processors. So, a separate table based on the current J721E table is added for J7200 SoCs, and selected using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol. Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-17 23:15:09 +00:00
* Suman Anna <s-anna@ti.com>
arm64: zynqmp: Move SoC sources to mach-zynqmp Similar changes was done for Zynq in past and this patch just follow this pattern to separate cpu code from SoC code. Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/* And also fix references to these files. Based on "ARM: zynq: move SoC sources to mach-zynq" (sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-17 07:22:43 +00:00
* (This file is derived from arch/arm/mach-zynqmp/cpu.c)
armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
*
*/
#include <common.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
armv8: K3: j721e: Add custom MMU support The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. A separate table based on the current AM65x table is added for J721E SoCs, since the number of remote processors and their DDR usage will be different between the two SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:48 +00:00
#ifdef CONFIG_SOC_K3_AM6
armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
armv8: K3: am65x: Update DDR address regions in MMU table The A53 U-Boot code can load and boot the MCU domain R5F cores (either a single core in LockStep mode or 2 cores in Split mode) to achieve various early system functionalities. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code loaded by U-Boot. These regions are currently limited to 0xa0000000 to 0xa2100000 as per the DDR carveouts assigned for these R5F cores in the overall DDR memory map. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-04 10:31:49 +00:00
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
/* ToDo: Add 64bit IO */
struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
armv8: K3: am65x: Update DDR address regions in MMU table The A53 U-Boot code can load and boot the MCU domain R5F cores (either a single core in LockStep mode or 2 cores in Split mode) to achieve various early system functionalities. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code loaded by U-Boot. These regions are currently limited to 0xa0000000 to 0xa2100000 as per the DDR carveouts assigned for these R5F cores in the overall DDR memory map. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-04 10:31:49 +00:00
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
.size = 0x02100000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa2100000UL,
.phys = 0xa2100000UL,
.size = 0x5df00000UL,
armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
ARM: mach-k3: arm64-mmu: map 64bit FSS MMIO space in A53 MMU Populate address mapping entries in A53 MMU for 4 GB of MMIO space reserved for providing MMIO access to multiple flash devices through OSPI/HBMC IPs within FSS. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-02-04 05:39:49 +00:00
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = am654_mem_map;
armv8: K3: j721e: Add custom MMU support The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. A separate table based on the current AM65x table is added for J721E SoCs, since the number of remote processors and their DDR usage will be different between the two SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:48 +00:00
#endif /* CONFIG_SOC_K3_AM6 */
#ifdef CONFIG_SOC_K3_J721E
armv8: K3: j7200: Add custom MMU support The A72 U-Boot code can load and boot a number of the available R5FSS Cores on the J7200 SoC. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. The J7200 SoC has less number of remote processors compared to J721E, so use less memory for the remote processors. So, a separate table based on the current J721E table is added for J7200 SoCs, and selected using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol. Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-17 23:15:09 +00:00
#ifdef CONFIG_TARGET_J721E_A72_EVM
armv8: K3: j721e: Add custom MMU support The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. A separate table based on the current AM65x table is added for J721E SoCs, since the number of remote processors and their DDR usage will be different between the two SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:48 +00:00
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
armv8: K3: j721e: Add DSP internal memory regions in MMU table The A72 U-Boot code supports early load and boot of a number of remote processors including the C66_0 and C66_1 DSPs. The current code supports only loading into the DDR regions which were already given the appropriate memory attributes. The C66 DSPs also have L1 and L2 internal memory regions that can behave as normal-memories. Add a new entry to the J721E MMU table covering these regions with the appropriate memory attributes to allow the A72 U-Boot code to support loading directly into these memory regions. Signed-off-by: Suman Anna <s-anna@ti.com>
2020-03-10 21:05:55 +00:00
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
armv8: K3: j721e: Add custom MMU support The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. A separate table based on the current AM65x table is added for J721E SoCs, since the number of remote processors and their DDR usage will be different between the two SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:48 +00:00
/* ToDo: Add 64bit IO */
struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
armv8: K3: j721e: Updated ddr address regions in MMU table The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. In order to view the code loaded by the U-Boot by remote cores, U-Boot should configure the memory region with right memory attributes. Right now U-Boot carves out a memory region which is not sufficient for all the images to be loaded. So, increase this carve out region by 256MB. Signed-off-by: Kedar Chitnis <kedarc@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-04 10:31:50 +00:00
.size = 0x1bc00000UL,
armv8: K3: j721e: Add custom MMU support The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. A separate table based on the current AM65x table is added for J721E SoCs, since the number of remote processors and their DDR usage will be different between the two SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:48 +00:00
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_NON_SHARE
}, {
armv8: K3: j721e: Updated ddr address regions in MMU table The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. In order to view the code loaded by the U-Boot by remote cores, U-Boot should configure the memory region with right memory attributes. Right now U-Boot carves out a memory region which is not sufficient for all the images to be loaded. So, increase this carve out region by 256MB. Signed-off-by: Kedar Chitnis <kedarc@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-04 10:31:50 +00:00
.virt = 0xbbc00000UL,
.phys = 0xbbc00000UL,
.size = 0x44400000UL,
armv8: K3: j721e: Add custom MMU support The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. A separate table based on the current AM65x table is added for J721E SoCs, since the number of remote processors and their DDR usage will be different between the two SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:48 +00:00
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
armv8: K3: j721e: Add DSP internal memory regions in MMU table The A72 U-Boot code supports early load and boot of a number of remote processors including the C66_0 and C66_1 DSPs. The current code supports only loading into the DDR regions which were already given the appropriate memory attributes. The C66 DSPs also have L1 and L2 internal memory regions that can behave as normal-memories. Add a new entry to the J721E MMU table covering these regions with the appropriate memory attributes to allow the A72 U-Boot code to support loading directly into these memory regions. Signed-off-by: Suman Anna <s-anna@ti.com>
2020-03-10 21:05:55 +00:00
}, {
.virt = 0x4d80000000UL,
.phys = 0x4d80000000UL,
.size = 0x0002000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_INNER_SHARE
armv8: K3: j721e: Add custom MMU support The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. A separate table based on the current AM65x table is added for J721E SoCs, since the number of remote processors and their DDR usage will be different between the two SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:48 +00:00
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = j721e_mem_map;
armv8: K3: j7200: Add custom MMU support The A72 U-Boot code can load and boot a number of the available R5FSS Cores on the J7200 SoC. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. The J7200 SoC has less number of remote processors compared to J721E, so use less memory for the remote processors. So, a separate table based on the current J721E table is added for J7200 SoCs, and selected using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol. Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-17 23:15:09 +00:00
#endif /* CONFIG_TARGET_J721E_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
/* ToDo: Add 64bit IO */
struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
.size = 0x04800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_NON_SHARE
}, {
.virt = 0xa4800000UL,
.phys = 0xa4800000UL,
.size = 0x5b800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = j7200_mem_map;
#endif /* CONFIG_TARGET_J7200_A72_EVM */
armv8: K3: j721e: Add custom MMU support The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. A separate table based on the current AM65x table is added for J721E SoCs, since the number of remote processors and their DDR usage will be different between the two SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:48 +00:00
#endif /* CONFIG_SOC_K3_J721E */
armv8: mach-k3: am642: Add custom MMU support Change the memory attributes for the DDR regions used by the remote processors on AM65x so that the cores can see and execute the proper code. A separate table based on the previous K3 SoCs is introduced since the number of remote processors and their DDR usage is different between the SoC families. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:39 +00:00
arm: K3: Add basic support for J721S2 SoC definition Add basic support for J721S2 SoC definition Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
2022-01-25 15:26:31 +00:00
#ifdef CONFIG_SOC_K3_J721S2
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
/* ToDo: Add 64bit IO */
struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = j721s2_mem_map;
#endif /* CONFIG_SOC_K3_J721S2 */
arm: mach-k3: Introduce the basic files to support AM62 The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC architecture platform, providing ultra-low-power modes, dual display, multi-sensor edge compute, security and other BOM-saving integration. The AM62 SoC targets broad market to enable applications such as Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building Automation, Appliances and more. Some highlights of this SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Pin-to-pin compatible options for single and quad core are available. * Cortex-M4F for general-purpose or safety usage. * Dual display support, providing 24-bit RBG parallel interface and OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display resolution. * Selectable GPUsupport, up to 8GFLOPS, providing better user experience in 3D graphic display case and Android. * PRU(Programmable Realtime Unit) support for customized programmable interfaces/IOs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized System Controller for Security, Power, and Resource Management. * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, enabling battery powered system design. AM625 is the first device of the family. Add DT bindings for the same. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Gowtham Tammana <g-tammana@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-25 08:08:42 +00:00
#if (CONFIG_IS_ENABLED(SOC_K3_AM642) || CONFIG_IS_ENABLED(SOC_K3_AM625))
armv8: mach-k3: am642: Add custom MMU support Change the memory attributes for the DDR regions used by the remote processors on AM65x so that the cores can see and execute the proper code. A separate table based on the previous K3 SoCs is introduced since the number of remote processors and their DDR usage is different between the SoC families. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:39 +00:00
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
/* ToDo: Add 64bit IO */
struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = am64_mem_map;
arm: mach-k3: Introduce the basic files to support AM62 The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC architecture platform, providing ultra-low-power modes, dual display, multi-sensor edge compute, security and other BOM-saving integration. The AM62 SoC targets broad market to enable applications such as Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building Automation, Appliances and more. Some highlights of this SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Pin-to-pin compatible options for single and quad core are available. * Cortex-M4F for general-purpose or safety usage. * Dual display support, providing 24-bit RBG parallel interface and OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display resolution. * Selectable GPUsupport, up to 8GFLOPS, providing better user experience in 3D graphic display case and Android. * PRU(Programmable Realtime Unit) support for customized programmable interfaces/IOs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized System Controller for Security, Power, and Resource Management. * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, enabling battery powered system design. AM625 is the first device of the family. Add DT bindings for the same. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Gowtham Tammana <g-tammana@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-25 08:08:42 +00:00
#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 */
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