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u-boot/drivers/clk/sunxi/Makefile

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clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
#
# Copyright (C) 2018 Amarula Solutions.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
clk: sunxi: Add a dummy clock driver for the RTC The 32kHz clock ("LOSC") on sunxi SoCs is provided by the RTC. It is used, among other things, by the XHCI controller in the H6. To be able to call clk_get_bulk() on the XHCI controller, some device needs to provide all referenced clocks. Since LOSC is a fixed-rate always-on clock, implementation is trivial. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-02-08 05:57:19 +00:00
obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o
clk: sunxi: implement clock driver for suniv f1c100s The f1c100s has a clock tree similar to those of other sunxi parts. Add support for it. Signed-off-by: George Hilliard <thirtythreeforty@gmail.com> Signed-off-by: Yifan Gu <me@yifangu.com> Acked-by: Sean Anderson <seanga2@gmail.com> [Andre: add PIO and I2C] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-25 23:16:23 +00:00
obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f1c100s.o
clk: sunxi: Add Allwinner A10/A20 CLK driver Add initial clock driver for Allwinner A10/A20. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-02 11:22:37 +00:00
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
clk: sunxi: Add Allwinner A10s/A13 CLK driver Add initial clock driver for Allwinner A10s/A13. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10s/A13, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10s/A13, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-02 14:24:26 +00:00
obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
clk: sunxi: Add Allwinner A31 CLK driver Add initial clock driver for Allwinner A31. - Implement USB ahb1 and USB clocks via ccu_clk_gate table for A31, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB ahb1 and USB resets via ccu_reset table for A31, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-02 17:45:34 +00:00
obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
clk: sunxi: Add drivers for A31 and H6 PRCM CCUs Add a driver so the clocks/resets for these peripherals (especially I2C, RSB, and UART) can be enabled using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-12 14:47:25 +00:00
obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
clk: sunxi: Add Allwinner A23/A33 CLK driver Add initial clock driver for Allwinner A23/A33. - Implement USB bus and USB clocks via ccu_clk_gate table for A23/A33, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A23/A33, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-02 17:55:03 +00:00
obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
clk: sunxi: Add Allwinner A83T CLK driver Add initial clock driver for Allwinner A83T. - Implement USB bus and USB clocks via ccu_clk_gate table for A83T, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A83T, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-02 18:03:55 +00:00
obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
clk: sunxi: Add Allwinner R40 CLK driver Add initial clock driver for Allwinner R40. - Implement USB bus and USB clocks via ccu_clk_gate for R40, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for R40, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-05 05:46:33 +00:00
obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
clk: sunxi: Add Allwinner V3S CLK driver Add initial clock driver for Allwinner V3S. - Implement USB bus and USB clocks via ccu_clk_gate table for V3S, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for V3S, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-05 09:01:54 +00:00
obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
clk: sunxi: Add Allwinner A80 CLK driver Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-11 10:11:46 +00:00
obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
clk: sunxi: Add Allwinner H3/H5 CLK driver Add initial clock driver for Allwinner H3/H5. - Implement USB bus and USB clocks via ccu_clk_gate table for H3/H5, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for H3/H5, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-02 10:13:02 +00:00
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2018-12-31 10:05:01 +00:00
obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
clk: sunxi: Add drivers for A31 and H6 PRCM CCUs Add a driver so the clocks/resets for these peripherals (especially I2C, RSB, and UART) can be enabled using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-12 14:47:25 +00:00
obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
clk: sunxi: Add support for H616 clocks This commit introduces DM H616 clock driver. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-11 20:11:52 +00:00
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
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