pinctrl: add pin control uclass support
This creates a new framework for handling of pin control devices,
i.e. devices that control different aspects of package pins.
This uclass handles pinmuxing and pin configuration; pinmuxing
controls switching among silicon blocks that share certain physical
pins, pin configuration handles electronic properties such as pin-
biasing, load capacitance etc.
This framework can support the same device tree bindings, but if you
do not need full interface support, you can disable some features to
reduce memory foot print. Typically around 1.5KB is necessary to
include full-featured uclass support on ARM board (CONFIG_PINCTRL +
CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX),
for example.
We are often limited on code size for SPL. Besides, we still have
many boards that do not support device tree configuration. The full
pinctrl, which requires OF_CONTROL, does not make sense for those
boards. So, this framework also has a Do-It-Yourself (let's say
simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the
uclass itself provides no systematic mechanism for identifying the
peripheral device, applying pinctrl settings, etc. They must be
done in each low-level driver. In return, you can save much memory
footprint and it might be useful especially for SPL.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-27 03:44:29 +00:00
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#
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# PINCTRL infrastructure and drivers
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#
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menu "Pin controllers"
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config PINCTRL
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bool "Support pin controllers"
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depends on DM
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help
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This enables the basic support for pinctrl framework. You may want
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to enable some more options depending on what you want to do.
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config PINCTRL_FULL
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bool "Support full pin controllers"
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depends on PINCTRL && OF_CONTROL
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default y
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help
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This provides Linux-compatible device tree interface for the pinctrl
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subsystem. This feature depends on device tree configuration because
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it parses a device tree to look for the pinctrl device which the
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peripheral device is associated with.
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If this option is disabled (it is the only possible choice for non-DT
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boards), the pinctrl core provides no systematic mechanism for
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identifying peripheral devices, applying needed pinctrl settings.
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It is totally up to the implementation of each low-level driver.
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You can save memory footprint in return for some limitations.
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config PINCTRL_GENERIC
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bool "Support generic pin controllers"
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depends on PINCTRL_FULL
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default y
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help
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Say Y here if you want to use the pinctrl subsystem through the
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generic DT interface. If enabled, some functions become available
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to parse common properties such as "pins", "groups", "functions" and
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some pin configuration parameters. It would be easier if you only
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need the generic DT interface for pin muxing and pin configuration.
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If you need to handle vendor-specific DT properties, you can disable
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this option and implement your own set_state callback in the pinctrl
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operations.
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config PINMUX
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bool "Support pin multiplexing controllers"
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depends on PINCTRL_GENERIC
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default y
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help
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This option enables pin multiplexing through the generic pinctrl
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2015-08-30 22:55:12 +00:00
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framework. Most SoCs have their own own multiplexing arrangement
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where a single pin can be used for several functions. An SoC pinctrl
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driver allows the required function to be selected for each pin.
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The driver is typically controlled by the device tree.
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pinctrl: add pin control uclass support
This creates a new framework for handling of pin control devices,
i.e. devices that control different aspects of package pins.
This uclass handles pinmuxing and pin configuration; pinmuxing
controls switching among silicon blocks that share certain physical
pins, pin configuration handles electronic properties such as pin-
biasing, load capacitance etc.
This framework can support the same device tree bindings, but if you
do not need full interface support, you can disable some features to
reduce memory foot print. Typically around 1.5KB is necessary to
include full-featured uclass support on ARM board (CONFIG_PINCTRL +
CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX),
for example.
We are often limited on code size for SPL. Besides, we still have
many boards that do not support device tree configuration. The full
pinctrl, which requires OF_CONTROL, does not make sense for those
boards. So, this framework also has a Do-It-Yourself (let's say
simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the
uclass itself provides no systematic mechanism for identifying the
peripheral device, applying pinctrl settings, etc. They must be
done in each low-level driver. In return, you can save much memory
footprint and it might be useful especially for SPL.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-27 03:44:29 +00:00
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config PINCONF
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bool "Support pin configuration controllers"
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depends on PINCTRL_GENERIC
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help
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This option enables pin configuration through the generic pinctrl
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framework.
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config SPL_PINCTRL
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bool "Support pin controlloers in SPL"
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depends on SPL && SPL_DM
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help
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This option is an SPL-variant of the PINCTRL option.
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See the help of PINCTRL for details.
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config SPL_PINCTRL_FULL
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bool "Support full pin controllers in SPL"
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depends on SPL_PINCTRL && SPL_OF_CONTROL
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default y
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help
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This option is an SPL-variant of the PINCTRL_FULL option.
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See the help of PINCTRL_FULL for details.
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config SPL_PINCTRL_GENERIC
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bool "Support generic pin controllers in SPL"
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depends on SPL_PINCTRL_FULL
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default y
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help
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This option is an SPL-variant of the PINCTRL_GENERIC option.
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See the help of PINCTRL_GENERIC for details.
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config SPL_PINMUX
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bool "Support pin multiplexing controllers in SPL"
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depends on SPL_PINCTRL_GENERIC
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default y
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help
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This option is an SPL-variant of the PINMUX option.
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See the help of PINMUX for details.
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2015-08-30 22:55:12 +00:00
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The pinctrl subsystem can add a substantial overhead to the SPL
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image since it typically requires quite a few tables either in the
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driver or in the device tree. If this is acceptable and you need
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to adjust pin multiplexing in SPL in order to boot into U-Boot,
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enable this option. You will need to enable device tree in SPL
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for this to work.
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pinctrl: add pin control uclass support
This creates a new framework for handling of pin control devices,
i.e. devices that control different aspects of package pins.
This uclass handles pinmuxing and pin configuration; pinmuxing
controls switching among silicon blocks that share certain physical
pins, pin configuration handles electronic properties such as pin-
biasing, load capacitance etc.
This framework can support the same device tree bindings, but if you
do not need full interface support, you can disable some features to
reduce memory foot print. Typically around 1.5KB is necessary to
include full-featured uclass support on ARM board (CONFIG_PINCTRL +
CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX),
for example.
We are often limited on code size for SPL. Besides, we still have
many boards that do not support device tree configuration. The full
pinctrl, which requires OF_CONTROL, does not make sense for those
boards. So, this framework also has a Do-It-Yourself (let's say
simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the
uclass itself provides no systematic mechanism for identifying the
peripheral device, applying pinctrl settings, etc. They must be
done in each low-level driver. In return, you can save much memory
footprint and it might be useful especially for SPL.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-27 03:44:29 +00:00
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config SPL_PINCONF
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bool "Support pin configuration controllers in SPL"
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depends on SPL_PINCTRL_GENERIC
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help
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This option is an SPL-variant of the PINCONF option.
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See the help of PINCONF for details.
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if PINCTRL || SPL_PINCTRL
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2016-03-16 08:59:55 +00:00
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config AR933X_PINCTRL
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bool "QCA/Athores ar933x pin control driver"
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depends on DM && SOC_AR933X
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help
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Support pin multiplexing control on QCA/Athores ar933x SoCs.
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The driver is controlled by a device tree node which contains
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both the GPIO definitions and pin control functions for each
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available multiplex function.
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2016-03-16 08:59:56 +00:00
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config QCA953X_PINCTRL
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bool "QCA/Athores qca953x pin control driver"
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depends on DM && SOC_QCA953X
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help
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Support pin multiplexing control on QCA/Athores qca953x SoCs.
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The driver is controlled by a device tree node which contains
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both the GPIO definitions and pin control functions for each
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available multiplex function.
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2015-08-30 22:55:35 +00:00
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config ROCKCHIP_PINCTRL
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bool "Rockchip pin control driver"
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depends on DM
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help
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Support pin multiplexing control on Rockchip SoCs. The driver is
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controlled by a device tree node which contains both the GPIO
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definitions and pin control functions for each available multiplex
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function.
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2015-11-17 06:20:20 +00:00
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config ROCKCHIP_3036_PINCTRL
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bool "Rockchip rk3036 pin control driver"
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depends on DM
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help
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Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is
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controlled by a device tree node which contains both the GPIO
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definitions and pin control functions for each available multiplex
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function.
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2015-08-27 03:44:30 +00:00
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config PINCTRL_SANDBOX
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bool "Sandbox pinctrl driver"
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depends on SANDBOX
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help
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This enables pinctrl driver for sandbox. Currently, this driver
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actually does nothing but print debug messages when pinctrl
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operations are invoked.
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2016-01-28 10:00:12 +00:00
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config PIC32_PINCTRL
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bool "Microchip PIC32 pin-control and pin-mux driver"
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depends on DM && MACH_PIC32
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default y
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help
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Supports individual pin selection and configuration for each remappable
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peripheral available on Microchip PIC32 SoCs. This driver is controlled
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by a device tree node which contains both GPIO defintion and pin control
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functions.
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pinctrl: add pin control uclass support
This creates a new framework for handling of pin control devices,
i.e. devices that control different aspects of package pins.
This uclass handles pinmuxing and pin configuration; pinmuxing
controls switching among silicon blocks that share certain physical
pins, pin configuration handles electronic properties such as pin-
biasing, load capacitance etc.
This framework can support the same device tree bindings, but if you
do not need full interface support, you can disable some features to
reduce memory foot print. Typically around 1.5KB is necessary to
include full-featured uclass support on ARM board (CONFIG_PINCTRL +
CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX),
for example.
We are often limited on code size for SPL. Besides, we still have
many boards that do not support device tree configuration. The full
pinctrl, which requires OF_CONTROL, does not make sense for those
boards. So, this framework also has a Do-It-Yourself (let's say
simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the
uclass itself provides no systematic mechanism for identifying the
peripheral device, applying pinctrl settings, etc. They must be
done in each low-level driver. In return, you can save much memory
footprint and it might be useful especially for SPL.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-27 03:44:29 +00:00
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endif
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pinctrl: imx: Introduce pinctrl driver for i.MX6
Introduce pinctrl for i.MX6
1. pinctrl-imx.c is for common usage. It's used by i.MX6/7.
2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry.
3. To the pinctrl_ops implementation, only set_state is implemented.
To i.MX6/7, the pinctrl dts entry is as following:
&iomuxc {
pinctrl-names = "default";
pinctrl_csi1: csi1grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
>;
};
[.....]
};
there is no property named function or groups. So pinctrl_generic_set_state
can not be used here.
5. This driver is a simple implementation for i.mx iomux controller,
only parse the fsl,pins property and write value to registers.
6. With DEBUG enabled, we can see log when "i2c bus 0":
"
set_state_simple op missing
imx_pinctrl_set_state: i2c1grp
mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
write mux: offset 0x14c val 0x10
select_input: offset 0x5d8 val 0x1
write config: offset 0x3bc val 0x7f
mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
write mux: offset 0x148 val 0x10
select_input: offset 0x5d4 val 0x1
write config: offset 0x3b8 val 0x7f
"
this means imx6 pinctrl driver works as expected.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-03 02:06:07 +00:00
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source "drivers/pinctrl/nxp/Kconfig"
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2015-09-11 11:17:32 +00:00
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source "drivers/pinctrl/uniphier/Kconfig"
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2016-04-23 16:48:08 +00:00
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source "drivers/pinctrl/exynos/Kconfig"
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2015-09-11 11:17:32 +00:00
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pinctrl: add pin control uclass support
This creates a new framework for handling of pin control devices,
i.e. devices that control different aspects of package pins.
This uclass handles pinmuxing and pin configuration; pinmuxing
controls switching among silicon blocks that share certain physical
pins, pin configuration handles electronic properties such as pin-
biasing, load capacitance etc.
This framework can support the same device tree bindings, but if you
do not need full interface support, you can disable some features to
reduce memory foot print. Typically around 1.5KB is necessary to
include full-featured uclass support on ARM board (CONFIG_PINCTRL +
CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX),
for example.
We are often limited on code size for SPL. Besides, we still have
many boards that do not support device tree configuration. The full
pinctrl, which requires OF_CONTROL, does not make sense for those
boards. So, this framework also has a Do-It-Yourself (let's say
simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the
uclass itself provides no systematic mechanism for identifying the
peripheral device, applying pinctrl settings, etc. They must be
done in each low-level driver. In return, you can save much memory
footprint and it might be useful especially for SPL.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-27 03:44:29 +00:00
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endmenu
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