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u-boot/arch/arm/include/asm/arch-ls102xa/config.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
arm: ls102xa: Add Freescale LS102xA SoC support The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05 05:52:34 +00:00
/*
* Copyright 2014, Freescale Semiconductor
*/
#ifndef _ASM_ARMV7_LS102XA_CONFIG_
#define _ASM_ARMV7_LS102XA_CONFIG_
#define OCRAM_BASE_ADDR 0x10000000
ARMv7: PSCI: ls102xa: move secure text section into OCRAM LS1021 offers two secure OCRAM blocks for trustzone. This patch moves all the secure text sections into the OCRAM. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-21 10:09:39 +00:00
#define OCRAM_SIZE 0x00010000
ls102xa: changing a few targets' configurations. Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-21 09:40:57 +00:00
#define OCRAM_BASE_S_ADDR 0x10010000
#define OCRAM_S_SIZE 0x00010000
arm: ls102xa: Add Freescale LS102xA SoC support The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05 05:52:34 +00:00
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#define CFG_SYS_DCSRBAR 0x20000000
arm: ls102xa: Add Freescale LS102xA SoC support The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05 05:52:34 +00:00
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00220000)
#define SYS_FSL_DCSR_RCPM_ADDR (CFG_SYS_DCSRBAR + 0x00222000)
arm: ls102xa: Add NAND boot support for LS1021AQDS board This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-09 09:38:14 +00:00
armv7: ls102xa: Rename GIC_ADDR and DCSR_RCPM_ADDR Instead of using CONFIG_* name space, rename these two macros to SYS_FSL_* space. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-26 15:09:30 +00:00
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
#define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:28 +00:00
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
arm: ls102xa: Add Freescale LS102xA SoC support The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05 05:52:34 +00:00
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
#define CFG_SYS_FSL_SEC_OFFSET 0x00700000
#define CFG_SYS_FSL_JR0_OFFSET 0x00710000
arm: ls102xa: Add Freescale LS102xA SoC support The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05 05:52:34 +00:00
#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CFG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL
#define CFG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL
#define CFG_SYS_PCIE1_VIRT_ADDR 0x24000000UL
#define CFG_SYS_PCIE2_VIRT_ADDR 0x34000000UL
#define CFG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */
arm/ls102xa: create TLB to map PCIe region LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins 0x48_00000000. In order to access PCIe device, we must create TLB to map the 40bit physical address to 32bit virtual address. This patch will enable MMU after DDR is available and creates MMU table in DRAM to map all 4G space; then, re-use the reserved space to map PCIe region. The following the mapping layout. VA mapping: ------- <---- 0GB | | | | |-------| <---- 0x24000000 |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 |-------| <---- 0x300000000 | | |-------| <---- 0x34000000 |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 |-------| <---- 0x40000000 | | |-------| <---- 0x80000000 DDR0 space start |\\\\\\\| |\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space |\\\\\\\| ------- <---- 4GB DDR0 space end Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-21 09:29:17 +00:00
/*
* TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
* So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
*/
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
#define CFG_SYS_PCIE1_PHYS_ADDR (CFG_SYS_PCIE1_PHYS_BASE + \
CFG_SYS_PCIE1_VIRT_ADDR)
#define CFG_SYS_PCIE2_PHYS_ADDR (CFG_SYS_PCIE2_PHYS_BASE + \
CFG_SYS_PCIE2_VIRT_ADDR)
arm/ls102xa: create TLB to map PCIe region LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins 0x48_00000000. In order to access PCIe device, we must create TLB to map the 40bit physical address to 32bit virtual address. This patch will enable MMU after DDR is available and creates MMU table in DRAM to map all 4G space; then, re-use the reserved space to map PCIe region. The following the mapping layout. VA mapping: ------- <---- 0GB | | | | |-------| <---- 0x24000000 |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 |-------| <---- 0x300000000 | | |-------| <---- 0x34000000 |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 |-------| <---- 0x40000000 | | |-------| <---- 0x80000000 DDR0 space start |\\\\\\\| |\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space |\\\\\\\| ------- <---- 4GB DDR0 space end Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-21 09:29:17 +00:00
arm: ls1021a: Add sata support on qds and twr board Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-16 08:06:05 +00:00
/* SATA */
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
arm: ls102xa: Add Freescale LS102xA SoC support The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05 05:52:34 +00:00
#ifdef CONFIG_DDR_SPD
layerscape: Remove some unused CONFIG symbols All of these symbols are not referenced anywhere else in the code, so remove them. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-25 15:02:34 +00:00
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
arm: ls102xa: Add Freescale LS102xA SoC support The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05 05:52:34 +00:00
#endif
video: dcu: Add DCU driver support This patch is to add DCU driver support. DCU also named 2D-ACE(Two Dimensional Animation and Compositing Engine) is a system master that fetches graphics stored in internal or external memory and displays them on a TFT LCD panel. Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-05 05:52:48 +00:00
#define DCU_LAYER_MAX_NUM 16
arm: ls102xa: Add Freescale LS102xA SoC support The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05 05:52:34 +00:00
armv7: ls1021a: Drop macro CONFIG_LS102XA Use CONFIG_ARCH_LS1021A instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-27 18:41:03 +00:00
#ifdef CONFIG_ARCH_LS1021A
arm: ls102xa: Add Freescale LS102xA SoC support The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05 05:52:34 +00:00
#else
#error SoC not defined
#endif
ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD boot As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are only enabled in QSPI boot, and disabled in other boot modes. IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot. This patch will add fdt support for the above rules. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-26 05:14:01 +00:00
#define FSL_IFC_COMPAT "fsl,ifc"
arm: ls102xa: fdt: Update FSL_QSPI_COMPAT and FSL_DSPI_COMPAT As the compatible property values for QSPI and DSPI dts nodes are changed in kernel, FSL_QSPI_COMPAT and FSL_DSPI_COMPAT need to be updated too. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-29 06:50:20 +00:00
#define FSL_QSPI_COMPAT "fsl,ls1021a-qspi"
#define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi"
ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD boot As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are only enabled in QSPI boot, and disabled in other boot modes. IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot. This patch will add fdt support for the above rules. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-26 05:14:01 +00:00
arm: ls102xa: Add Freescale LS102xA SoC support The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05 05:52:34 +00:00
#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
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