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https://github.com/AsahiLinux/u-boot
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107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
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/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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unsigned int fsl_ddr_get_mem_data_rate(void)
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{
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return get_ddr_freq(0);
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}
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void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
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{
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int ret;
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/*
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* The P1022 has only one DDR controller, and the board has only one
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* DIMM slot.
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*/
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ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd,
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sizeof(ddr3_spd_eeprom_t));
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if (ret) {
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debug("DDR: failed to read SPD from address %u\n",
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SPD_EEPROM_ADDRESS1);
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memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t));
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}
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}
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typedef struct {
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u32 datarate_mhz_low;
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u32 datarate_mhz_high;
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u32 n_ranks;
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u32 clk_adjust; /* Range: 0-8 */
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u32 cpo; /* Range: 2-31 */
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u32 write_data_delay; /* Range: 0-6 */
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u32 force_2T;
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} board_specific_parameters_t;
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static const board_specific_parameters_t bsp[] = {
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/*
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* lo| hi| num| clk| cpo|wrdata|2T
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* mhz| mhz|ranks|adjst| | delay|
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*/
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{ 0, 333, 1, 5, 31, 3, 0},
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{334, 400, 1, 5, 31, 3, 0},
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{401, 549, 1, 5, 31, 3, 0},
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{550, 680, 1, 5, 31, 5, 0},
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{681, 850, 1, 5, 31, 5, 0},
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{ 0, 333, 2, 5, 31, 3, 0},
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{334, 400, 2, 5, 31, 3, 0},
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{401, 549, 2, 5, 31, 3, 0},
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{550, 680, 2, 5, 31, 5, 0},
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{681, 850, 2, 5, 31, 5, 0},
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};
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void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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unsigned long ddr_freq;
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unsigned int i;
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/* set odt_rd_cfg and odt_wr_cfg. */
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 1;
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}
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/*
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* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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for (i = 0; i < ARRAY_SIZE(bsp); i++) {
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if (ddr_freq >= bsp[i].datarate_mhz_low &&
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ddr_freq <= bsp[i].datarate_mhz_high &&
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pdimm->n_ranks == bsp[i].n_ranks) {
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popts->clk_adjust = bsp[i].clk_adjust;
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popts->cpo_override = bsp[i].cpo;
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popts->write_data_delay = bsp[i].write_data_delay;
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popts->twoT_en = bsp[i].force_2T;
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break;
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}
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}
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popts->half_strength_driver_enable = 1;
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/* Per AN4039, enable ZQ calibration. */
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popts->zq_en = 1;
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/*
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* For wake-up on ARP, we need auto self refresh enabled
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*/
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popts->auto_self_refresh_en = 1;
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popts->sr_it = 0xb;
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}
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