2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2015-05-09 01:28:35 +00:00
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/*
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* Copyright (C) 2013 Gateworks Corporation
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*
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* Author: Tim Harvey <tharvey@gateworks.com>
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*/
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2020-05-10 17:39:55 +00:00
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#include <common.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2017-03-13 15:51:03 +00:00
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#include <asm/arch/clock.h>
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2015-05-09 01:28:35 +00:00
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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2017-06-29 08:16:06 +00:00
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#include <asm/mach-imx/mxc_i2c.h>
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2019-08-01 15:46:52 +00:00
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#include <env.h>
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2019-06-21 03:42:28 +00:00
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#include <fsl_esdhc_imx.h>
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2015-05-09 01:28:35 +00:00
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#include <hwconfig.h>
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2020-05-10 17:40:11 +00:00
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#include <linux/delay.h>
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2015-05-09 01:28:35 +00:00
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#include "common.h"
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/* UART2: Serial Console */
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static iomux_v3_cfg_t const uart2_pads[] = {
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IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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void setup_iomux_uart(void)
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{
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SETUP_IOMUX_PADS(uart2_pads);
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}
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2017-03-13 15:51:03 +00:00
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/* MMC */
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2017-03-17 14:30:38 +00:00
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static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
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IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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};
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2017-03-17 14:32:21 +00:00
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/* 4-bit microSD on SD2 */
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static iomux_v3_cfg_t const gw5904_mmc_pads[] = {
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IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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/* CD */
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IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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};
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2017-03-17 14:31:02 +00:00
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/* 8-bit eMMC on SD2/NAND */
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static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
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IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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};
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2017-03-13 15:51:03 +00:00
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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};
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2015-05-09 01:28:35 +00:00
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/*
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* Baseboard specific GPIO
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*/
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static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
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/* IOEXP_PWREN# */
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
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/* IOEXP_IRQ# */
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
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/* GPS_SHDN */
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IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
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/* PCIESKT_WDIS# */
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
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};
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static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
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2017-03-13 15:51:08 +00:00
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/* SD3_VSELECT */
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IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
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2016-07-15 14:14:22 +00:00
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/* RS232_EN# */
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IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
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2016-05-24 18:03:56 +00:00
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/* MSATA_EN */
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IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
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2015-05-09 01:28:35 +00:00
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/* IOEXP_PWREN# */
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
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/* IOEXP_IRQ# */
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
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/* GPS_SHDN */
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IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
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/* USBOTG_SEL */
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IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
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2015-05-26 18:04:54 +00:00
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/* RS485_EN */
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IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
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2015-05-09 01:28:35 +00:00
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/* PCIESKT_WDIS# */
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
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};
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static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
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2017-03-13 15:51:08 +00:00
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/* SD3_VSELECT */
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IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
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2016-07-15 14:14:22 +00:00
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/* RS232_EN# */
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IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
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2016-05-24 18:03:56 +00:00
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/* MSATA_EN */
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IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
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2015-05-09 01:28:35 +00:00
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/* IOEXP_PWREN# */
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
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/* IOEXP_IRQ# */
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
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/* DIOI2C_DIS# */
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IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
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/* GPS_SHDN */
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IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
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2015-05-26 18:04:54 +00:00
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/* RS485_EN */
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IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
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2015-05-09 01:28:35 +00:00
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/* PCIESKT_WDIS# */
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
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2021-07-24 17:40:45 +00:00
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/* J6_PWREN */
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IOMUX_PADS(PAD_EIM_DA15__GPIO3_IO15 | DIO_PAD_CFG),
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/* PCIEGBE_EN */
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IOMUX_PADS(PAD_EIM_DA14__GPIO3_IO14 | DIO_PAD_CFG),
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2015-05-09 01:28:35 +00:00
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};
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static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
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2017-03-13 15:51:08 +00:00
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/* SD3_VSELECT */
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IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
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2016-07-15 14:14:22 +00:00
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/* RS232_EN# */
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IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
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2016-05-24 18:03:56 +00:00
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/* MSATA_EN */
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IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
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2015-05-09 01:28:35 +00:00
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/* MIPI_DIO */
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IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
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/* RS485_EN */
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IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
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/* IOEXP_PWREN# */
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2015-05-26 18:04:54 +00:00
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
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2015-05-09 01:28:35 +00:00
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/* IOEXP_IRQ# */
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2015-05-26 18:04:54 +00:00
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
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2015-05-09 01:28:35 +00:00
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/* DIOI2C_DIS# */
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IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
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2015-05-26 18:04:54 +00:00
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/* RS485_EN */
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IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
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2015-05-09 01:28:35 +00:00
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/* PCIESKT_WDIS# */
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IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
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2021-07-24 17:40:46 +00:00
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/* J7_PWREN */
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IOMUX_PADS(PAD_EIM_DA15__GPIO3_IO15 | DIO_PAD_CFG),
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/* PCIEGBE_EN */
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IOMUX_PADS(PAD_EIM_DA14__GPIO3_IO14 | DIO_PAD_CFG),
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2015-05-09 01:28:35 +00:00
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};
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static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
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/* PCIESKT_WDIS# */
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
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};
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static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
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2016-05-24 18:03:56 +00:00
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/* MSATA_EN */
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IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
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2015-05-26 18:04:54 +00:00
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/* USBOTG_SEL */
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IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
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2015-05-09 01:28:35 +00:00
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/* MX6_DIO[4:9] */
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IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
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IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
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IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
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IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
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IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
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IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
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/* PCIEGBE1_OFF# */
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IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
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/* PCIEGBE2_OFF# */
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IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
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/* PCIESKT_WDIS# */
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
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};
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2016-05-24 18:03:58 +00:00
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static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
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2017-03-13 15:51:08 +00:00
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/* SD3_VSELECT */
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IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
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2016-05-24 18:03:58 +00:00
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/* PCIESKT_WDIS# */
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
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};
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2017-03-17 14:31:02 +00:00
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static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
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/* RS232_EN# */
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IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
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/* IOEXP_PWREN# */
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
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/* IOEXP_IRQ# */
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
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/* DIOI2C_DIS# */
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IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
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/* RS485_EN */
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IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
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/* PCIESKT_WDIS# */
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
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/* 12V0_PWR_EN */
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IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
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};
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2019-02-04 21:10:58 +00:00
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static iomux_v3_cfg_t const gw5901_gpio_pads[] = {
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/* ETH1_EN */
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IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
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/* PMIC reset */
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IOMUX_PADS(PAD_DISP0_DAT8__WDOG1_B | DIO_PAD_CFG),
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/* COM_CFGA/B/C/D */
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IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
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IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15 | DIO_PAD_CFG),
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IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16 | DIO_PAD_CFG),
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IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
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/* ETI_IRQ# */
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IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
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/* DIO_IRQ# */
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IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
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|
|
/* FIBER_SIGDET */
|
|
|
|
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
|
|
|
|
};
|
|
|
|
|
|
|
|
static iomux_v3_cfg_t const gw5902_gpio_pads[] = {
|
|
|
|
/* UART1_EN# */
|
|
|
|
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
|
|
|
|
/* 5V_UVLO */
|
|
|
|
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
|
|
|
|
/* ETI_IRQ# */
|
|
|
|
IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
|
|
|
|
/* DIO_IRQ# */
|
|
|
|
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
|
|
|
|
};
|
|
|
|
|
2017-03-17 14:32:21 +00:00
|
|
|
static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
|
|
|
|
/* BKLT_12VEN */
|
|
|
|
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
|
|
|
|
/* EMMY_PDN# */
|
|
|
|
IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG),
|
|
|
|
/* EMMY_CFG1# */
|
|
|
|
IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
|
|
|
|
/* EMMY_CFG1# */
|
|
|
|
IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
|
|
|
|
/* USBH1_PEN (EHCI) */
|
|
|
|
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
|
|
|
|
/* USBDPC_PEN */
|
|
|
|
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
|
|
|
|
/* TOUCH_RST */
|
|
|
|
IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
|
|
|
|
/* AUDIO_RST# */
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
|
|
|
|
/* UART1_TEN# */
|
|
|
|
IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
|
|
|
|
/* LVDS_BKLEN # */
|
|
|
|
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
|
|
|
|
/* RGMII_PDWN# */
|
|
|
|
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG),
|
|
|
|
/* TOUCH_IRQ# */
|
|
|
|
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
|
|
|
|
/* TOUCH_RST# */
|
|
|
|
IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
|
|
|
|
};
|
|
|
|
|
2017-03-17 14:30:38 +00:00
|
|
|
static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
|
|
|
|
/* IOEXP_PWREN# */
|
|
|
|
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
|
|
|
|
/* IOEXP_IRQ# */
|
|
|
|
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
|
|
|
|
/* DIOI2C_DIS# */
|
|
|
|
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
|
|
|
|
/* UART_RS485 */
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG),
|
|
|
|
/* UART_HALF */
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG),
|
|
|
|
/* SKT1_WDIS# */
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG),
|
|
|
|
/* SKT1_RST# */
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG),
|
|
|
|
/* SKT2_WDIS# */
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG),
|
|
|
|
/* SKT2_RST# */
|
|
|
|
IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
|
|
|
|
/* M2_OFF# */
|
|
|
|
IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
|
|
|
|
/* M2_WDIS# */
|
|
|
|
IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
|
|
|
|
/* M2_RST# */
|
|
|
|
IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
|
2019-02-04 21:10:57 +00:00
|
|
|
/* RS232_EN# */
|
|
|
|
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
|
2017-03-17 14:30:38 +00:00
|
|
|
};
|
|
|
|
|
2019-02-04 21:10:50 +00:00
|
|
|
static iomux_v3_cfg_t const gw5905_gpio_pads[] = {
|
|
|
|
/* EMMY_PDN# */
|
|
|
|
IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
|
|
|
|
/* MIPI_RST */
|
|
|
|
IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
|
|
|
|
/* MIPI_PWDN */
|
|
|
|
IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
|
|
|
|
/* USBEHCI_SEL */
|
|
|
|
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
|
|
|
|
/* LVDS_BKLEN # */
|
|
|
|
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
|
|
|
|
/* PCIESKT_WDIS# */
|
|
|
|
IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | DIO_PAD_CFG),
|
|
|
|
/* SPK_SHDN# */
|
|
|
|
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
|
|
|
|
/* DECT_RST# */
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
|
|
|
|
/* USBH1_PEN (EHCI) */
|
|
|
|
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
|
|
|
|
/* LVDS_PWM */
|
|
|
|
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
|
|
|
|
/* CODEC_RST */
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
|
|
|
|
/* GYRO_CONTROL/DATA_EN */
|
|
|
|
IOMUX_PADS(PAD_CSI0_DAT8__GPIO5_IO26 | DIO_PAD_CFG),
|
|
|
|
/* TOUCH_RST */
|
|
|
|
IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
|
|
|
|
/* TOUCH_IRQ */
|
|
|
|
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
|
|
|
|
};
|
|
|
|
|
2021-07-24 17:40:42 +00:00
|
|
|
static iomux_v3_cfg_t const gw5910_gpio_pads[] = {
|
|
|
|
/* SD3_VSELECT */
|
|
|
|
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
|
|
|
|
/* RS232_EN# */
|
|
|
|
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
|
|
|
|
/* RF_RESET# */
|
|
|
|
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
|
|
|
|
/* RF_BOOT */
|
|
|
|
IOMUX_PADS(PAD_GPIO_8__GPIO1_IO08 | DIO_PAD_CFG),
|
|
|
|
/* PCIESKT_WDIS# */
|
|
|
|
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
|
|
|
|
};
|
|
|
|
|
2021-07-24 17:40:43 +00:00
|
|
|
static iomux_v3_cfg_t const gw5912_gpio_pads[] = {
|
|
|
|
/* SD3_VSELECT */
|
|
|
|
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
|
|
|
|
/* RS232_EN# */
|
|
|
|
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
|
|
|
|
/* PCIESKT_WDIS# */
|
|
|
|
IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
|
|
|
|
};
|
|
|
|
|
2016-07-15 14:14:23 +00:00
|
|
|
/* Digital I/O */
|
|
|
|
struct dio_cfg gw51xx_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
|
|
|
|
IMX_GPIO_NR(1, 16),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
|
|
|
IMX_GPIO_NR(1, 19),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
|
|
|
2
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
|
|
|
IMX_GPIO_NR(1, 17),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
|
|
|
3
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
|
|
|
|
IMX_GPIO_NR(1, 18),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
|
|
|
|
4
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct dio_cfg gw52xx_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
|
|
|
|
IMX_GPIO_NR(1, 16),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
|
|
|
IMX_GPIO_NR(1, 19),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
|
|
|
2
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
|
|
|
IMX_GPIO_NR(1, 17),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
|
|
|
3
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
|
|
|
|
IMX_GPIO_NR(1, 20),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct dio_cfg gw53xx_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
|
|
|
|
IMX_GPIO_NR(1, 16),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
|
|
|
IMX_GPIO_NR(1, 19),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
|
|
|
2
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
|
|
|
IMX_GPIO_NR(1, 17),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
|
|
|
3
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
|
|
|
|
IMX_GPIO_NR(1, 20),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct dio_cfg gw54xx_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
|
|
|
|
IMX_GPIO_NR(1, 9),
|
|
|
|
{ IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
|
|
|
|
1
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
|
|
|
IMX_GPIO_NR(1, 19),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
|
|
|
2
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
|
|
|
|
IMX_GPIO_NR(2, 9),
|
|
|
|
{ IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
|
|
|
|
3
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
|
|
|
|
IMX_GPIO_NR(2, 10),
|
|
|
|
{ IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
|
|
|
|
4
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct dio_cfg gw551x_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
|
|
|
IMX_GPIO_NR(1, 19),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
|
|
|
2
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
|
|
|
IMX_GPIO_NR(1, 17),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
|
|
|
3
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct dio_cfg gw552x_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
|
|
|
|
IMX_GPIO_NR(1, 16),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
|
|
|
IMX_GPIO_NR(1, 19),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
|
|
|
2
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
|
|
|
IMX_GPIO_NR(1, 17),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
|
|
|
3
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
|
|
|
|
IMX_GPIO_NR(1, 20),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
2016-07-15 14:14:24 +00:00
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18) },
|
|
|
|
IMX_GPIO_NR(5, 18),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20) },
|
|
|
|
IMX_GPIO_NR(5, 20),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21) },
|
|
|
|
IMX_GPIO_NR(5, 21),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22) },
|
|
|
|
IMX_GPIO_NR(5, 22),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23) },
|
|
|
|
IMX_GPIO_NR(5, 23),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25) },
|
|
|
|
IMX_GPIO_NR(5, 25),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
2016-07-15 14:14:23 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
struct dio_cfg gw553x_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
|
|
|
|
IMX_GPIO_NR(1, 16),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
|
|
|
IMX_GPIO_NR(1, 19),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
|
|
|
2
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
|
|
|
IMX_GPIO_NR(1, 17),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
|
|
|
3
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
|
|
|
|
IMX_GPIO_NR(1, 18),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
|
|
|
|
4
|
|
|
|
},
|
|
|
|
};
|
2015-05-09 01:28:35 +00:00
|
|
|
|
2017-03-17 14:31:02 +00:00
|
|
|
struct dio_cfg gw560x_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
|
|
|
|
IMX_GPIO_NR(1, 16),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
|
|
|
IMX_GPIO_NR(1, 19),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
|
|
|
2
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
|
|
|
IMX_GPIO_NR(1, 17),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
|
|
|
3
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
|
|
|
|
IMX_GPIO_NR(1, 20),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2019-02-04 21:10:58 +00:00
|
|
|
struct dio_cfg gw5901_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
|
|
|
|
IMX_GPIO_NR(5, 14),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
|
|
|
|
IMX_GPIO_NR(5, 15),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
|
|
|
|
IMX_GPIO_NR(5, 16),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
|
|
|
|
IMX_GPIO_NR(5, 17),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct dio_cfg gw5902_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
|
|
|
|
IMX_GPIO_NR(5, 14),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
|
|
|
|
IMX_GPIO_NR(5, 15),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
|
|
|
|
IMX_GPIO_NR(5, 16),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
|
|
|
|
IMX_GPIO_NR(5, 17),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2017-03-17 14:32:21 +00:00
|
|
|
struct dio_cfg gw5903_dio[] = {
|
|
|
|
};
|
|
|
|
|
2017-03-17 14:30:38 +00:00
|
|
|
struct dio_cfg gw5904_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
|
|
|
|
IMX_GPIO_NR(1, 16),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
|
|
|
IMX_GPIO_NR(1, 19),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
|
|
|
2
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
|
|
|
IMX_GPIO_NR(1, 17),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
|
|
|
3
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
|
|
|
|
IMX_GPIO_NR(1, 20),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) },
|
|
|
|
IMX_GPIO_NR(2, 0),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) },
|
|
|
|
IMX_GPIO_NR(2, 1),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) },
|
|
|
|
IMX_GPIO_NR(2, 2),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) },
|
|
|
|
IMX_GPIO_NR(2, 3),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) },
|
|
|
|
IMX_GPIO_NR(2, 4),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) },
|
|
|
|
IMX_GPIO_NR(2, 5),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) },
|
|
|
|
IMX_GPIO_NR(2, 6),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) },
|
|
|
|
IMX_GPIO_NR(2, 7),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2019-02-04 21:10:54 +00:00
|
|
|
struct dio_cfg gw5906_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
|
|
|
|
IMX_GPIO_NR(1, 16),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
|
|
|
IMX_GPIO_NR(1, 19),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
|
|
|
2
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
|
|
|
IMX_GPIO_NR(1, 17),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
|
|
|
3
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
|
|
|
|
IMX_GPIO_NR(1, 20),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2021-07-24 17:40:44 +00:00
|
|
|
struct dio_cfg gw5913_dio[] = {
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
|
|
|
|
IMX_GPIO_NR(1, 16),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
|
|
|
IMX_GPIO_NR(1, 19),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
|
|
|
2
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
|
|
|
IMX_GPIO_NR(1, 17),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
|
|
|
3
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
|
|
|
|
IMX_GPIO_NR(1, 18),
|
|
|
|
{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
|
|
|
|
4
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15) },
|
|
|
|
IMX_GPIO_NR(1, 15),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14) },
|
|
|
|
IMX_GPIO_NR(1, 14),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
{
|
|
|
|
{ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05) },
|
|
|
|
IMX_GPIO_NR(4, 5),
|
|
|
|
{ 0, 0 },
|
|
|
|
0
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2015-05-09 01:28:35 +00:00
|
|
|
/*
|
|
|
|
* Board Specific GPIO
|
|
|
|
*/
|
|
|
|
struct ventana gpio_cfg[GW_UNKNOWN] = {
|
|
|
|
/* GW5400proto */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw54xx_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
|
2016-07-15 14:14:23 +00:00
|
|
|
.dio_cfg = gw54xx_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw54xx_dio),
|
2015-05-09 01:28:35 +00:00
|
|
|
.mezz_pwren = IMX_GPIO_NR(4, 7),
|
|
|
|
.mezz_irq = IMX_GPIO_NR(4, 9),
|
|
|
|
.rs485en = IMX_GPIO_NR(3, 24),
|
|
|
|
.dioi2c_en = IMX_GPIO_NR(4, 5),
|
|
|
|
.pcie_sson = IMX_GPIO_NR(1, 20),
|
2017-03-17 14:30:38 +00:00
|
|
|
.mmc_cd = IMX_GPIO_NR(7, 0),
|
2021-07-24 17:40:43 +00:00
|
|
|
.wdis = -1,
|
2015-05-09 01:28:35 +00:00
|
|
|
},
|
|
|
|
|
|
|
|
/* GW51xx */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw51xx_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
|
2016-07-15 14:14:23 +00:00
|
|
|
.dio_cfg = gw51xx_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw51xx_dio),
|
2015-05-09 01:28:35 +00:00
|
|
|
.mezz_pwren = IMX_GPIO_NR(2, 19),
|
|
|
|
.mezz_irq = IMX_GPIO_NR(2, 18),
|
|
|
|
.gps_shdn = IMX_GPIO_NR(1, 2),
|
|
|
|
.wdis = IMX_GPIO_NR(7, 12),
|
|
|
|
},
|
|
|
|
|
|
|
|
/* GW52xx */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw52xx_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
|
2016-07-15 14:14:23 +00:00
|
|
|
.dio_cfg = gw52xx_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw52xx_dio),
|
2015-05-09 01:28:35 +00:00
|
|
|
.mezz_pwren = IMX_GPIO_NR(2, 19),
|
|
|
|
.mezz_irq = IMX_GPIO_NR(2, 18),
|
|
|
|
.gps_shdn = IMX_GPIO_NR(1, 27),
|
|
|
|
.usb_sel = IMX_GPIO_NR(1, 2),
|
|
|
|
.wdis = IMX_GPIO_NR(7, 12),
|
2016-05-24 18:03:56 +00:00
|
|
|
.msata_en = GP_MSATA_SEL,
|
2016-07-15 14:14:22 +00:00
|
|
|
.rs232_en = GP_RS232_EN,
|
2017-03-13 15:51:08 +00:00
|
|
|
.vsel_pin = IMX_GPIO_NR(6, 14),
|
2017-03-17 14:30:38 +00:00
|
|
|
.mmc_cd = IMX_GPIO_NR(7, 0),
|
2015-05-09 01:28:35 +00:00
|
|
|
},
|
|
|
|
|
|
|
|
/* GW53xx */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw53xx_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
|
2016-07-15 14:14:23 +00:00
|
|
|
.dio_cfg = gw53xx_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw53xx_dio),
|
2015-05-09 01:28:35 +00:00
|
|
|
.mezz_pwren = IMX_GPIO_NR(2, 19),
|
|
|
|
.mezz_irq = IMX_GPIO_NR(2, 18),
|
|
|
|
.gps_shdn = IMX_GPIO_NR(1, 27),
|
|
|
|
.wdis = IMX_GPIO_NR(7, 12),
|
2016-05-24 18:03:56 +00:00
|
|
|
.msata_en = GP_MSATA_SEL,
|
2016-07-15 14:14:22 +00:00
|
|
|
.rs232_en = GP_RS232_EN,
|
2017-03-13 15:51:08 +00:00
|
|
|
.vsel_pin = IMX_GPIO_NR(6, 14),
|
2017-03-17 14:30:38 +00:00
|
|
|
.mmc_cd = IMX_GPIO_NR(7, 0),
|
2015-05-09 01:28:35 +00:00
|
|
|
},
|
|
|
|
|
|
|
|
/* GW54xx */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw54xx_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
|
2016-07-15 14:14:23 +00:00
|
|
|
.dio_cfg = gw54xx_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw54xx_dio),
|
2015-05-09 01:28:35 +00:00
|
|
|
.mezz_pwren = IMX_GPIO_NR(2, 19),
|
|
|
|
.mezz_irq = IMX_GPIO_NR(2, 18),
|
|
|
|
.rs485en = IMX_GPIO_NR(7, 1),
|
|
|
|
.dioi2c_en = IMX_GPIO_NR(4, 5),
|
|
|
|
.pcie_sson = IMX_GPIO_NR(1, 20),
|
|
|
|
.wdis = IMX_GPIO_NR(5, 17),
|
2016-05-24 18:03:56 +00:00
|
|
|
.msata_en = GP_MSATA_SEL,
|
2016-07-15 14:14:22 +00:00
|
|
|
.rs232_en = GP_RS232_EN,
|
2017-03-13 15:51:08 +00:00
|
|
|
.vsel_pin = IMX_GPIO_NR(6, 14),
|
2017-03-17 14:30:38 +00:00
|
|
|
.mmc_cd = IMX_GPIO_NR(7, 0),
|
2015-05-09 01:28:35 +00:00
|
|
|
},
|
|
|
|
|
|
|
|
/* GW551x */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw551x_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
|
2016-07-15 14:14:23 +00:00
|
|
|
.dio_cfg = gw551x_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw551x_dio),
|
2015-05-09 01:28:35 +00:00
|
|
|
.wdis = IMX_GPIO_NR(7, 12),
|
|
|
|
},
|
|
|
|
|
|
|
|
/* GW552x */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw552x_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
|
2016-07-15 14:14:23 +00:00
|
|
|
.dio_cfg = gw552x_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw552x_dio),
|
2015-05-26 18:04:54 +00:00
|
|
|
.usb_sel = IMX_GPIO_NR(1, 7),
|
2015-05-09 01:28:35 +00:00
|
|
|
.wdis = IMX_GPIO_NR(7, 12),
|
2016-05-24 18:03:56 +00:00
|
|
|
.msata_en = GP_MSATA_SEL,
|
2015-05-09 01:28:35 +00:00
|
|
|
},
|
2016-05-24 18:03:58 +00:00
|
|
|
|
|
|
|
/* GW553x */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw553x_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
|
2016-07-15 14:14:23 +00:00
|
|
|
.dio_cfg = gw553x_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw553x_dio),
|
2016-05-24 18:03:58 +00:00
|
|
|
.wdis = IMX_GPIO_NR(7, 12),
|
2017-03-13 15:51:08 +00:00
|
|
|
.vsel_pin = IMX_GPIO_NR(6, 14),
|
2017-03-17 14:30:38 +00:00
|
|
|
.mmc_cd = IMX_GPIO_NR(7, 0),
|
|
|
|
},
|
|
|
|
|
2017-03-17 14:31:02 +00:00
|
|
|
/* GW560x */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw560x_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
|
|
|
|
.dio_cfg = gw560x_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw560x_dio),
|
|
|
|
.mezz_pwren = IMX_GPIO_NR(2, 19),
|
|
|
|
.mezz_irq = IMX_GPIO_NR(2, 18),
|
|
|
|
.rs232_en = GP_RS232_EN,
|
|
|
|
.wdis = IMX_GPIO_NR(7, 12),
|
|
|
|
.mmc_cd = IMX_GPIO_NR(7, 0),
|
|
|
|
},
|
|
|
|
|
2019-02-04 21:10:58 +00:00
|
|
|
/* GW5901 */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw5901_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw5901_gpio_pads)/2,
|
|
|
|
.dio_cfg = gw5901_dio,
|
2021-07-24 17:40:43 +00:00
|
|
|
.wdis = -1,
|
2019-02-04 21:10:58 +00:00
|
|
|
},
|
|
|
|
|
|
|
|
/* GW5902 */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw5902_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw5902_gpio_pads)/2,
|
|
|
|
.dio_cfg = gw5902_dio,
|
|
|
|
.rs232_en = GP_RS232_EN,
|
2021-07-24 17:40:43 +00:00
|
|
|
.wdis = -1,
|
2019-02-04 21:10:58 +00:00
|
|
|
},
|
|
|
|
|
2017-03-17 14:32:21 +00:00
|
|
|
/* GW5903 */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw5903_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
|
|
|
|
.dio_cfg = gw5903_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw5903_dio),
|
|
|
|
.mmc_cd = IMX_GPIO_NR(6, 11),
|
2021-07-24 17:40:43 +00:00
|
|
|
.wdis = -1,
|
2017-03-17 14:32:21 +00:00
|
|
|
},
|
|
|
|
|
2017-03-17 14:30:38 +00:00
|
|
|
/* GW5904 */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw5904_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
|
|
|
|
.dio_cfg = gw5904_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw5904_dio),
|
|
|
|
.mezz_pwren = IMX_GPIO_NR(2, 19),
|
|
|
|
.mezz_irq = IMX_GPIO_NR(2, 18),
|
2021-07-24 17:40:43 +00:00
|
|
|
.wdis = -1,
|
2016-05-24 18:03:58 +00:00
|
|
|
},
|
2019-02-04 21:10:50 +00:00
|
|
|
|
|
|
|
/* GW5905 */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw5905_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw5905_gpio_pads)/2,
|
|
|
|
.wdis = IMX_GPIO_NR(7, 13),
|
|
|
|
},
|
2019-02-04 21:10:54 +00:00
|
|
|
|
|
|
|
/* GW5906 */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw552x_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
|
|
|
|
.dio_cfg = gw5906_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw5906_dio),
|
|
|
|
.usb_sel = IMX_GPIO_NR(1, 7),
|
|
|
|
.wdis = IMX_GPIO_NR(7, 12),
|
|
|
|
.msata_en = GP_MSATA_SEL,
|
|
|
|
},
|
2019-02-04 21:10:55 +00:00
|
|
|
|
|
|
|
/* GW5907 */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw51xx_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
|
|
|
|
.dio_cfg = gw51xx_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw51xx_dio),
|
|
|
|
.wdis = IMX_GPIO_NR(7, 12),
|
|
|
|
},
|
2019-02-04 21:10:56 +00:00
|
|
|
|
|
|
|
/* GW5908 */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw53xx_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
|
|
|
|
.dio_cfg = gw53xx_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw53xx_dio),
|
|
|
|
.mezz_pwren = IMX_GPIO_NR(2, 19),
|
|
|
|
.mezz_irq = IMX_GPIO_NR(2, 18),
|
|
|
|
.gps_shdn = IMX_GPIO_NR(1, 27),
|
|
|
|
.wdis = IMX_GPIO_NR(7, 12),
|
|
|
|
.msata_en = GP_MSATA_SEL,
|
|
|
|
.rs232_en = GP_RS232_EN,
|
|
|
|
},
|
2019-02-04 21:10:57 +00:00
|
|
|
|
|
|
|
/* GW5909 */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw5904_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
|
|
|
|
.dio_cfg = gw5904_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw5904_dio),
|
|
|
|
.mezz_pwren = IMX_GPIO_NR(2, 19),
|
|
|
|
.mezz_irq = IMX_GPIO_NR(2, 18),
|
2021-07-24 17:40:43 +00:00
|
|
|
.wdis = -1,
|
2019-02-04 21:10:57 +00:00
|
|
|
},
|
2021-07-24 17:40:42 +00:00
|
|
|
|
|
|
|
/* GW5910 */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw5910_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw5910_gpio_pads) / 2,
|
|
|
|
.dio_cfg = gw52xx_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw52xx_dio),
|
|
|
|
.wdis = IMX_GPIO_NR(7, 12),
|
|
|
|
.rs232_en = GP_RS232_EN,
|
|
|
|
.vsel_pin = IMX_GPIO_NR(6, 14),
|
|
|
|
.mmc_cd = IMX_GPIO_NR(7, 0),
|
|
|
|
},
|
2021-07-24 17:40:43 +00:00
|
|
|
|
|
|
|
/* GW5912 */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw5912_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw5912_gpio_pads) / 2,
|
|
|
|
.dio_cfg = gw54xx_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw54xx_dio),
|
|
|
|
.wdis = IMX_GPIO_NR(1, 0),
|
|
|
|
.rs232_en = GP_RS232_EN,
|
|
|
|
.vsel_pin = IMX_GPIO_NR(6, 14),
|
|
|
|
.mmc_cd = IMX_GPIO_NR(7, 0),
|
|
|
|
},
|
2021-07-24 17:40:44 +00:00
|
|
|
|
|
|
|
/* GW5913 */
|
|
|
|
{
|
|
|
|
.gpio_pads = gw5912_gpio_pads,
|
|
|
|
.num_pads = ARRAY_SIZE(gw5912_gpio_pads) / 2,
|
|
|
|
.dio_cfg = gw5913_dio,
|
|
|
|
.dio_num = ARRAY_SIZE(gw5913_dio),
|
|
|
|
.wdis = IMX_GPIO_NR(1, 0),
|
|
|
|
},
|
2015-05-09 01:28:35 +00:00
|
|
|
};
|
|
|
|
|
2019-02-04 21:10:50 +00:00
|
|
|
#define SETUP_GPIO_OUTPUT(gpio, name, level) \
|
|
|
|
gpio_request(gpio, name); \
|
|
|
|
gpio_direction_output(gpio, level);
|
|
|
|
#define SETUP_GPIO_INPUT(gpio, name) \
|
|
|
|
gpio_request(gpio, name); \
|
|
|
|
gpio_direction_input(gpio);
|
2015-05-09 01:28:35 +00:00
|
|
|
void setup_iomux_gpio(int board, struct ventana_board_info *info)
|
|
|
|
{
|
|
|
|
if (board >= GW_UNKNOWN)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* board specific iomux */
|
|
|
|
imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads,
|
|
|
|
gpio_cfg[board].num_pads);
|
|
|
|
|
2016-07-15 14:14:22 +00:00
|
|
|
/* RS232_EN# */
|
|
|
|
if (gpio_cfg[board].rs232_en) {
|
2017-03-13 15:51:05 +00:00
|
|
|
gpio_request(gpio_cfg[board].rs232_en, "rs232_en#");
|
2016-07-15 14:14:22 +00:00
|
|
|
gpio_direction_output(gpio_cfg[board].rs232_en, 0);
|
|
|
|
}
|
|
|
|
|
2016-05-24 18:03:56 +00:00
|
|
|
/* MSATA Enable - default to PCI */
|
|
|
|
if (gpio_cfg[board].msata_en) {
|
|
|
|
gpio_request(gpio_cfg[board].msata_en, "msata_en");
|
|
|
|
gpio_direction_output(gpio_cfg[board].msata_en, 0);
|
|
|
|
}
|
|
|
|
|
2015-05-09 01:28:35 +00:00
|
|
|
/* Expansion Mezzanine IO */
|
|
|
|
if (gpio_cfg[board].mezz_pwren) {
|
|
|
|
gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr");
|
|
|
|
gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
|
|
|
|
}
|
|
|
|
if (gpio_cfg[board].mezz_irq) {
|
|
|
|
gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#");
|
|
|
|
gpio_direction_input(gpio_cfg[board].mezz_irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* RS485 Transmit Enable */
|
|
|
|
if (gpio_cfg[board].rs485en) {
|
|
|
|
gpio_request(gpio_cfg[board].rs485en, "rs485_en");
|
|
|
|
gpio_direction_output(gpio_cfg[board].rs485en, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* GPS_SHDN */
|
|
|
|
if (gpio_cfg[board].gps_shdn) {
|
|
|
|
gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn");
|
|
|
|
gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* DIOI2C_DIS# */
|
|
|
|
if (gpio_cfg[board].dioi2c_en) {
|
|
|
|
gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#");
|
|
|
|
gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PCICK_SSON: disable spread-spectrum clock */
|
|
|
|
if (gpio_cfg[board].pcie_sson) {
|
|
|
|
gpio_request(gpio_cfg[board].pcie_sson, "pci_sson");
|
|
|
|
gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* USBOTG mux routing */
|
|
|
|
if (gpio_cfg[board].usb_sel) {
|
|
|
|
gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel");
|
|
|
|
gpio_direction_output(gpio_cfg[board].usb_sel, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
|
2021-07-24 17:40:43 +00:00
|
|
|
if (gpio_cfg[board].wdis != -1) {
|
2015-05-09 01:28:35 +00:00
|
|
|
gpio_request(gpio_cfg[board].wdis, "wlan_dis");
|
|
|
|
gpio_direction_output(gpio_cfg[board].wdis, 1);
|
|
|
|
}
|
2016-05-24 18:03:59 +00:00
|
|
|
|
|
|
|
/* sense vselect pin to see if we support uhs-i */
|
2017-03-13 15:51:08 +00:00
|
|
|
if (gpio_cfg[board].vsel_pin) {
|
|
|
|
gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect");
|
|
|
|
gpio_direction_input(gpio_cfg[board].vsel_pin);
|
|
|
|
gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin);
|
|
|
|
}
|
2017-03-17 14:30:38 +00:00
|
|
|
|
|
|
|
/* microSD CD */
|
|
|
|
if (gpio_cfg[board].mmc_cd) {
|
|
|
|
gpio_request(gpio_cfg[board].mmc_cd, "sd_cd");
|
|
|
|
gpio_direction_input(gpio_cfg[board].mmc_cd);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Anything else board specific */
|
|
|
|
switch(board) {
|
2021-07-24 17:40:45 +00:00
|
|
|
case GW53xx:
|
|
|
|
gpio_request(IMX_GPIO_NR(3, 15), "j6_pwren");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
|
|
|
|
gpio_request(IMX_GPIO_NR(3, 14), "gbe_en");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(3, 14), 1);
|
|
|
|
break;
|
2021-07-24 17:40:46 +00:00
|
|
|
case GW54xx:
|
|
|
|
gpio_request(IMX_GPIO_NR(3, 15), "j7_pwren");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
|
|
|
|
gpio_request(IMX_GPIO_NR(3, 14), "gbe_en");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(3, 14), 1);
|
|
|
|
break;
|
2017-03-17 14:31:02 +00:00
|
|
|
case GW560x:
|
|
|
|
gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
|
|
|
|
break;
|
2019-02-04 21:10:58 +00:00
|
|
|
case GW5902:
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "5P0V_EN", 1);
|
|
|
|
break;
|
2017-03-17 14:32:21 +00:00
|
|
|
case GW5903:
|
|
|
|
gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
|
|
|
|
gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
|
|
|
|
gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
|
|
|
|
gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
|
|
|
|
gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#");
|
|
|
|
gpio_direction_input(IMX_GPIO_NR(4, 6));
|
|
|
|
gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(4, 8), 1);
|
|
|
|
gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
|
|
|
|
break;
|
2019-02-04 21:10:57 +00:00
|
|
|
case GW5909:
|
2017-03-17 14:30:38 +00:00
|
|
|
case GW5904:
|
2019-02-04 21:10:59 +00:00
|
|
|
gpio_request(IMX_GPIO_NR(4, 23), "rs485_en");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(4, 23), 0);
|
2017-03-17 14:30:38 +00:00
|
|
|
gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
|
|
|
|
gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(5, 12), 1);
|
|
|
|
gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(5, 13), 1);
|
|
|
|
gpio_request(IMX_GPIO_NR(1, 15), "m2_off#");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
|
|
|
|
gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(1, 14), 1);
|
|
|
|
gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
|
|
|
|
break;
|
2019-02-04 21:10:50 +00:00
|
|
|
case GW5905:
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 7), "usb_pcisel", 0);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 9), "lvds_cabc", 1);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 14), "mipi_pdwn", 1);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 15), "mipi_rst#", 0);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(2, 3), "emmy_pdwn#", 1);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 5), "spk_shdn#", 0);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 0);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 6), "touch_irq", 0);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 5), "flash_en1", 0);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 6), "flash_en2", 0);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 14), "dect_rst#", 1);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 17), "codec_rst#", 0);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 26), "imu_den", 1);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "lvds_cabc", 0);
|
|
|
|
mdelay(100);
|
|
|
|
/*
|
|
|
|
* gauruntee touch controller comes out of reset with INT
|
|
|
|
* low for address
|
|
|
|
*/
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 1);
|
|
|
|
break;
|
2021-07-24 17:40:42 +00:00
|
|
|
case GW5910:
|
|
|
|
/* CC1352 */
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 7), "rf_reset#", 1);
|
|
|
|
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 8), "rf_boot", 1);
|
|
|
|
break;
|
2017-03-17 14:30:38 +00:00
|
|
|
}
|
2015-05-09 01:28:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* setup GPIO pinmux and default configuration per baseboard and env */
|
|
|
|
void setup_board_gpio(int board, struct ventana_board_info *info)
|
|
|
|
{
|
|
|
|
const char *s;
|
|
|
|
char arg[10];
|
|
|
|
size_t len;
|
|
|
|
int i;
|
2017-08-03 18:22:12 +00:00
|
|
|
int quiet = simple_strtol(env_get("quiet"), NULL, 10);
|
2015-05-09 01:28:35 +00:00
|
|
|
|
|
|
|
if (board >= GW_UNKNOWN)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* RS232_EN# */
|
2016-07-15 14:14:22 +00:00
|
|
|
if (gpio_cfg[board].rs232_en) {
|
|
|
|
gpio_direction_output(gpio_cfg[board].rs232_en,
|
|
|
|
(hwconfig("rs232")) ? 0 : 1);
|
|
|
|
}
|
2015-05-09 01:28:35 +00:00
|
|
|
|
|
|
|
/* MSATA Enable */
|
2016-05-24 18:03:56 +00:00
|
|
|
if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
|
2015-05-09 01:28:35 +00:00
|
|
|
gpio_direction_output(GP_MSATA_SEL,
|
2016-05-24 18:03:56 +00:00
|
|
|
(hwconfig("msata")) ? 1 : 0);
|
2015-05-09 01:28:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* USBOTG Select (PCISKT or FrontPanel) */
|
|
|
|
if (gpio_cfg[board].usb_sel) {
|
|
|
|
gpio_direction_output(gpio_cfg[board].usb_sel,
|
|
|
|
(hwconfig("usb_pcisel")) ? 1 : 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure DIO pinmux/padctl registers
|
|
|
|
* see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
|
|
|
|
*/
|
2016-07-15 14:14:23 +00:00
|
|
|
for (i = 0; i < gpio_cfg[board].dio_num; i++) {
|
2015-05-09 01:28:35 +00:00
|
|
|
struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
|
|
|
|
iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
|
|
|
|
unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
|
|
|
|
|
|
|
|
if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
|
|
|
|
continue;
|
|
|
|
sprintf(arg, "dio%d", i);
|
|
|
|
if (!hwconfig(arg))
|
|
|
|
continue;
|
|
|
|
s = hwconfig_subarg(arg, "padctrl", &len);
|
|
|
|
if (s) {
|
2021-07-24 15:03:29 +00:00
|
|
|
ctrl = MUX_PAD_CTRL(hextoul(s, NULL)
|
2015-05-09 01:28:35 +00:00
|
|
|
& 0x1ffff) | MUX_MODE_SION;
|
|
|
|
}
|
|
|
|
if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
|
|
|
|
if (!quiet) {
|
|
|
|
printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
|
|
|
|
(cfg->gpio_param/32)+1,
|
|
|
|
cfg->gpio_param%32,
|
|
|
|
cfg->gpio_param);
|
|
|
|
}
|
|
|
|
imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
|
|
|
|
ctrl);
|
|
|
|
gpio_requestf(cfg->gpio_param, "dio%d", i);
|
|
|
|
gpio_direction_input(cfg->gpio_param);
|
2016-05-24 18:03:54 +00:00
|
|
|
} else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
|
2015-05-09 01:28:35 +00:00
|
|
|
cfg->pwm_padmux) {
|
2016-05-24 18:03:55 +00:00
|
|
|
if (!cfg->pwm_param) {
|
|
|
|
printf("DIO%d: Error: pwm config invalid\n",
|
|
|
|
i);
|
|
|
|
continue;
|
|
|
|
}
|
2015-05-09 01:28:35 +00:00
|
|
|
if (!quiet)
|
|
|
|
printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
|
|
|
|
imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
|
|
|
|
MUX_PAD_CTRL(ctrl));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!quiet) {
|
2016-05-24 18:03:56 +00:00
|
|
|
if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
|
2015-05-09 01:28:35 +00:00
|
|
|
printf("MSATA: %s\n", (hwconfig("msata") ?
|
|
|
|
"enabled" : "disabled"));
|
|
|
|
}
|
2016-07-15 14:14:22 +00:00
|
|
|
if (gpio_cfg[board].rs232_en) {
|
|
|
|
printf("RS232: %s\n", (hwconfig("rs232")) ?
|
|
|
|
"enabled" : "disabled");
|
|
|
|
}
|
2015-05-09 01:28:35 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-07-24 17:40:32 +00:00
|
|
|
#include <fdt_support.h>
|
|
|
|
#define WDOG1_ADDR 0x20bc000
|
|
|
|
#define WDOG2_ADDR 0x20c0000
|
|
|
|
#define GPIO3_ADDR 0x20a4000
|
|
|
|
#define USDHC3_ADDR 0x2198000
|
|
|
|
|
|
|
|
static void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
|
|
|
|
{
|
|
|
|
int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
|
|
|
|
|
|
|
|
if (off) {
|
|
|
|
fdt_delprop(blob, off, "ext-reset-output");
|
|
|
|
fdt_delprop(blob, off, "fsl,ext-reset-output");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void ft_early_fixup(void *blob, int board_type)
|
|
|
|
{
|
|
|
|
struct ventana_board_info *info = &ventana_info;
|
|
|
|
char rev = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* determine board revision */
|
|
|
|
for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
|
|
|
|
if (ventana_info.model[i] >= 'A') {
|
|
|
|
rev = ventana_info.model[i];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Board model specific fixups
|
|
|
|
*/
|
|
|
|
switch (board_type) {
|
|
|
|
case GW51xx:
|
|
|
|
/*
|
|
|
|
* disable wdog node for GW51xx-A/B to work around
|
|
|
|
* errata causing wdog timer to be unreliable.
|
|
|
|
*/
|
|
|
|
if (rev >= 'A' && rev < 'C') {
|
|
|
|
i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
|
|
|
|
WDOG1_ADDR);
|
|
|
|
if (i)
|
|
|
|
fdt_status_disabled(blob, i);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* GW51xx-E adds WDOG1_B external reset */
|
|
|
|
if (rev < 'E')
|
|
|
|
ft_board_wdog_fixup(blob, WDOG1_ADDR);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case GW52xx:
|
|
|
|
/* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
|
|
|
|
if (info->model[4] == '2') {
|
|
|
|
u32 handle = 0;
|
|
|
|
u32 *range = NULL;
|
|
|
|
|
|
|
|
i = fdt_node_offset_by_compatible(blob, -1,
|
|
|
|
"fsl,imx6q-pcie");
|
|
|
|
if (i)
|
|
|
|
range = (u32 *)fdt_getprop(blob, i,
|
|
|
|
"reset-gpio", NULL);
|
|
|
|
|
|
|
|
if (range) {
|
|
|
|
i = fdt_node_offset_by_compat_reg(blob,
|
|
|
|
"fsl,imx6q-gpio", GPIO3_ADDR);
|
|
|
|
if (i)
|
|
|
|
handle = fdt_get_phandle(blob, i);
|
|
|
|
if (handle) {
|
|
|
|
range[0] = cpu_to_fdt32(handle);
|
|
|
|
range[1] = cpu_to_fdt32(23);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* these have broken usd_vsel */
|
|
|
|
if (strstr((const char *)info->model, "SP318-B") ||
|
|
|
|
strstr((const char *)info->model, "SP331-B"))
|
|
|
|
gpio_cfg[board_type].usd_vsel = 0;
|
|
|
|
|
|
|
|
/* GW522x-B adds WDOG1_B external reset */
|
|
|
|
if (rev < 'B')
|
|
|
|
ft_board_wdog_fixup(blob, WDOG1_ADDR);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* GW520x-E adds WDOG1_B external reset */
|
|
|
|
else if (info->model[4] == '0' && rev < 'E')
|
|
|
|
ft_board_wdog_fixup(blob, WDOG1_ADDR);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case GW53xx:
|
|
|
|
/* GW53xx-E adds WDOG1_B external reset */
|
|
|
|
if (rev < 'E')
|
|
|
|
ft_board_wdog_fixup(blob, WDOG1_ADDR);
|
2021-07-24 17:40:45 +00:00
|
|
|
|
|
|
|
/* GW53xx-G has an adv7280 instead of an adv7180 */
|
|
|
|
else if (rev > 'F') {
|
|
|
|
i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
|
|
|
|
if (i) {
|
|
|
|
fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
|
|
|
|
fdt_setprop_empty(blob, i, "adv,force-bt656-4");
|
|
|
|
}
|
|
|
|
}
|
2021-07-24 17:40:32 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case GW54xx:
|
|
|
|
/*
|
|
|
|
* disable serial2 node for GW54xx for compatibility with older
|
|
|
|
* 3.10.x kernel that improperly had this node enabled in the DT
|
|
|
|
*/
|
2021-11-26 13:57:08 +00:00
|
|
|
fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED);
|
2021-07-24 17:40:32 +00:00
|
|
|
|
|
|
|
/* GW54xx-E adds WDOG2_B external reset */
|
|
|
|
if (rev < 'E')
|
|
|
|
ft_board_wdog_fixup(blob, WDOG2_ADDR);
|
2021-07-24 17:40:46 +00:00
|
|
|
|
|
|
|
/* GW54xx-G has an adv7280 instead of an adv7180 */
|
|
|
|
else if (rev > 'F') {
|
|
|
|
i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
|
|
|
|
if (i) {
|
|
|
|
fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
|
|
|
|
fdt_setprop_empty(blob, i, "adv,force-bt656-4");
|
|
|
|
}
|
|
|
|
}
|
2021-07-24 17:40:32 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case GW551x:
|
|
|
|
/* GW551x-C adds WDOG1_B external reset */
|
|
|
|
if (rev < 'C')
|
|
|
|
ft_board_wdog_fixup(blob, WDOG1_ADDR);
|
|
|
|
break;
|
|
|
|
case GW5901:
|
|
|
|
case GW5902:
|
|
|
|
/* GW5901/GW5901 revB adds WDOG1_B as an external reset */
|
|
|
|
if (rev < 'B')
|
|
|
|
ft_board_wdog_fixup(blob, WDOG1_ADDR);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* remove no-1-8-v if UHS-I support is present */
|
|
|
|
if (gpio_cfg[board_type].usd_vsel) {
|
|
|
|
debug("Enabling UHS-I support\n");
|
|
|
|
i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
|
|
|
|
USDHC3_ADDR);
|
|
|
|
if (i)
|
|
|
|
fdt_delprop(blob, i, "no-1-8-v");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-06-21 03:42:28 +00:00
|
|
|
#ifdef CONFIG_FSL_ESDHC_IMX
|
2017-03-17 14:31:02 +00:00
|
|
|
static struct fsl_esdhc_cfg usdhc_cfg[2];
|
2017-03-13 15:51:03 +00:00
|
|
|
|
2020-06-26 06:13:33 +00:00
|
|
|
int board_mmc_init(struct bd_info *bis)
|
2017-03-13 15:51:03 +00:00
|
|
|
{
|
2017-03-17 14:30:38 +00:00
|
|
|
struct ventana_board_info ventana_info;
|
|
|
|
int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (board_type) {
|
|
|
|
case GW52xx:
|
|
|
|
case GW53xx:
|
|
|
|
case GW54xx:
|
|
|
|
case GW553x:
|
2021-07-24 17:40:42 +00:00
|
|
|
case GW5910:
|
2021-07-24 17:40:43 +00:00
|
|
|
case GW5912:
|
2017-03-17 14:30:38 +00:00
|
|
|
/* usdhc3: 4bit microSD */
|
|
|
|
SETUP_IOMUX_PADS(usdhc3_pads);
|
2017-03-17 14:31:02 +00:00
|
|
|
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
|
|
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
|
|
usdhc_cfg[0].max_bus_width = 4;
|
|
|
|
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
|
|
|
case GW560x:
|
|
|
|
/* usdhc2: 8-bit eMMC */
|
|
|
|
SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads);
|
|
|
|
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
|
|
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
|
|
usdhc_cfg[0].max_bus_width = 8;
|
|
|
|
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
/* usdhc3: 4-bit microSD */
|
|
|
|
SETUP_IOMUX_PADS(usdhc3_pads);
|
|
|
|
usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
|
|
|
|
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
|
|
usdhc_cfg[1].max_bus_width = 4;
|
|
|
|
return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
|
2017-03-17 14:32:21 +00:00
|
|
|
case GW5903:
|
|
|
|
/* usdhc3: 8-bit eMMC */
|
|
|
|
SETUP_IOMUX_PADS(gw5904_emmc_pads);
|
|
|
|
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
|
|
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
|
|
usdhc_cfg[0].max_bus_width = 8;
|
|
|
|
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
/* usdhc2: 4-bit microSD */
|
|
|
|
SETUP_IOMUX_PADS(gw5904_mmc_pads);
|
|
|
|
usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
|
|
|
|
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
|
|
usdhc_cfg[1].max_bus_width = 4;
|
|
|
|
return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
|
2017-03-17 14:30:38 +00:00
|
|
|
case GW5904:
|
2019-02-04 21:10:50 +00:00
|
|
|
case GW5905:
|
2019-02-04 21:10:57 +00:00
|
|
|
case GW5909:
|
2017-03-17 14:30:38 +00:00
|
|
|
/* usdhc3: 8bit eMMC */
|
|
|
|
SETUP_IOMUX_PADS(gw5904_emmc_pads);
|
2017-03-17 14:31:02 +00:00
|
|
|
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
|
|
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
|
|
usdhc_cfg[0].max_bus_width = 8;
|
|
|
|
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
2017-03-17 14:30:38 +00:00
|
|
|
default:
|
|
|
|
/* doesn't have MMC */
|
2021-06-11 19:46:28 +00:00
|
|
|
printf("None");
|
2017-03-17 14:30:38 +00:00
|
|
|
return -1;
|
|
|
|
}
|
2017-03-13 15:51:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int board_mmc_getcd(struct mmc *mmc)
|
|
|
|
{
|
2017-03-17 14:30:38 +00:00
|
|
|
struct ventana_board_info ventana_info;
|
|
|
|
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
|
|
|
int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
|
|
|
|
int gpio = gpio_cfg[board].mmc_cd;
|
|
|
|
|
2017-03-13 15:51:03 +00:00
|
|
|
/* Card Detect */
|
2017-03-17 14:30:38 +00:00
|
|
|
switch (board) {
|
2017-03-17 14:31:02 +00:00
|
|
|
case GW560x:
|
|
|
|
/* emmc is always present */
|
|
|
|
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
|
|
|
|
return 1;
|
|
|
|
break;
|
2017-03-17 14:32:21 +00:00
|
|
|
case GW5903:
|
2017-03-17 14:30:38 +00:00
|
|
|
case GW5904:
|
2019-02-04 21:10:50 +00:00
|
|
|
case GW5905:
|
2019-02-04 21:10:57 +00:00
|
|
|
case GW5909:
|
2017-03-17 14:30:38 +00:00
|
|
|
/* emmc is always present */
|
|
|
|
if (cfg->esdhc_base == USDHC3_BASE_ADDR)
|
|
|
|
return 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (gpio) {
|
|
|
|
debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio));
|
|
|
|
return !gpio_get_value(gpio);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -1;
|
2017-03-13 15:51:03 +00:00
|
|
|
}
|
2017-03-17 14:30:38 +00:00
|
|
|
|
2019-06-21 03:42:28 +00:00
|
|
|
#endif /* CONFIG_FSL_ESDHC_IMX */
|