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u-boot/arch/arm/cpu/armv8/Kconfig

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armv8/vexpress64: make multientry conditional While the Freescale ARMv8 board LS2085A will enter U-Boot both on a master and a secondary (slave) CPU, this is not the common behaviour on ARMv8 platforms. The norm is that U-Boot is entered from the master CPU only, while the other CPUs are kept in WFI (wait for interrupt) state. The code determining which CPU we are running on is using the MPIDR register, but the definition of that register varies with platform to some extent, and handling multi-cluster platforms (such as the Juno) will become cumbersome. It is better to only enable the multiple entry code on machines that actually need it and disable it by default. Make the single entry default and add a special ARMV8_MULTIENTRY KConfig option to be used by the platforms that need multientry and set it for the LS2085A. Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 boards as it is just totally unused and misleading, and make it conditional in the generic start.S code. This makes the Juno platform start U-Boot properly. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 09:53:21 +00:00
if ARM64
arm: cpu: Add optional CMOs by VA Exposing set/way cache maintenance to a virtual machine is unsafe, not least because the instructions are not permission-checked but also because they are not broadcast between CPUs. Consequently, KVM traps and emulates such maintenance in the host kernel using by-VA operations and looping over the stage-2 page-tables. However, when running under protected KVM, these instructions are not able to be emulated and will instead result in an exception being delivered to the guest. Introduce CONFIG_CMO_BY_VA_ONLY so that virtual platforms can select this option and perform by-VA cache maintenance instead of using the set/way instructions. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Will Deacon <willdeacon@google.com> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com> [ Paul: pick from the Android tree. Fixup Pierre's commit. And fix some checkpatch warnings. Rebased to upstream. ] Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Link: https://android.googlesource.com/platform/external/u-boot/+/db5507f47f4f57f766d52f753ff2cc761afc213b Link: https://android.googlesource.com/platform/external/u-boot/+/2baf54e743380a1e4a6bc2dbdde020a2e783ff67
2023-02-08 20:54:27 +00:00
config CMO_BY_VA_ONLY
bool "Force cache maintenance to be exclusively by VA"
depends on !SYS_DISABLE_DCACHE_OPS
armv8: make SPL exception vectors optional Even though the exception vector table is a fundamental part of the ARM architecture, U-Boot mostly does not make real use of it, except when crash dumping. But having it in takes up quite some space, partly due to the architectural alignment requirement of 2KB. Since we don't take special care of that, the compiler adds a more or less random amount of padding space, which increases the image size quite a bit, especially for the SPL. On a typical Allwinner build this is around 1.5KB of padding, plus 1KB for the vector table (mostly padding space again), then some extra code to do the actual handling. This amounts to almost 10% of the maximum image size, which is quite a lot for a pure debugging feature. Add a Kconfig symbol to allow the exception vector table to be left out of the build for the SPL. For now this is "default y" for everyone, but specific defconfigs, platforms or .config files can opt out here at will, to mitigate the code size pressure we see for some SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-07-24 23:57:01 +00:00
config ARMV8_SPL_EXCEPTION_VECTORS
bool "Install crash dump exception vectors"
depends on SPL
help
The default exception vector table is only used for the crash
dump, but still takes quite a lot of space in the image size.
Say N here if you are running out of code space in the image
and want to save some space at the cost of less debugging info.
armv8/vexpress64: make multientry conditional While the Freescale ARMv8 board LS2085A will enter U-Boot both on a master and a secondary (slave) CPU, this is not the common behaviour on ARMv8 platforms. The norm is that U-Boot is entered from the master CPU only, while the other CPUs are kept in WFI (wait for interrupt) state. The code determining which CPU we are running on is using the MPIDR register, but the definition of that register varies with platform to some extent, and handling multi-cluster platforms (such as the Juno) will become cumbersome. It is better to only enable the multiple entry code on machines that actually need it and disable it by default. Make the single entry default and add a special ARMV8_MULTIENTRY KConfig option to be used by the platforms that need multientry and set it for the LS2085A. Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 boards as it is just totally unused and misleading, and make it conditional in the generic start.S code. This makes the Juno platform start U-Boot properly. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 09:53:21 +00:00
config ARMV8_MULTIENTRY
kconfig: use bool instead of boolean for type definition attributes Linux stopped the use of keyword 'boolean' in Kconfig. Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig: use bool instead of boolean for type definition attributes") in Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-12 01:26:50 +00:00
bool "Enable multiple CPUs to enter into U-Boot"
armv8/vexpress64: make multientry conditional While the Freescale ARMv8 board LS2085A will enter U-Boot both on a master and a secondary (slave) CPU, this is not the common behaviour on ARMv8 platforms. The norm is that U-Boot is entered from the master CPU only, while the other CPUs are kept in WFI (wait for interrupt) state. The code determining which CPU we are running on is using the MPIDR register, but the definition of that register varies with platform to some extent, and handling multi-cluster platforms (such as the Juno) will become cumbersome. It is better to only enable the multiple entry code on machines that actually need it and disable it by default. Make the single entry default and add a special ARMV8_MULTIENTRY KConfig option to be used by the platforms that need multientry and set it for the LS2085A. Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 boards as it is just totally unused and misleading, and make it conditional in the generic start.S code. This makes the Juno platform start U-Boot properly. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 09:53:21 +00:00
armv8: Enable CPUECTLR.SMPEN for coherency For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the cache is not coherent with other cores and data corruption could occur. For A57/A72, SMPEN bit enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster. This bit should be set before enabling the caches and MMU, or performing any cache and TLB maintenance operations. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-06 09:41:10 +00:00
config ARMV8_SET_SMPEN
bool "Enable data coherency with other cores in cluster"
help
Say Y here if there is not any trust firmware to set
CPUECTLR_EL1.SMPEN bit before U-Boot.
For A53, it enables data coherency with other cores in the
cluster, and for A57/A72, it enables receiving of instruction
cache and TLB maintenance operations.
Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
for single core systems. Unfortunately write access to this
register may be controlled by EL3/EL2 firmware. To be more
precise, by default (if there is EL2/EL3 firmware running)
this register is RO for NS EL1.
This switch can be used to avoid writing to CPUECTLR_EL1,
it can be safely enabled when EL2/EL3 initialized SMPEN bit
or when CPU implementation doesn't include that register.
Convert CONFIG_ARMV8_SWITCH_TO_EL1 to Kconfig This converts the following to Kconfig: CONFIG_ARMV8_SWITCH_TO_EL1 Cc: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2022-03-11 14:11:58 +00:00
config ARMV8_SWITCH_TO_EL1
bool "Enable switching to running in EL1"
help
In some circumstances we need to switch to running in EL1.
Enable this option to have U-Boot switch to EL1.
arm64: add better and more generic spin-table support There are two enable methods supported by ARM64 Linux; psci and spin-table. The latter is simpler and helpful for quick SoC bring up. My main motivation for this patch is to improve the spin-table support, which allows us to boot an ARMv8 system without the ARM Trusted Firmware. Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S and the spin-table is supported in a really ad-hoc way, and I see some problems: - We must hard-code CPU_RELEASE_ADDR so that it matches the "cpu-release-addr" property in the DT that comes from the kernel tree. - The Documentation/arm64/booting.txt in Linux requires that the release address must be zero-initialized, but it is not cared by the common code in U-Boot. We must do it in a board function. - There is no systematic way to protect the spin-table code from the kernel. We are supposed to do it in a board specific manner, but it is difficult to predict where the spin-table code will be located after the relocation. So, it also makes difficult to hard-code /memreserve/ in the DT of the kernel. So, here is a patch to solve those problems; the DT is run-time modified to reserve the spin-table code (+ cpu-release-addr). Also, the "cpu-release-addr" property is set to an appropriate address after the relocation, which means we no longer need the hard-coded CPU_RELEASE_ADDR. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-27 10:31:05 +00:00
config ARMV8_SPIN_TABLE
bool "Support spin-table enable method"
depends on ARMV8_MULTIENTRY && OF_LIBFDT
help
Say Y here to support "spin-table" enable method for booting Linux.
To use this feature, you must do:
- Specify enable-method = "spin-table" in each CPU node in the
Device Tree you are using to boot the kernel
arm64: spin-table: add more information in Kconfig help This feature seems to be sometimes misunderstood. The intention is: [1] Bring the slaves into the U-Boot proper image, not SPL (unless you have a special reason to do otherwise). [2] The operation must be done in a board (SoC) specific manner since how to wake the slaves from the Boot ROM is SoC specific. [3] The slaves must enter U-Boot proper after U-Boot relocates itself because the "cpu-release-addr" property points to the relocated memory area. [2] is already explained in the help. We can make [1] even clearer by mentioning "U-Boot proper" instead of "U-Boot". [3] is missing, so I am adding it to the list. Instead, "before the master CPU jumps to the kernel" is a matter of course, so removed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-20 09:04:43 +00:00
- Bring secondary CPUs into U-Boot proper in a board specific
manner. This must be done *after* relocation. Otherwise, the
secondary CPUs will spin in unprotected memory area because the
master CPU protects the relocated spin code.
arm64: add better and more generic spin-table support There are two enable methods supported by ARM64 Linux; psci and spin-table. The latter is simpler and helpful for quick SoC bring up. My main motivation for this patch is to improve the spin-table support, which allows us to boot an ARMv8 system without the ARM Trusted Firmware. Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S and the spin-table is supported in a really ad-hoc way, and I see some problems: - We must hard-code CPU_RELEASE_ADDR so that it matches the "cpu-release-addr" property in the DT that comes from the kernel tree. - The Documentation/arm64/booting.txt in Linux requires that the release address must be zero-initialized, but it is not cared by the common code in U-Boot. We must do it in a board function. - There is no systematic way to protect the spin-table code from the kernel. We are supposed to do it in a board specific manner, but it is difficult to predict where the spin-table code will be located after the relocation. So, it also makes difficult to hard-code /memreserve/ in the DT of the kernel. So, here is a patch to solve those problems; the DT is run-time modified to reserve the spin-table code (+ cpu-release-addr). Also, the "cpu-release-addr" property is set to an appropriate address after the relocation, which means we no longer need the hard-coded CPU_RELEASE_ADDR. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-27 10:31:05 +00:00
U-Boot automatically does:
- Set "cpu-release-addr" property of each CPU node
(overwrites it if already exists).
- Reserve the code for the spin-table and the release address
via a /memreserve/ region in the Device Tree.
kconfig: armv8: move armv8 sec_firmware CONFIG_* to Kconfig Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York S: clean up scripts/config_whitelist.txt] Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-16 09:31:47 +00:00
menu "ARMv8 secure monitor firmware"
config ARMV8_SEC_FIRMWARE_SUPPORT
bool "Enable ARMv8 secure monitor firmware framework support"
select FIT
Kconfig: Sort bool, default, select and imply options Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-23 13:55:15 +00:00
select OF_LIBFDT
kconfig: armv8: move armv8 sec_firmware CONFIG_* to Kconfig Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York S: clean up scripts/config_whitelist.txt] Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-16 09:31:47 +00:00
help
This framework is aimed at making secure monitor firmware load
process brief.
Note: Only FIT format image is supported.
You should prepare and provide the below information:
- Address of secure firmware.
- Address to hold the return address from secure firmware.
- Secure firmware FIT image related information.
Fix typo in macros, "FIRMEWARE" -> "FIRMWARE" Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2019-11-10 16:23:15 +00:00
Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMWARE_FIT_CNF_NAME
kconfig: armv8: move armv8 sec_firmware CONFIG_* to Kconfig Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York S: clean up scripts/config_whitelist.txt] Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-16 09:31:47 +00:00
- The target exception level that secure monitor firmware will
return to.
config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
bool "Enable ARMv8 secure monitor firmware framework support for SPL"
spl: Ensure all SPL symbols in Kconfig have some SPL dependency Tighten up symbol dependencies in a number of places. Ensure that a SPL specific option has at least a direct dependency on SPL. In places where it's clear that we depend on something more specific, use that dependency instead. This means in a very small number of places we can drop redundant dependencies. Reported-by: Pali Rohár <pali@kernel.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-11 03:03:09 +00:00
depends on SPL
kconfig: armv8: move armv8 sec_firmware CONFIG_* to Kconfig Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York S: clean up scripts/config_whitelist.txt] Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-16 09:31:47 +00:00
select SPL_FIT
Kconfig: Sort bool, default, select and imply options Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-23 13:55:15 +00:00
select SPL_OF_LIBFDT
kconfig: armv8: move armv8 sec_firmware CONFIG_* to Kconfig Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York S: clean up scripts/config_whitelist.txt] Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-16 09:31:47 +00:00
help
Say Y here to support this framework in SPL phase.
imx: imx8qm/qxp: Recover SPL data section for partition reboot When doing partition reboot, the boot image won't be reloaded by ROM, it is just CPU reset to boot entry. The SW has to keep the boot image inside the RAM unchanged. It includes both the TEXT section and DATA section. For SPL, the problem is DATA section will be updated at runtime, so in next partition reboot the data is not same as the initial value from cold boot. If any code depends on the initial value, then it will have problem. This patch introduces a mechanism to recover the data section for partition reboot. It adds a new section in image for saving data section. When from cold boot, the data section will be saved to that new section at SPL early phase. When from partition reboot, the data section will be restored from the new section. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-05 12:28:41 +00:00
config SPL_RECOVER_DATA_SECTION
bool "save/restore SPL data section"
spl: Ensure all SPL symbols in Kconfig have some SPL dependency Tighten up symbol dependencies in a number of places. Ensure that a SPL specific option has at least a direct dependency on SPL. In places where it's clear that we depend on something more specific, use that dependency instead. This means in a very small number of places we can drop redundant dependencies. Reported-by: Pali Rohár <pali@kernel.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-11 03:03:09 +00:00
depends on SPL
imx: imx8qm/qxp: Recover SPL data section for partition reboot When doing partition reboot, the boot image won't be reloaded by ROM, it is just CPU reset to boot entry. The SW has to keep the boot image inside the RAM unchanged. It includes both the TEXT section and DATA section. For SPL, the problem is DATA section will be updated at runtime, so in next partition reboot the data is not same as the initial value from cold boot. If any code depends on the initial value, then it will have problem. This patch introduces a mechanism to recover the data section for partition reboot. It adds a new section in image for saving data section. When from cold boot, the data section will be saved to that new section at SPL early phase. When from partition reboot, the data section will be restored from the new section. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-05 12:28:41 +00:00
help
Say Y here to save SPL data section for cold boot, and restore
at warm boot in SPL phase.
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-16 09:31:48 +00:00
config SEC_FIRMWARE_ARMV8_PSCI
bool "PSCI implementation in secure monitor firmware"
depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
armv8: psci: add ARMV8_PSCI_RELOCATE Kconfig option There is an user-selectable SYS_HAS_ARMV8_SECURE_BASE, which has the same meaning but is just for the ls1043ardb board. As no in-tree config uses this, drop it and replace it with something more sophiticated: ARMV8_PSCI_RELOCATE. This option will then enable the ARMV8_SECURE_BASE option which is used as the base to relocate the PSCI code (or any code in the secure region, but that is only PSCI). A SoC (or board) can now opt-in into having such a secure region by enabling SYS_HAS_ARMV8_SECURE_BASE. Enable it for the LS1043A SoC, where it was possible to relocate the PSCI code before as well as on the LS1028A SoC where there will be PSCI support soon. Additionally, make ARMV8_PSCI and SEC_FIRMWARE_ARMV8_PSCI exclusive. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-28 12:48:40 +00:00
depends on ARMV8_PSCI=n
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-16 09:31:48 +00:00
help
This config enables the ARMv8 PSCI implementation in secure monitor
firmware. This is a private PSCI implementation and different from
those implemented under the common ARMv8 PSCI framework.
kconfig: armv8: move armv8 sec_firmware CONFIG_* to Kconfig Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York S: clean up scripts/config_whitelist.txt] Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-16 09:31:47 +00:00
config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
bool "ARMv8 secure monitor firmware ERET address byteorder swap"
depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
help
Say Y here when the endianness of the register or memory holding the
Secure firmware exception return address is different with core's.
endmenu
arm: Provide common PSCI based reset handler Most armv8 systems have PSCI support enabled in EL3, either through ARM Trusted Firmware or other firmware. On these systems, we do not need to implement system reset manually, but can instead rely on higher level firmware to deal with it. The exclude list seems excessive right now, but NXP is working on providing an in-tree PSCI implementation, so that all NXP systems can eventually use PSCI as well. Signed-off-by: Alexander Graf <agraf@suse.de> [agraf: fix meson] Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-16 19:08:48 +00:00
config PSCI_RESET
bool "Use PSCI for reset and shutdown"
default y
efi_loader: PSCI reset and shutdown When an operating system started via bootefi tries to reset or power off this is done by calling the EFI runtime ResetSystem(). On most ARMv8 system the actual reset relies on PSCI. Depending on whether the PSCI firmware resides the hypervisor (EL2) or in the secure monitor (EL3) either an HVC or an SMC command has to be issued. The current implementation always uses SMC. This results in crashes on systems where the PSCI firmware is implemented in the hypervisor, e.g. qemu-arm64_defconfig. The logic to decide which call is needed based on the device tree is already implemented in the PSCI firmware driver. During the EFI runtime the device driver model is not available. But we can minimize code duplication by merging the EFI runtime reset and poweroff code with the PSCI firmware driver. As the same HVC/SMC problem is also evident for the ARMv8 do_poweroff and reset_misc routines let's move them into the same code module. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-10-18 10:29:40 +00:00
select ARM_SMCCC if OF_CONTROL
armv8: apple: Disable PSCI reset Apple's ARMv8 cores don't implement EL3 and therefore don't provide a PSCI implementation. So don't attempt to use PSCI to reset on machines using Apple SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2021-12-21 16:31:50 +00:00
depends on !ARCH_APPLE && !ARCH_BCM283X && !ARCH_EXYNOS7 && \
arm: Remove ls2080a_simu board This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it. Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-09 13:03:10 +00:00
!TARGET_LS2080AQDS && \
armv8/kconfig: Align boards of same family at one place Align boards belonging to LS1012A, LS2080A SoC at one place. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-11 14:33:30 +00:00
!TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
armv8: ls1088aqds: Add support of LS1088AQDS This patch add support of LS1088AQDS platform. The LS1088A QorIQTM Development System (QDS) is a high-performance computing, evaluation, and development platform that supports the LS1088A QorIQ Architecture processor. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:55 +00:00
!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
arm: Provide common PSCI based reset handler Most armv8 systems have PSCI support enabled in EL3, either through ARM Trusted Firmware or other firmware. On these systems, we do not need to implement system reset manually, but can instead rely on higher level firmware to deal with it. The exclude list seems excessive right now, but NXP is working on providing an in-tree PSCI implementation, so that all NXP systems can eventually use PSCI as well. Signed-off-by: Alexander Graf <agraf@suse.de> [agraf: fix meson] Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-16 19:08:48 +00:00
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
board: ls1012a: LS1012A-2G5RDB board support LS1012A-2G5RDB belongs to LS1012A family with features 2 2.5G SGMII PFE MAC, SATA, USB 2.0/3.0, WiFi DDR, eMMC, QuadSPI, UART. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-11 14:33:31 +00:00
!TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
board: ls1012a: FRWY-LS1012A board support FRWY-LS1012A belongs to LS1012A family with features 2 1G SGMII PFE MAC, Micro SD, USB 3.0, DDR, QuadSPI, Audio, UART. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> [yorks: rebase and fix SPDX tag] [yorks: fix board/freescale/ls1012afrdm/Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-23 05:33:30 +00:00
!TARGET_LS1012AFRWY && \
armv8: ls1028aqds: Add support of LS1028AQDS LS1028AQDS Development System is a high-performance computing, evaluation, and development platform that supports LS1028A QorIQ Architecture processor. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-10 08:43:35 +00:00
!TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
efi_loader: Disable PSCI reset for ls1043 and ls1046 The NXP ls1043 and ls1046 systems do not (yet) have PSCI enablement for reset. Don't enable generic PSCI reset code on them. Signed-off-by: Alexander Graf <agraf@suse.de>
2016-11-17 00:02:55 +00:00
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
armv8: ls1046afrwy: Add support for LS1046AFRWY platform LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-06 12:35:28 +00:00
!TARGET_LS1046AFRWY && \
armv8: lx2160ardb : Add support for LX2160ARDB platform LX2160ARDB is an evaluation board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [PK: Sqaush patches from Yinbo Zhu, Peng Ma, Chuanhua Han and re-arrange defconfig] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2018-11-28 13:04:27 +00:00
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-29 13:46:16 +00:00
!TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
arm: Remove s32v234evb board This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-02-21 01:05:49 +00:00
!ARCH_UNIPHIER
arm: Provide common PSCI based reset handler Most armv8 systems have PSCI support enabled in EL3, either through ARM Trusted Firmware or other firmware. On these systems, we do not need to implement system reset manually, but can instead rely on higher level firmware to deal with it. The exclude list seems excessive right now, but NXP is working on providing an in-tree PSCI implementation, so that all NXP systems can eventually use PSCI as well. Signed-off-by: Alexander Graf <agraf@suse.de> [agraf: fix meson] Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-16 19:08:48 +00:00
help
Most armv8 systems have PSCI support enabled in EL3, either through
ARM Trusted Firmware or other firmware.
On these systems, we do not need to implement system reset manually,
but can instead rely on higher level firmware to deal with it.
Select Y here to make use of PSCI calls for system reset
armv8: psci: add ARMV8_PSCI_RELOCATE Kconfig option There is an user-selectable SYS_HAS_ARMV8_SECURE_BASE, which has the same meaning but is just for the ls1043ardb board. As no in-tree config uses this, drop it and replace it with something more sophiticated: ARMV8_PSCI_RELOCATE. This option will then enable the ARMV8_SECURE_BASE option which is used as the base to relocate the PSCI code (or any code in the secure region, but that is only PSCI). A SoC (or board) can now opt-in into having such a secure region by enabling SYS_HAS_ARMV8_SECURE_BASE. Enable it for the LS1043A SoC, where it was possible to relocate the PSCI code before as well as on the LS1028A SoC where there will be PSCI support soon. Additionally, make ARMV8_PSCI and SEC_FIRMWARE_ARMV8_PSCI exclusive. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-28 12:48:40 +00:00
config SYS_HAS_ARMV8_SECURE_BASE
bool
ARMv8: Add secure sections for PSCI text and data This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to hold PSCI text and data, and it is based on the legacy implementation of ARMv7. ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here in Kconfig too. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-08 03:58:22 +00:00
config ARMV8_PSCI
bool "Enable PSCI support" if EXPERT
help
PSCI is Power State Coordination Interface defined by ARM.
global: Use proper project name U-Boot Use proper project name in comments, Kconfig, readmes. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Qu Wenruo <wqu@suse.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com
2023-05-17 07:17:16 +00:00
The PSCI in U-Boot provides a general framework and each platform
ARMv8: Add secure sections for PSCI text and data This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to hold PSCI text and data, and it is based on the legacy implementation of ARMv7. ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here in Kconfig too. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-08 03:58:22 +00:00
can implement their own specific PSCI functions.
Say Y here to enable PSCI support on ARMv8 platform.
config ARMV8_PSCI_NR_CPUS
int "Maximum supported CPUs for PSCI"
depends on ARMV8_PSCI
default 4
help
The maximum number of CPUs supported in the PSCI firmware.
It is no problem to set a larger value than the number of CPUs in
the actual hardware implementation.
ARMv8: Add basic PSCI framework This patch introduces a generic ARMv8 PSCI framework, with all functions returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each platform to implement their own functions based on this framework. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-08 03:58:24 +00:00
config ARMV8_PSCI_CPUS_PER_CLUSTER
int "Number of CPUs per cluster"
depends on ARMV8_PSCI
default 0
help
The number of CPUs per cluster, suppose each cluster has same number
of CPU cores, platforms with asymmetric clusters don't apply here.
A value 0 or no definition of it works for single cluster system.
System with multi-cluster should difine their own exact value.
armv8: psci: add ARMV8_PSCI_RELOCATE Kconfig option There is an user-selectable SYS_HAS_ARMV8_SECURE_BASE, which has the same meaning but is just for the ls1043ardb board. As no in-tree config uses this, drop it and replace it with something more sophiticated: ARMV8_PSCI_RELOCATE. This option will then enable the ARMV8_SECURE_BASE option which is used as the base to relocate the PSCI code (or any code in the secure region, but that is only PSCI). A SoC (or board) can now opt-in into having such a secure region by enabling SYS_HAS_ARMV8_SECURE_BASE. Enable it for the LS1043A SoC, where it was possible to relocate the PSCI code before as well as on the LS1028A SoC where there will be PSCI support soon. Additionally, make ARMV8_PSCI and SEC_FIRMWARE_ARMV8_PSCI exclusive. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-28 12:48:40 +00:00
config ARMV8_PSCI_RELOCATE
bool "Relocate PSCI code"
depends on ARMV8_PSCI
depends on SYS_HAS_ARMV8_SECURE_BASE
ARMv8: Add EL3 exception handling for ARMv8's Kconfig Kconfig option to allow all External Abort and SError exception taken to EL3. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-08-20 17:57:35 +00:00
help
armv8: psci: add ARMV8_PSCI_RELOCATE Kconfig option There is an user-selectable SYS_HAS_ARMV8_SECURE_BASE, which has the same meaning but is just for the ls1043ardb board. As no in-tree config uses this, drop it and replace it with something more sophiticated: ARMV8_PSCI_RELOCATE. This option will then enable the ARMV8_SECURE_BASE option which is used as the base to relocate the PSCI code (or any code in the secure region, but that is only PSCI). A SoC (or board) can now opt-in into having such a secure region by enabling SYS_HAS_ARMV8_SECURE_BASE. Enable it for the LS1043A SoC, where it was possible to relocate the PSCI code before as well as on the LS1028A SoC where there will be PSCI support soon. Additionally, make ARMV8_PSCI and SEC_FIRMWARE_ARMV8_PSCI exclusive. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-28 12:48:40 +00:00
Relocate PSCI code, for example to a secure memory on the SoC. If not
set, the PSCI sections are placed together with the u-boot and the
regions will be marked as reserved before linux is started.
ARMv8: Add secure sections for PSCI text and data This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to hold PSCI text and data, and it is based on the legacy implementation of ARMv7. ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here in Kconfig too. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-08 03:58:22 +00:00
config ARMV8_SECURE_BASE
hex "Secure address for PSCI image"
armv8: psci: add ARMV8_PSCI_RELOCATE Kconfig option There is an user-selectable SYS_HAS_ARMV8_SECURE_BASE, which has the same meaning but is just for the ls1043ardb board. As no in-tree config uses this, drop it and replace it with something more sophiticated: ARMV8_PSCI_RELOCATE. This option will then enable the ARMV8_SECURE_BASE option which is used as the base to relocate the PSCI code (or any code in the secure region, but that is only PSCI). A SoC (or board) can now opt-in into having such a secure region by enabling SYS_HAS_ARMV8_SECURE_BASE. Enable it for the LS1043A SoC, where it was possible to relocate the PSCI code before as well as on the LS1028A SoC where there will be PSCI support soon. Additionally, make ARMV8_PSCI and SEC_FIRMWARE_ARMV8_PSCI exclusive. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-28 12:48:40 +00:00
depends on ARMV8_PSCI_RELOCATE
default 0x18000000 if ARCH_LS1028A
ARMv8: Add secure sections for PSCI text and data This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to hold PSCI text and data, and it is based on the legacy implementation of ARMv7. ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here in Kconfig too. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-08 03:58:22 +00:00
help
Address for placing the PSCI text, data and stack sections.
armv8: psci: add ARMV8_PSCI_RELOCATE Kconfig option There is an user-selectable SYS_HAS_ARMV8_SECURE_BASE, which has the same meaning but is just for the ls1043ardb board. As no in-tree config uses this, drop it and replace it with something more sophiticated: ARMV8_PSCI_RELOCATE. This option will then enable the ARMV8_SECURE_BASE option which is used as the base to relocate the PSCI code (or any code in the secure region, but that is only PSCI). A SoC (or board) can now opt-in into having such a secure region by enabling SYS_HAS_ARMV8_SECURE_BASE. Enable it for the LS1043A SoC, where it was possible to relocate the PSCI code before as well as on the LS1028A SoC where there will be PSCI support soon. Additionally, make ARMV8_PSCI and SEC_FIRMWARE_ARMV8_PSCI exclusive. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-28 12:48:40 +00:00
config ARMV8_EA_EL3_FIRST
bool "External aborts and SError interrupt exception are taken in EL3"
help
Exception handling at all exception levels for External Abort and
SError interrupt exception are taken in EL3.
ARMv8: Add secure sections for PSCI text and data This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to hold PSCI text and data, and it is based on the legacy implementation of ARMv7. ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here in Kconfig too. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-08 03:58:22 +00:00
armv8 SHA-1 using ARMv8 Crypto Extensions: This patch adds support for the SHA-1 Secure Hash Algorithm for CPUs that have support for the SHA-1 part of the ARM v8 Crypto Extensions. It greatly improves sha-1 based operations, about 10x faster on iMX8M evk board. ~12ms vs ~165ms for a 20MiB kernel sha-1 verification. asm implementation is a simplified version of the Linux version (from Ard Biesheuvel). Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-01 18:26:29 +00:00
menuconfig ARMV8_CRYPTO
bool "ARM64 Accelerated Cryptographic Algorithms"
if ARMV8_CRYPTO
config ARMV8_CE_SHA1
bool "SHA-1 digest algorithm (ARMv8 Crypto Extensions)"
default y if SHA1
armv8 SHA-256 using ARMv8 Crypto Extensions This patch adds support for the SHA-256 Secure Hash Algorithm for CPUs that have support for the SHA-256 part of the ARM v8 Crypto Extensions. It greatly improves sha-256 based operations, about 17x faster on iMX8M evk board. ~12ms vs ~208ms for a 20MiB kernel sha-256 verification. asm implementation is a simplified version of the Linux version (from Ard Biesheuvel). Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-01 18:26:31 +00:00
config ARMV8_CE_SHA256
bool "SHA-256 digest algorithm (ARMv8 Crypto Extensions)"
default y if SHA256
armv8 SHA-1 using ARMv8 Crypto Extensions: This patch adds support for the SHA-1 Secure Hash Algorithm for CPUs that have support for the SHA-1 part of the ARM v8 Crypto Extensions. It greatly improves sha-1 based operations, about 10x faster on iMX8M evk board. ~12ms vs ~165ms for a 20MiB kernel sha-1 verification. asm implementation is a simplified version of the Linux version (from Ard Biesheuvel). Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2022-06-01 18:26:29 +00:00
endif
armv8/vexpress64: make multientry conditional While the Freescale ARMv8 board LS2085A will enter U-Boot both on a master and a secondary (slave) CPU, this is not the common behaviour on ARMv8 platforms. The norm is that U-Boot is entered from the master CPU only, while the other CPUs are kept in WFI (wait for interrupt) state. The code determining which CPU we are running on is using the MPIDR register, but the definition of that register varies with platform to some extent, and handling multi-cluster platforms (such as the Juno) will become cumbersome. It is better to only enable the multiple entry code on machines that actually need it and disable it by default. Make the single entry default and add a special ARMV8_MULTIENTRY KConfig option to be used by the platforms that need multientry and set it for the LS2085A. Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 boards as it is just totally unused and misleading, and make it conditional in the generic start.S code. This makes the Juno platform start U-Boot properly. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 09:53:21 +00:00
endif
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