u-boot/arch/arm/mach-bcm283x/include/mach/base.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * (C) Copyright 2019 Matthias Brugger
 */

#ifndef _BCM283x_BASE_H_
#define _BCM283x_BASE_H_

extern unsigned long rpi_bcm283x_base;

#ifdef CONFIG_ARMV7_LPAE
#ifdef CONFIG_TARGET_RPI_4_32B
#include <addr_map.h>
#define phys_to_virt addrmap_phys_to_virt
#define virt_to_phys addrmap_virt_to_phys
#endif
#endif

#endif
ARM: bcm283x: Move BCM283x_BASE to a global variable We move the per SOC define BCM283x_BASE to a global variable. This is a first step to provide a single binary for several bcm283x SoCs. Signed-off-by: Matthias Brugger <mbrugger@suse.com> 2019-11-19 15:01:03 +00:00			`/* SPDX-License-Identifier: GPL-2.0 */`
			`/*`
			`* (C) Copyright 2019 Matthias Brugger`
			`*/`

			`#ifndef _BCM283x_BASE_H_`
			`#define _BCM283x_BASE_H_`

			`extern unsigned long rpi_bcm283x_base;`

rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> 2020-06-03 12:43:44 +00:00			`#ifdef CONFIG_ARMV7_LPAE`
			`#ifdef CONFIG_TARGET_RPI_4_32B`
			`#include <addr_map.h>`
			`#define phys_to_virt addrmap_phys_to_virt`
			`#define virt_to_phys addrmap_virt_to_phys`
			`#endif`
			`#endif`

ARM: bcm283x: Move BCM283x_BASE to a global variable We move the per SOC define BCM283x_BASE to a global variable. This is a first step to provide a single binary for several bcm283x SoCs. Signed-off-by: Matthias Brugger <mbrugger@suse.com> 2019-11-19 15:01:03 +00:00			`#endif`