2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2014-01-26 17:06:40 +00:00
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/*
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* (C) Copyright 2014 Freescale Semiconductor, Inc.
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*/
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2015-08-13 02:55:30 +00:00
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#define MXC_CPU_MX23 0x23
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#define MXC_CPU_MX25 0x25
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#define MXC_CPU_MX27 0x27
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#define MXC_CPU_MX28 0x28
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#define MXC_CPU_MX31 0x31
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#define MXC_CPU_MX35 0x35
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2014-01-26 17:06:40 +00:00
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#define MXC_CPU_MX51 0x51
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#define MXC_CPU_MX53 0x53
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#define MXC_CPU_MX6SL 0x60
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#define MXC_CPU_MX6DL 0x61
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2014-06-24 20:40:58 +00:00
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#define MXC_CPU_MX6SX 0x62
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2014-01-26 17:06:40 +00:00
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#define MXC_CPU_MX6Q 0x63
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2015-07-20 11:28:21 +00:00
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#define MXC_CPU_MX6UL 0x64
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2016-08-11 06:02:38 +00:00
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#define MXC_CPU_MX6ULL 0x65
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#define MXC_CPU_MX6SOLO 0x66 /* dummy */
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2016-12-11 11:24:20 +00:00
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#define MXC_CPU_MX6SLL 0x67
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#define MXC_CPU_MX6D 0x6A
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2015-07-11 03:38:42 +00:00
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#define MXC_CPU_MX6DP 0x68
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#define MXC_CPU_MX6QP 0x69
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2016-02-28 15:33:17 +00:00
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#define MXC_CPU_MX7S 0x71 /* dummy ID */
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2015-09-02 18:54:19 +00:00
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#define MXC_CPU_MX7D 0x72
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2018-01-10 05:20:27 +00:00
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#define MXC_CPU_MX8MQ 0x82
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2018-10-18 12:28:24 +00:00
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#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
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2018-10-18 12:28:16 +00:00
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#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
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2018-01-10 05:20:27 +00:00
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#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
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2015-09-01 09:15:03 +00:00
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#define MXC_CPU_VF610 0xF6 /* dummy ID */
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2014-11-14 13:27:21 +00:00
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2015-09-02 18:54:12 +00:00
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#define MXC_SOC_MX6 0x60
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2015-09-02 18:54:19 +00:00
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#define MXC_SOC_MX7 0x70
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2018-01-10 05:20:27 +00:00
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#define MXC_SOC_MX8M 0x80
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2018-10-18 12:28:16 +00:00
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#define MXC_SOC_IMX8 0x90 /* dummy */
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2018-01-10 05:20:27 +00:00
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#define MXC_SOC_MX7ULP 0xE0 /* dummy */
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2015-09-02 18:54:12 +00:00
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2015-10-12 18:48:07 +00:00
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#define CHIP_REV_1_0 0x10
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#define CHIP_REV_1_1 0x11
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#define CHIP_REV_1_2 0x12
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#define CHIP_REV_1_5 0x15
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#define CHIP_REV_2_0 0x20
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#define CHIP_REV_2_5 0x25
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#define CHIP_REV_3_0 0x30
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2018-10-18 12:28:24 +00:00
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#define CHIP_REV_A 0x0
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#define CHIP_REV_B 0x1
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2018-10-18 12:28:16 +00:00
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2015-10-12 18:48:07 +00:00
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#define BOARD_REV_1_0 0x0
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#define BOARD_REV_2_0 0x1
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#define BOARD_VER_OFFSET 0x8
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2014-11-14 13:27:21 +00:00
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#define CS0_128 0
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#define CS0_64M_CS1_64M 1
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#define CS0_64M_CS1_32M_CS2_32M 2
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#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
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2015-02-15 21:37:21 +00:00
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u32 get_imx_reset_cause(void);
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2017-05-17 14:23:07 +00:00
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ulong get_systemPLLCLK(void);
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ulong get_FCLK(void);
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ulong get_HCLK(void);
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ulong get_BCLK(void);
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ulong get_PERCLK1(void);
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ulong get_PERCLK2(void);
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ulong get_PERCLK3(void);
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