2014-01-26 17:06:40 +00:00
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/*
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* (C) Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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2015-08-13 02:55:30 +00:00
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#define MXC_CPU_MX23 0x23
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#define MXC_CPU_MX25 0x25
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#define MXC_CPU_MX27 0x27
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#define MXC_CPU_MX28 0x28
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#define MXC_CPU_MX31 0x31
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#define MXC_CPU_MX35 0x35
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2014-01-26 17:06:40 +00:00
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#define MXC_CPU_MX51 0x51
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#define MXC_CPU_MX53 0x53
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#define MXC_CPU_MX6SL 0x60
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#define MXC_CPU_MX6DL 0x61
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2014-06-24 20:40:58 +00:00
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#define MXC_CPU_MX6SX 0x62
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2014-01-26 17:06:40 +00:00
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#define MXC_CPU_MX6Q 0x63
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2015-07-20 11:28:21 +00:00
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#define MXC_CPU_MX6UL 0x64
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2014-06-24 20:40:58 +00:00
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#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
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2015-07-20 11:28:21 +00:00
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#define MXC_CPU_MX6D 0x67
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2015-07-11 03:38:42 +00:00
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#define MXC_CPU_MX6DP 0x68
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#define MXC_CPU_MX6QP 0x69
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2014-11-14 13:27:21 +00:00
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#define CS0_128 0
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#define CS0_64M_CS1_64M 1
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#define CS0_64M_CS1_32M_CS2_32M 2
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#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
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2015-02-15 21:37:21 +00:00
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u32 get_imx_reset_cause(void);
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