u-boot/arch/microblaze/include/asm/cache.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (c) 2011 The Chromium OS Authors.
 */

#ifndef __MICROBLAZE_CACHE_H__
#define __MICROBLAZE_CACHE_H__

/*
 * The microblaze can have either a 4 or 16 byte cacheline depending on whether
 * you are using OPB(4) or CacheLink(16).  If the board config has not specified
 * a cacheline size we assume the larger value of 16 bytes for DMA buffer
 * alignment.
 */
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN	16
#endif

/**
 * flush_cache_all - flush the entire instruction/data caches
 */
void flush_cache_all(void);

#endif /* __MICROBLAZE_CACHE_H__ */
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-06 21:58:06 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Michal Simek <monstr@monstr.eu> 2011-10-17 23:46:10 +00:00			`/*`
			`* Copyright (c) 2011 The Chromium OS Authors.`
			`*/`

			`#ifndef __MICROBLAZE_CACHE_H__`
			`#define __MICROBLAZE_CACHE_H__`

			`/*`
			`* The microblaze can have either a 4 or 16 byte cacheline depending on whether`
			`* you are using OPB(4) or CacheLink(16). If the board config has not specified`
			`* a cacheline size we assume the larger value of 16 bytes for DMA buffer`
			`* alignment.`
			`*/`
			`#ifdef CONFIG_SYS_CACHELINE_SIZE`
			`#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE`
			`#else`
			`#define ARCH_DMA_MINALIGN 16`
			`#endif`

microblaze: cache: introduce flush_cache_all() All flush_cache() calls in microblaze code are supposed to flush the entire instruction and data caches, so introduce flush_cache_all() helper to handle this. Also, provide implementations for flush_dcache_all() and invalidate_icache_all() so that icache and dcache u-boot commands can work. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-9-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> 2022-05-31 18:14:30 +00:00			`/**`
			`* flush_cache_all - flush the entire instruction/data caches`
			`*/`
			`void flush_cache_all(void);`

microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Michal Simek <monstr@monstr.eu> 2011-10-17 23:46:10 +00:00			`#endif /* __MICROBLAZE_CACHE_H__ */`