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u-boot/drivers/clk/uniphier/clk-uniphier-sys.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
clk: uniphier: add System clock support Support system clocks for LD4, Pro4, sLD8, Pro5, PXs2/LD6b, LD11, LD20. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-28 16:06:15 +00:00
/*
* Copyright (C) 2016-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#include "clk-uniphier.h"
clk: uniphier: add NAND controller clock This allows the NAND driver to enable clock and get its clock rate. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 17:21:19 +00:00
#define UNIPHIER_LD4_SYS_CLK_NAND(_id) \
clk: uniphier: add NAND 200MHz clock The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-19 11:03:20 +00:00
UNIPHIER_CLK_RATE(128, 50000000), \
clk: uniphier: add NAND controller clock This allows the NAND driver to enable clock and get its clock rate. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 17:21:19 +00:00
UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2)
#define UNIPHIER_LD11_SYS_CLK_NAND(_id) \
clk: uniphier: add NAND 200MHz clock The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-19 11:03:20 +00:00
UNIPHIER_CLK_RATE(128, 50000000), \
clk: uniphier: add NAND controller clock This allows the NAND driver to enable clock and get its clock rate. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 17:21:19 +00:00
UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0)
clk: uniphier: rework for better clock tree structure U-Boot does not support fancy clock tree structures like the Linux common clock framework. Implement a simple clock tree model at the driver level. With this, the clock data will be simplified. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 10:21:59 +00:00
const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\
defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
clk: uniphier: add NAND controller clock This allows the NAND driver to enable clock and get its clock rate. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 17:21:19 +00:00
UNIPHIER_LD4_SYS_CLK_NAND(2),
clk: uniphier: add NAND 200MHz clock The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-19 11:03:20 +00:00
UNIPHIER_CLK_RATE(3, 200000000),
clk: uniphier: add ethernet clock control support Add clock control for ethernet controller on each SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-18 01:05:33 +00:00
UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */
UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
clk: uniphier: rework for better clock tree structure U-Boot does not support fancy clock tree structures like the Linux common clock framework. Implement a simple clock tree model at the driver level. With this, the clock data will be simplified. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 10:21:59 +00:00
UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */
clk: uniphier: add ethernet clock control support Add clock control for ethernet controller on each SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-18 01:05:33 +00:00
UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0), /* ether-phy (Pro4) */
clk: uniphier: rework for better clock tree structure U-Boot does not support fancy clock tree structures like the Linux common clock framework. Implement a simple clock tree model at the driver level. With this, the clock data will be simplified. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 10:21:59 +00:00
UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */
UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */
UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19), /* usb30-phy (PXs2) */
UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20), /* usb31-phy (PXs2) */
{ /* sentinel */ }
#endif
clk: uniphier: add System clock support Support system clocks for LD4, Pro4, sLD8, Pro5, PXs2/LD6b, LD11, LD20. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-28 16:06:15 +00:00
};
clk: uniphier: rework for better clock tree structure U-Boot does not support fancy clock tree structures like the Linux common clock framework. Implement a simple clock tree model at the driver level. With this, the clock data will be simplified. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 10:21:59 +00:00
const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
clk: uniphier: add NAND controller clock This allows the NAND driver to enable clock and get its clock rate. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 17:21:19 +00:00
UNIPHIER_LD11_SYS_CLK_NAND(2),
clk: uniphier: add NAND 200MHz clock The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-19 11:03:20 +00:00
UNIPHIER_CLK_RATE(3, 200000000),
clk: uniphier: add ethernet clock control support Add clock control for ethernet controller on each SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-18 01:05:33 +00:00
UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
clk: uniphier: rework for better clock tree structure U-Boot does not support fancy clock tree structures like the Linux common clock framework. Implement a simple clock tree model at the driver level. With this, the clock data will be simplified. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 10:21:59 +00:00
UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */
UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13), /* usb30-phy1 (LD20) */
{ /* sentinel */ }
#endif
clk: uniphier: add System clock support Support system clocks for LD4, Pro4, sLD8, Pro5, PXs2/LD6b, LD11, LD20. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-28 16:06:15 +00:00
};
clk: uniphier: add PXs3 clock data Add basic clock data for Socionext's new SoC PXs3. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 10:22:00 +00:00
const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
clk: uniphier: add NAND controller clock This allows the NAND driver to enable clock and get its clock rate. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 17:21:19 +00:00
UNIPHIER_LD11_SYS_CLK_NAND(2),
clk: uniphier: add NAND 200MHz clock The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-19 11:03:20 +00:00
UNIPHIER_CLK_RATE(3, 200000000),
clk: uniphier: add ethernet clock control support Add clock control for ethernet controller on each SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-18 01:05:33 +00:00
UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */
clk: uniphier: add PXs3 clock data Add basic clock data for Socionext's new SoC PXs3. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-13 10:22:00 +00:00
UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */
UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */
UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 16), /* usb30-phy0 */
UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 18), /* usb30-phy1 */
UNIPHIER_CLK_GATE_SIMPLE(18, 0x210c, 20), /* usb30-phy2 */
UNIPHIER_CLK_GATE_SIMPLE(20, 0x210c, 17), /* usb31-phy0 */
UNIPHIER_CLK_GATE_SIMPLE(21, 0x210c, 19), /* usb31-phy1 */
{ /* sentinel */ }
#endif
};
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