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The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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| .. | ||
| clk-uniphier-core.c | ||
| clk-uniphier-mio.c | ||
| clk-uniphier-sys.c | ||
| clk-uniphier.h | ||
| Kconfig | ||
| Makefile | ||