2019-02-18 23:37:20 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
|
|
|
|
2019-02-19 15:49:05 +00:00
|
|
|
#include <dt-bindings/memory/stm32-sdram.h>
|
2018-02-07 09:44:49 +00:00
|
|
|
/{
|
|
|
|
soc {
|
2019-02-18 23:37:20 +00:00
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
|
|
|
|
fmc: fmc@A0000000 {
|
|
|
|
compatible = "st,stm32-fmc";
|
2021-11-15 10:39:16 +00:00
|
|
|
reg = <0xa0000000 0x1000>;
|
2019-02-18 23:37:20 +00:00
|
|
|
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
|
|
|
|
pinctrl-0 = <&fmc_pins>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
status = "okay";
|
2018-02-07 09:44:49 +00:00
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
2019-02-18 23:37:20 +00:00
|
|
|
|
|
|
|
mac: ethernet@40028000 {
|
|
|
|
compatible = "st,stm32-dwmac";
|
|
|
|
reg = <0x40028000 0x8000>;
|
|
|
|
reg-names = "stmmaceth";
|
|
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
|
|
|
|
<&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
|
|
|
|
<&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
|
|
|
|
interrupts = <61>, <62>;
|
|
|
|
interrupt-names = "macirq", "eth_wake_irq";
|
|
|
|
snps,pbl = <8>;
|
|
|
|
snps,mixed-burst;
|
|
|
|
pinctrl-0 = <ðernet_mii>;
|
|
|
|
phy-mode = "rmii";
|
|
|
|
phy-handle = <&phy0>;
|
|
|
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
mdio0 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
compatible = "snps,dwmac-mdio";
|
|
|
|
phy0: ethernet-phy@0 {
|
|
|
|
reg = <0>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2020-11-06 07:11:58 +00:00
|
|
|
qspi: spi@A0001000 {
|
2019-06-28 13:02:58 +00:00
|
|
|
compatible = "st,stm32f469-qspi";
|
2019-02-18 23:37:20 +00:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2021-11-15 10:39:16 +00:00
|
|
|
reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
|
2019-02-18 23:37:20 +00:00
|
|
|
reg-names = "qspi", "qspi_mm";
|
|
|
|
interrupts = <92>;
|
|
|
|
spi-max-frequency = <108000000>;
|
|
|
|
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
|
|
|
|
resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
|
|
|
|
pinctrl-0 = <&qspi_pins>;
|
|
|
|
|
|
|
|
status = "okay";
|
|
|
|
};
|
2018-02-07 09:44:49 +00:00
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2019-02-18 23:37:20 +00:00
|
|
|
&clk_hse {
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
|
|
|
|
&gpioa {
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
|
|
|
|
&gpiob {
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
|
|
|
|
&gpioc {
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
|
|
|
|
&gpiod {
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
|
|
|
|
&gpioe {
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
|
|
|
|
&gpiof {
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
|
|
|
|
&gpiog {
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
|
|
|
|
&gpioh {
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
|
|
|
|
&gpioi {
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
|
2017-04-12 21:16:36 +00:00
|
|
|
&pinctrl {
|
2019-02-18 23:37:20 +00:00
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
|
|
|
|
fmc_pins: fmc@0 {
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
pins
|
|
|
|
{
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
};
|
2017-04-12 21:16:36 +00:00
|
|
|
};
|
|
|
|
|
2019-02-18 23:37:20 +00:00
|
|
|
&pwrcfg {
|
|
|
|
u-boot,dm-pre-reloc;
|
2017-04-12 21:16:36 +00:00
|
|
|
};
|
2017-11-15 12:14:43 +00:00
|
|
|
|
2019-02-18 23:37:20 +00:00
|
|
|
&rcc {
|
2017-11-15 12:14:43 +00:00
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
2018-01-18 12:39:29 +00:00
|
|
|
|
2019-02-18 23:37:20 +00:00
|
|
|
&timer5 {
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
|
|
|
|
&usart1 {
|
2018-01-18 12:39:29 +00:00
|
|
|
u-boot,dm-pre-reloc;
|
2019-02-18 22:19:45 +00:00
|
|
|
clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
|
2018-01-18 12:39:29 +00:00
|
|
|
};
|