2018-05-06 21:58:06 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2012-09-13 03:18:20 +00:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2012 Freescale Semiconductor, Inc.
|
|
|
|
*
|
|
|
|
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <asm/arch/clock.h>
|
|
|
|
#include <asm/arch/imx-regs.h>
|
|
|
|
#include <asm/arch/iomux.h>
|
2013-06-04 07:00:15 +00:00
|
|
|
#include <asm/arch/mx6-pins.h>
|
2017-09-27 16:12:38 +00:00
|
|
|
#include <asm/mach-imx/spi.h>
|
2019-08-01 15:46:51 +00:00
|
|
|
#include <env.h>
|
2016-09-21 02:28:55 +00:00
|
|
|
#include <linux/errno.h>
|
2012-09-13 03:18:20 +00:00
|
|
|
#include <asm/gpio.h>
|
2017-06-29 08:16:06 +00:00
|
|
|
#include <asm/mach-imx/mxc_i2c.h>
|
|
|
|
#include <asm/mach-imx/iomux-v3.h>
|
|
|
|
#include <asm/mach-imx/boot_mode.h>
|
|
|
|
#include <asm/mach-imx/video.h>
|
2012-09-13 03:18:20 +00:00
|
|
|
#include <mmc.h>
|
2019-06-21 03:42:28 +00:00
|
|
|
#include <fsl_esdhc_imx.h>
|
2012-09-13 03:18:20 +00:00
|
|
|
#include <miiphy.h>
|
|
|
|
#include <netdev.h>
|
2013-07-25 17:12:14 +00:00
|
|
|
#include <asm/arch/mxc_hdmi.h>
|
|
|
|
#include <asm/arch/crm_regs.h>
|
|
|
|
#include <asm/io.h>
|
|
|
|
#include <asm/arch/sys_proto.h>
|
2014-05-09 16:15:42 +00:00
|
|
|
#include <i2c.h>
|
2017-09-22 15:12:18 +00:00
|
|
|
#include <input.h>
|
2014-05-09 16:15:42 +00:00
|
|
|
#include <power/pmic.h>
|
|
|
|
#include <power/pfuze100_pmic.h>
|
2014-11-06 08:29:00 +00:00
|
|
|
#include "../common/pfuze.h"
|
2014-12-02 01:55:27 +00:00
|
|
|
#include <usb.h>
|
2017-09-27 16:12:40 +00:00
|
|
|
#include <usb/ehci-ci.h>
|
2014-11-12 22:27:45 +00:00
|
|
|
|
2012-09-13 03:18:20 +00:00
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
|
2013-04-26 01:34:47 +00:00
|
|
|
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
|
|
|
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
|
|
|
|
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
2012-09-13 03:18:20 +00:00
|
|
|
|
2013-04-26 01:34:47 +00:00
|
|
|
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
|
|
|
|
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
|
|
|
|
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
2012-09-13 03:18:20 +00:00
|
|
|
|
2013-04-26 01:34:47 +00:00
|
|
|
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
|
|
|
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
2012-09-13 03:18:20 +00:00
|
|
|
|
2013-11-08 18:20:54 +00:00
|
|
|
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
|
|
|
|
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
|
|
|
|
2014-05-09 16:15:42 +00:00
|
|
|
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
|
|
|
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
|
|
|
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
|
|
|
|
|
|
|
|
#define I2C_PMIC 1
|
|
|
|
|
|
|
|
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
|
|
|
|
|
2014-10-21 23:14:53 +00:00
|
|
|
#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
|
|
|
|
|
2016-10-11 14:09:27 +00:00
|
|
|
#define KEY_VOL_UP IMX_GPIO_NR(1, 4)
|
|
|
|
|
2012-09-13 03:18:20 +00:00
|
|
|
int dram_init(void)
|
|
|
|
{
|
2014-11-12 22:27:45 +00:00
|
|
|
gd->ram_size = imx_ddr_size();
|
2012-09-13 03:18:20 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-11-06 14:24:25 +00:00
|
|
|
static iomux_v3_cfg_t const uart1_pads[] = {
|
2017-05-12 15:45:23 +00:00
|
|
|
IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
2012-09-13 03:18:20 +00:00
|
|
|
};
|
|
|
|
|
2014-11-06 14:24:25 +00:00
|
|
|
static iomux_v3_cfg_t const enet_pads[] = {
|
2017-05-12 15:45:23 +00:00
|
|
|
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
2012-09-18 17:24:23 +00:00
|
|
|
/* AR8031 PHY Reset */
|
2017-05-12 15:45:23 +00:00
|
|
|
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
2012-09-18 17:24:23 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static void setup_iomux_enet(void)
|
|
|
|
{
|
2017-05-12 15:45:23 +00:00
|
|
|
SETUP_IOMUX_PADS(enet_pads);
|
2012-09-18 17:24:23 +00:00
|
|
|
}
|
|
|
|
|
2014-11-06 14:24:25 +00:00
|
|
|
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
2017-05-12 15:45:23 +00:00
|
|
|
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
|
2012-12-30 14:14:59 +00:00
|
|
|
};
|
|
|
|
|
2014-11-06 14:24:25 +00:00
|
|
|
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
2017-05-12 15:45:23 +00:00
|
|
|
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
|
2012-09-13 03:18:20 +00:00
|
|
|
};
|
|
|
|
|
2014-11-06 14:24:25 +00:00
|
|
|
static iomux_v3_cfg_t const usdhc4_pads[] = {
|
2017-05-12 15:45:23 +00:00
|
|
|
IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
2012-12-30 14:14:59 +00:00
|
|
|
};
|
|
|
|
|
2014-11-06 14:24:25 +00:00
|
|
|
static iomux_v3_cfg_t const ecspi1_pads[] = {
|
2017-05-12 15:45:23 +00:00
|
|
|
IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
2013-11-08 18:20:54 +00:00
|
|
|
};
|
|
|
|
|
2014-10-21 23:14:53 +00:00
|
|
|
static iomux_v3_cfg_t const rgb_pads[] = {
|
2017-05-12 15:45:23 +00:00
|
|
|
IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
|
|
IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
2016-06-08 18:05:31 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static iomux_v3_cfg_t const bl_pads[] = {
|
2017-05-12 15:45:23 +00:00
|
|
|
IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
2014-10-21 23:14:53 +00:00
|
|
|
};
|
|
|
|
|
2016-06-08 18:05:31 +00:00
|
|
|
static void enable_backlight(void)
|
|
|
|
{
|
2017-05-12 15:45:23 +00:00
|
|
|
SETUP_IOMUX_PADS(bl_pads);
|
2019-02-01 16:40:19 +00:00
|
|
|
gpio_request(DISP0_PWR_EN, "Display Power Enable");
|
2016-06-08 18:05:31 +00:00
|
|
|
gpio_direction_output(DISP0_PWR_EN, 1);
|
|
|
|
}
|
|
|
|
|
2014-10-21 23:14:53 +00:00
|
|
|
static void enable_rgb(struct display_info_t const *dev)
|
|
|
|
{
|
2017-05-12 15:45:23 +00:00
|
|
|
SETUP_IOMUX_PADS(rgb_pads);
|
2016-06-08 18:05:31 +00:00
|
|
|
enable_backlight();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void enable_lvds(struct display_info_t const *dev)
|
|
|
|
{
|
|
|
|
enable_backlight();
|
2014-10-21 23:14:53 +00:00
|
|
|
}
|
|
|
|
|
2017-05-12 15:45:23 +00:00
|
|
|
static struct i2c_pads_info mx6q_i2c_pad_info1 = {
|
2014-05-09 16:15:42 +00:00
|
|
|
.scl = {
|
2017-05-12 15:45:23 +00:00
|
|
|
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
|
|
|
|
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
|
2014-05-09 16:15:42 +00:00
|
|
|
.gp = IMX_GPIO_NR(4, 12)
|
|
|
|
},
|
|
|
|
.sda = {
|
2017-05-12 15:45:23 +00:00
|
|
|
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
|
|
|
|
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
|
|
|
|
.gp = IMX_GPIO_NR(4, 13)
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
|
|
|
|
.scl = {
|
|
|
|
.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
|
|
|
|
.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
|
|
|
|
.gp = IMX_GPIO_NR(4, 12)
|
|
|
|
},
|
|
|
|
.sda = {
|
|
|
|
.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
|
|
|
|
.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
|
2014-05-09 16:15:42 +00:00
|
|
|
.gp = IMX_GPIO_NR(4, 13)
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2013-11-08 18:20:54 +00:00
|
|
|
static void setup_spi(void)
|
|
|
|
{
|
2017-05-12 15:45:23 +00:00
|
|
|
SETUP_IOMUX_PADS(ecspi1_pads);
|
2013-11-08 18:20:54 +00:00
|
|
|
}
|
|
|
|
|
2014-03-23 21:45:41 +00:00
|
|
|
iomux_v3_cfg_t const pcie_pads[] = {
|
2017-05-12 15:45:23 +00:00
|
|
|
IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */
|
|
|
|
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */
|
2014-03-23 21:45:41 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static void setup_pcie(void)
|
|
|
|
{
|
2017-05-12 15:45:23 +00:00
|
|
|
SETUP_IOMUX_PADS(pcie_pads);
|
2014-03-23 21:45:41 +00:00
|
|
|
}
|
|
|
|
|
2013-12-04 03:08:16 +00:00
|
|
|
iomux_v3_cfg_t const di0_pads[] = {
|
2017-05-12 15:45:23 +00:00
|
|
|
IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */
|
|
|
|
IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */
|
|
|
|
IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */
|
2013-12-04 03:08:16 +00:00
|
|
|
};
|
|
|
|
|
2012-09-13 03:18:20 +00:00
|
|
|
static void setup_iomux_uart(void)
|
|
|
|
{
|
2017-05-12 15:45:23 +00:00
|
|
|
SETUP_IOMUX_PADS(uart1_pads);
|
2012-09-13 03:18:20 +00:00
|
|
|
}
|
|
|
|
|
2019-06-21 03:42:28 +00:00
|
|
|
#ifdef CONFIG_FSL_ESDHC_IMX
|
2012-12-30 14:14:59 +00:00
|
|
|
struct fsl_esdhc_cfg usdhc_cfg[3] = {
|
|
|
|
{USDHC2_BASE_ADDR},
|
2012-09-13 03:18:20 +00:00
|
|
|
{USDHC3_BASE_ADDR},
|
2012-12-30 14:14:59 +00:00
|
|
|
{USDHC4_BASE_ADDR},
|
2012-09-13 03:18:20 +00:00
|
|
|
};
|
|
|
|
|
2012-12-30 14:14:59 +00:00
|
|
|
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
|
|
|
|
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
|
|
|
|
|
2016-01-28 08:51:27 +00:00
|
|
|
int board_mmc_get_env_dev(int devno)
|
|
|
|
{
|
|
|
|
return devno - 1;
|
|
|
|
}
|
|
|
|
|
2012-09-13 03:18:20 +00:00
|
|
|
int board_mmc_getcd(struct mmc *mmc)
|
|
|
|
{
|
2012-12-30 14:14:59 +00:00
|
|
|
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
2013-03-16 08:05:06 +00:00
|
|
|
int ret = 0;
|
2012-12-30 14:14:59 +00:00
|
|
|
|
|
|
|
switch (cfg->esdhc_base) {
|
|
|
|
case USDHC2_BASE_ADDR:
|
2013-03-16 08:05:06 +00:00
|
|
|
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
|
|
|
break;
|
2012-12-30 14:14:59 +00:00
|
|
|
case USDHC3_BASE_ADDR:
|
2013-03-16 08:05:06 +00:00
|
|
|
ret = !gpio_get_value(USDHC3_CD_GPIO);
|
|
|
|
break;
|
|
|
|
case USDHC4_BASE_ADDR:
|
|
|
|
ret = 1; /* eMMC/uSDHC4 is always present */
|
|
|
|
break;
|
2012-12-30 14:14:59 +00:00
|
|
|
}
|
2013-03-16 08:05:06 +00:00
|
|
|
|
|
|
|
return ret;
|
2012-09-13 03:18:20 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int board_mmc_init(bd_t *bis)
|
|
|
|
{
|
2014-11-18 13:26:06 +00:00
|
|
|
struct src *psrc = (struct src *)SRC_BASE_ADDR;
|
|
|
|
unsigned reg = readl(&psrc->sbmr1) >> 11;
|
2014-11-12 22:27:45 +00:00
|
|
|
/*
|
|
|
|
* Upon reading BOOT_CFG register the following map is done:
|
|
|
|
* Bit 11 and 12 of BOOT_CFG register can determine the current
|
|
|
|
* mmc port
|
|
|
|
* 0x1 SD1
|
|
|
|
* 0x2 SD2
|
|
|
|
* 0x3 SD4
|
|
|
|
*/
|
|
|
|
|
|
|
|
switch (reg & 0x3) {
|
|
|
|
case 0x1:
|
2017-05-12 15:45:23 +00:00
|
|
|
SETUP_IOMUX_PADS(usdhc2_pads);
|
2014-11-12 22:27:45 +00:00
|
|
|
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
|
|
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
|
|
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
|
|
|
|
break;
|
|
|
|
case 0x2:
|
2017-05-12 15:45:23 +00:00
|
|
|
SETUP_IOMUX_PADS(usdhc3_pads);
|
2014-11-12 22:27:45 +00:00
|
|
|
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
|
|
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
|
|
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
|
|
|
|
break;
|
|
|
|
case 0x3:
|
2017-05-12 15:45:23 +00:00
|
|
|
SETUP_IOMUX_PADS(usdhc4_pads);
|
2014-11-12 22:27:45 +00:00
|
|
|
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
|
|
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
|
|
|
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
2012-09-13 03:18:20 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-10-24 12:22:06 +00:00
|
|
|
static int ar8031_phy_fixup(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
unsigned short val;
|
|
|
|
|
|
|
|
/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
|
|
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
|
|
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
|
|
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
|
|
|
|
|
|
|
|
val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
|
|
|
|
val &= 0xffe3;
|
|
|
|
val |= 0x18;
|
|
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
|
|
|
|
|
|
|
|
/* introduce tx clock delay */
|
|
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
|
|
|
|
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
|
|
|
|
val |= 0x0100;
|
|
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int board_phy_config(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
ar8031_phy_fixup(phydev);
|
|
|
|
|
|
|
|
if (phydev->drv->config)
|
|
|
|
phydev->drv->config(phydev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-07-25 17:12:14 +00:00
|
|
|
#if defined(CONFIG_VIDEO_IPUV3)
|
2013-11-25 12:34:26 +00:00
|
|
|
static void disable_lvds(struct display_info_t const *dev)
|
|
|
|
{
|
|
|
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
|
|
|
|
|
|
int reg = readl(&iomux->gpr[2]);
|
|
|
|
|
|
|
|
reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
|
|
|
|
IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
|
|
|
|
|
|
|
|
writel(reg, &iomux->gpr[2]);
|
|
|
|
}
|
|
|
|
|
2013-09-04 18:12:38 +00:00
|
|
|
static void do_enable_hdmi(struct display_info_t const *dev)
|
|
|
|
{
|
2013-11-25 12:34:26 +00:00
|
|
|
disable_lvds(dev);
|
2013-09-04 18:12:38 +00:00
|
|
|
imx_enable_hdmi_phy();
|
|
|
|
}
|
2013-07-25 17:12:14 +00:00
|
|
|
|
2014-04-04 17:05:54 +00:00
|
|
|
struct display_info_t const displays[] = {{
|
2013-09-04 18:12:38 +00:00
|
|
|
.bus = -1,
|
|
|
|
.addr = 0,
|
2013-12-04 03:08:17 +00:00
|
|
|
.pixfmt = IPU_PIX_FMT_RGB666,
|
2013-11-25 12:34:26 +00:00
|
|
|
.detect = NULL,
|
2016-06-08 18:05:31 +00:00
|
|
|
.enable = enable_lvds,
|
2013-09-04 18:12:38 +00:00
|
|
|
.mode = {
|
2013-11-25 12:34:26 +00:00
|
|
|
.name = "Hannstar-XGA",
|
2013-09-04 18:12:38 +00:00
|
|
|
.refresh = 60,
|
|
|
|
.xres = 1024,
|
|
|
|
.yres = 768,
|
2016-03-16 15:55:03 +00:00
|
|
|
.pixclock = 15384,
|
|
|
|
.left_margin = 160,
|
|
|
|
.right_margin = 24,
|
|
|
|
.upper_margin = 29,
|
|
|
|
.lower_margin = 3,
|
|
|
|
.hsync_len = 136,
|
|
|
|
.vsync_len = 6,
|
2013-09-04 18:12:38 +00:00
|
|
|
.sync = FB_SYNC_EXT,
|
|
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
|
|
} }, {
|
|
|
|
.bus = -1,
|
|
|
|
.addr = 0,
|
2013-11-25 12:34:26 +00:00
|
|
|
.pixfmt = IPU_PIX_FMT_RGB24,
|
|
|
|
.detect = detect_hdmi,
|
|
|
|
.enable = do_enable_hdmi,
|
2013-09-04 18:12:38 +00:00
|
|
|
.mode = {
|
2013-11-25 12:34:26 +00:00
|
|
|
.name = "HDMI",
|
2013-09-04 18:12:38 +00:00
|
|
|
.refresh = 60,
|
|
|
|
.xres = 1024,
|
|
|
|
.yres = 768,
|
2016-03-16 15:55:03 +00:00
|
|
|
.pixclock = 15384,
|
|
|
|
.left_margin = 160,
|
|
|
|
.right_margin = 24,
|
|
|
|
.upper_margin = 29,
|
|
|
|
.lower_margin = 3,
|
|
|
|
.hsync_len = 136,
|
|
|
|
.vsync_len = 6,
|
2013-09-04 18:12:38 +00:00
|
|
|
.sync = FB_SYNC_EXT,
|
|
|
|
.vmode = FB_VMODE_NONINTERLACED
|
2014-10-21 23:14:53 +00:00
|
|
|
} }, {
|
|
|
|
.bus = 0,
|
|
|
|
.addr = 0,
|
|
|
|
.pixfmt = IPU_PIX_FMT_RGB24,
|
|
|
|
.detect = NULL,
|
|
|
|
.enable = enable_rgb,
|
|
|
|
.mode = {
|
|
|
|
.name = "SEIKO-WVGA",
|
|
|
|
.refresh = 60,
|
|
|
|
.xres = 800,
|
|
|
|
.yres = 480,
|
|
|
|
.pixclock = 29850,
|
|
|
|
.left_margin = 89,
|
|
|
|
.right_margin = 164,
|
|
|
|
.upper_margin = 23,
|
|
|
|
.lower_margin = 10,
|
|
|
|
.hsync_len = 10,
|
|
|
|
.vsync_len = 10,
|
|
|
|
.sync = 0,
|
|
|
|
.vmode = FB_VMODE_NONINTERLACED
|
2013-09-04 18:12:38 +00:00
|
|
|
} } };
|
2014-04-04 17:05:54 +00:00
|
|
|
size_t display_count = ARRAY_SIZE(displays);
|
2013-07-25 17:12:14 +00:00
|
|
|
|
|
|
|
static void setup_display(void)
|
|
|
|
{
|
|
|
|
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
2013-09-04 18:12:38 +00:00
|
|
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
2013-07-25 17:12:14 +00:00
|
|
|
int reg;
|
|
|
|
|
2013-12-04 03:08:16 +00:00
|
|
|
/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
|
2017-05-12 15:45:23 +00:00
|
|
|
SETUP_IOMUX_PADS(di0_pads);
|
2013-12-04 03:08:16 +00:00
|
|
|
|
2013-07-25 17:12:14 +00:00
|
|
|
enable_ipu_clock();
|
|
|
|
imx_setup_hdmi();
|
|
|
|
|
2013-09-04 18:12:38 +00:00
|
|
|
/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
|
2013-11-29 14:38:39 +00:00
|
|
|
reg = readl(&mxc_ccm->CCGR3);
|
2013-09-04 18:12:38 +00:00
|
|
|
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
|
|
|
|
writel(reg, &mxc_ccm->CCGR3);
|
|
|
|
|
|
|
|
/* set LDB0, LDB1 clk select to 011/011 */
|
|
|
|
reg = readl(&mxc_ccm->cs2cdr);
|
|
|
|
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|
|
|
|
| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
|
|
|
|
reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
|
|
|
|
| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
|
|
|
|
writel(reg, &mxc_ccm->cs2cdr);
|
|
|
|
|
|
|
|
reg = readl(&mxc_ccm->cscmr2);
|
|
|
|
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
|
|
|
|
writel(reg, &mxc_ccm->cscmr2);
|
|
|
|
|
2013-07-25 17:12:14 +00:00
|
|
|
reg = readl(&mxc_ccm->chsccdr);
|
|
|
|
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
|
|
|
|
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
|
2013-09-04 18:12:38 +00:00
|
|
|
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
|
|
|
|
<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
|
2013-07-25 17:12:14 +00:00
|
|
|
writel(reg, &mxc_ccm->chsccdr);
|
2013-09-04 18:12:38 +00:00
|
|
|
|
|
|
|
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
|
|
|
|
| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
|
|
|
|
| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
|
|
|
|
| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
|
|
|
|
| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
|
|
|
|
| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|
|
|
|
| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
|
|
|
|
| IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
|
|
|
|
| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
|
|
|
|
writel(reg, &iomux->gpr[2]);
|
|
|
|
|
|
|
|
reg = readl(&iomux->gpr[3]);
|
|
|
|
reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
|
|
|
|
| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
|
|
|
|
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
|
|
|
|
<< IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
|
|
|
|
writel(reg, &iomux->gpr[3]);
|
2013-07-25 17:12:14 +00:00
|
|
|
}
|
|
|
|
#endif /* CONFIG_VIDEO_IPUV3 */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Do not overwrite the console
|
|
|
|
* Use always serial for U-Boot console
|
|
|
|
*/
|
|
|
|
int overwrite_console(void)
|
|
|
|
{
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2012-09-18 17:24:23 +00:00
|
|
|
int board_eth_init(bd_t *bis)
|
|
|
|
{
|
|
|
|
setup_iomux_enet();
|
2014-03-23 21:45:41 +00:00
|
|
|
setup_pcie();
|
2012-09-18 17:24:23 +00:00
|
|
|
|
2014-01-04 19:36:32 +00:00
|
|
|
return cpu_eth_init(bis);
|
2012-09-18 17:24:23 +00:00
|
|
|
}
|
|
|
|
|
2014-12-02 01:55:27 +00:00
|
|
|
#ifdef CONFIG_USB_EHCI_MX6
|
|
|
|
static void setup_usb(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* set daisy chain for otg_pin_id on 6q.
|
|
|
|
* for 6dl, this bit is reserved
|
|
|
|
*/
|
|
|
|
imx_iomux_set_gpr_register(1, 13, 1, 0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-09-13 03:18:20 +00:00
|
|
|
int board_early_init_f(void)
|
|
|
|
{
|
|
|
|
setup_iomux_uart();
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int board_init(void)
|
|
|
|
{
|
|
|
|
/* address of boot parameters */
|
|
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
|
2013-11-08 18:20:54 +00:00
|
|
|
#ifdef CONFIG_MXC_SPI
|
|
|
|
setup_spi();
|
|
|
|
#endif
|
2017-05-12 15:45:23 +00:00
|
|
|
if (is_mx6dq() || is_mx6dqp())
|
|
|
|
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
|
|
|
|
else
|
|
|
|
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
|
2017-09-23 02:45:28 +00:00
|
|
|
#if defined(CONFIG_VIDEO_IPUV3)
|
|
|
|
setup_display();
|
|
|
|
#endif
|
2014-12-02 01:55:27 +00:00
|
|
|
#ifdef CONFIG_USB_EHCI_MX6
|
|
|
|
setup_usb();
|
|
|
|
#endif
|
|
|
|
|
2014-05-09 16:15:42 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-11-06 08:29:00 +00:00
|
|
|
int power_init_board(void)
|
2014-05-09 16:15:42 +00:00
|
|
|
{
|
|
|
|
struct pmic *p;
|
2015-07-21 23:02:49 +00:00
|
|
|
unsigned int reg;
|
|
|
|
int ret;
|
2014-05-09 16:15:42 +00:00
|
|
|
|
2014-11-06 08:29:00 +00:00
|
|
|
p = pfuze_common_init(I2C_PMIC);
|
|
|
|
if (!p)
|
|
|
|
return -ENODEV;
|
2014-05-09 16:15:42 +00:00
|
|
|
|
2015-01-27 02:14:04 +00:00
|
|
|
ret = pfuze_mode_init(p, APS_PFM);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2014-05-09 16:15:42 +00:00
|
|
|
/* Increase VGEN3 from 2.5 to 2.8V */
|
|
|
|
pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
|
2014-11-06 08:29:00 +00:00
|
|
|
reg &= ~LDO_VOL_MASK;
|
|
|
|
reg |= LDOB_2_80V;
|
2014-05-09 16:15:42 +00:00
|
|
|
pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
|
|
|
|
|
|
|
|
/* Increase VGEN5 from 2.8 to 3V */
|
|
|
|
pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
|
2014-11-06 08:29:00 +00:00
|
|
|
reg &= ~LDO_VOL_MASK;
|
|
|
|
reg |= LDOB_3_00V;
|
2014-05-09 16:15:42 +00:00
|
|
|
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
|
|
|
|
|
2012-09-13 03:18:20 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
spi: mxc: fix sf probe when using mxc_spi
MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:
cs = (cs | gpio << 8)
This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".
This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.
Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-20 12:08:50 +00:00
|
|
|
#ifdef CONFIG_MXC_SPI
|
|
|
|
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
|
|
|
{
|
|
|
|
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-03-16 08:05:07 +00:00
|
|
|
#ifdef CONFIG_CMD_BMODE
|
|
|
|
static const struct boot_mode board_boot_modes[] = {
|
|
|
|
/* 4 bit bus width */
|
|
|
|
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
|
|
|
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
|
|
|
/* 8 bit bus width */
|
2016-01-30 03:53:42 +00:00
|
|
|
{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
|
2013-03-16 08:05:07 +00:00
|
|
|
{NULL, 0},
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
int board_late_init(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_CMD_BMODE
|
|
|
|
add_board_boot_modes(board_boot_modes);
|
|
|
|
#endif
|
2015-07-11 03:38:46 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
2017-08-03 18:22:09 +00:00
|
|
|
env_set("board_name", "SABRESD");
|
2015-07-11 03:38:46 +00:00
|
|
|
|
2015-10-15 10:05:59 +00:00
|
|
|
if (is_mx6dqp())
|
2017-08-03 18:22:09 +00:00
|
|
|
env_set("board_rev", "MX6QP");
|
2016-05-23 10:36:06 +00:00
|
|
|
else if (is_mx6dq())
|
2017-08-03 18:22:09 +00:00
|
|
|
env_set("board_rev", "MX6Q");
|
2016-05-23 10:36:06 +00:00
|
|
|
else if (is_mx6sdl())
|
2017-08-03 18:22:09 +00:00
|
|
|
env_set("board_rev", "MX6DL");
|
2015-07-11 03:38:46 +00:00
|
|
|
#endif
|
|
|
|
|
2013-03-16 08:05:07 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-09-13 03:18:20 +00:00
|
|
|
int checkboard(void)
|
|
|
|
{
|
2013-06-04 07:00:15 +00:00
|
|
|
puts("Board: MX6-SabreSD\n");
|
2012-09-13 03:18:20 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2014-11-12 22:27:45 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
2017-05-12 15:45:23 +00:00
|
|
|
#include <asm/arch/mx6-ddr.h>
|
2014-11-12 22:27:45 +00:00
|
|
|
#include <spl.h>
|
2018-03-04 16:20:11 +00:00
|
|
|
#include <linux/libfdt.h>
|
2014-11-12 22:27:45 +00:00
|
|
|
|
2016-10-11 14:09:27 +00:00
|
|
|
#ifdef CONFIG_SPL_OS_BOOT
|
|
|
|
int spl_start_uboot(void)
|
|
|
|
{
|
2019-02-01 16:40:19 +00:00
|
|
|
gpio_request(KEY_VOL_UP, "KEY Volume UP");
|
2016-10-11 14:09:27 +00:00
|
|
|
gpio_direction_input(KEY_VOL_UP);
|
|
|
|
|
|
|
|
/* Only enter in Falcon mode if KEY_VOL_UP is pressed */
|
|
|
|
return gpio_get_value(KEY_VOL_UP);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-11-14 11:36:59 +00:00
|
|
|
static void ccgr_init(void)
|
|
|
|
{
|
|
|
|
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
|
|
|
|
writel(0x00C03F3F, &ccm->CCGR0);
|
|
|
|
writel(0x0030FC03, &ccm->CCGR1);
|
|
|
|
writel(0x0FFFC000, &ccm->CCGR2);
|
|
|
|
writel(0x3FF00000, &ccm->CCGR3);
|
|
|
|
writel(0x00FFF300, &ccm->CCGR4);
|
|
|
|
writel(0x0F0000C3, &ccm->CCGR5);
|
|
|
|
writel(0x000003FF, &ccm->CCGR6);
|
|
|
|
}
|
|
|
|
|
2016-09-26 12:14:25 +00:00
|
|
|
static int mx6q_dcd_table[] = {
|
|
|
|
0x020e0798, 0x000C0000,
|
|
|
|
0x020e0758, 0x00000000,
|
|
|
|
0x020e0588, 0x00000030,
|
|
|
|
0x020e0594, 0x00000030,
|
|
|
|
0x020e056c, 0x00000030,
|
|
|
|
0x020e0578, 0x00000030,
|
|
|
|
0x020e074c, 0x00000030,
|
|
|
|
0x020e057c, 0x00000030,
|
|
|
|
0x020e058c, 0x00000000,
|
|
|
|
0x020e059c, 0x00000030,
|
|
|
|
0x020e05a0, 0x00000030,
|
|
|
|
0x020e078c, 0x00000030,
|
|
|
|
0x020e0750, 0x00020000,
|
|
|
|
0x020e05a8, 0x00000030,
|
|
|
|
0x020e05b0, 0x00000030,
|
|
|
|
0x020e0524, 0x00000030,
|
|
|
|
0x020e051c, 0x00000030,
|
|
|
|
0x020e0518, 0x00000030,
|
|
|
|
0x020e050c, 0x00000030,
|
|
|
|
0x020e05b8, 0x00000030,
|
|
|
|
0x020e05c0, 0x00000030,
|
|
|
|
0x020e0774, 0x00020000,
|
|
|
|
0x020e0784, 0x00000030,
|
|
|
|
0x020e0788, 0x00000030,
|
|
|
|
0x020e0794, 0x00000030,
|
|
|
|
0x020e079c, 0x00000030,
|
|
|
|
0x020e07a0, 0x00000030,
|
|
|
|
0x020e07a4, 0x00000030,
|
|
|
|
0x020e07a8, 0x00000030,
|
|
|
|
0x020e0748, 0x00000030,
|
|
|
|
0x020e05ac, 0x00000030,
|
|
|
|
0x020e05b4, 0x00000030,
|
|
|
|
0x020e0528, 0x00000030,
|
|
|
|
0x020e0520, 0x00000030,
|
|
|
|
0x020e0514, 0x00000030,
|
|
|
|
0x020e0510, 0x00000030,
|
|
|
|
0x020e05bc, 0x00000030,
|
|
|
|
0x020e05c4, 0x00000030,
|
|
|
|
0x021b0800, 0xa1390003,
|
|
|
|
0x021b080c, 0x001F001F,
|
|
|
|
0x021b0810, 0x001F001F,
|
|
|
|
0x021b480c, 0x001F001F,
|
|
|
|
0x021b4810, 0x001F001F,
|
|
|
|
0x021b083c, 0x43270338,
|
|
|
|
0x021b0840, 0x03200314,
|
|
|
|
0x021b483c, 0x431A032F,
|
|
|
|
0x021b4840, 0x03200263,
|
|
|
|
0x021b0848, 0x4B434748,
|
|
|
|
0x021b4848, 0x4445404C,
|
|
|
|
0x021b0850, 0x38444542,
|
|
|
|
0x021b4850, 0x4935493A,
|
|
|
|
0x021b081c, 0x33333333,
|
|
|
|
0x021b0820, 0x33333333,
|
|
|
|
0x021b0824, 0x33333333,
|
|
|
|
0x021b0828, 0x33333333,
|
|
|
|
0x021b481c, 0x33333333,
|
|
|
|
0x021b4820, 0x33333333,
|
|
|
|
0x021b4824, 0x33333333,
|
|
|
|
0x021b4828, 0x33333333,
|
|
|
|
0x021b08b8, 0x00000800,
|
|
|
|
0x021b48b8, 0x00000800,
|
|
|
|
0x021b0004, 0x00020036,
|
|
|
|
0x021b0008, 0x09444040,
|
|
|
|
0x021b000c, 0x555A7975,
|
|
|
|
0x021b0010, 0xFF538F64,
|
|
|
|
0x021b0014, 0x01FF00DB,
|
|
|
|
0x021b0018, 0x00001740,
|
|
|
|
0x021b001c, 0x00008000,
|
|
|
|
0x021b002c, 0x000026d2,
|
|
|
|
0x021b0030, 0x005A1023,
|
|
|
|
0x021b0040, 0x00000027,
|
|
|
|
0x021b0000, 0x831A0000,
|
|
|
|
0x021b001c, 0x04088032,
|
|
|
|
0x021b001c, 0x00008033,
|
|
|
|
0x021b001c, 0x00048031,
|
|
|
|
0x021b001c, 0x09408030,
|
|
|
|
0x021b001c, 0x04008040,
|
|
|
|
0x021b0020, 0x00005800,
|
|
|
|
0x021b0818, 0x00011117,
|
|
|
|
0x021b4818, 0x00011117,
|
|
|
|
0x021b0004, 0x00025576,
|
|
|
|
0x021b0404, 0x00011006,
|
|
|
|
0x021b001c, 0x00000000,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int mx6qp_dcd_table[] = {
|
|
|
|
0x020e0798, 0x000c0000,
|
|
|
|
0x020e0758, 0x00000000,
|
|
|
|
0x020e0588, 0x00000030,
|
|
|
|
0x020e0594, 0x00000030,
|
|
|
|
0x020e056c, 0x00000030,
|
|
|
|
0x020e0578, 0x00000030,
|
|
|
|
0x020e074c, 0x00000030,
|
|
|
|
0x020e057c, 0x00000030,
|
|
|
|
0x020e058c, 0x00000000,
|
|
|
|
0x020e059c, 0x00000030,
|
|
|
|
0x020e05a0, 0x00000030,
|
|
|
|
0x020e078c, 0x00000030,
|
|
|
|
0x020e0750, 0x00020000,
|
|
|
|
0x020e05a8, 0x00000030,
|
|
|
|
0x020e05b0, 0x00000030,
|
|
|
|
0x020e0524, 0x00000030,
|
|
|
|
0x020e051c, 0x00000030,
|
|
|
|
0x020e0518, 0x00000030,
|
|
|
|
0x020e050c, 0x00000030,
|
|
|
|
0x020e05b8, 0x00000030,
|
|
|
|
0x020e05c0, 0x00000030,
|
|
|
|
0x020e0774, 0x00020000,
|
|
|
|
0x020e0784, 0x00000030,
|
|
|
|
0x020e0788, 0x00000030,
|
|
|
|
0x020e0794, 0x00000030,
|
|
|
|
0x020e079c, 0x00000030,
|
|
|
|
0x020e07a0, 0x00000030,
|
|
|
|
0x020e07a4, 0x00000030,
|
|
|
|
0x020e07a8, 0x00000030,
|
|
|
|
0x020e0748, 0x00000030,
|
|
|
|
0x020e05ac, 0x00000030,
|
|
|
|
0x020e05b4, 0x00000030,
|
|
|
|
0x020e0528, 0x00000030,
|
|
|
|
0x020e0520, 0x00000030,
|
|
|
|
0x020e0514, 0x00000030,
|
|
|
|
0x020e0510, 0x00000030,
|
|
|
|
0x020e05bc, 0x00000030,
|
|
|
|
0x020e05c4, 0x00000030,
|
|
|
|
0x021b0800, 0xa1390003,
|
|
|
|
0x021b080c, 0x001b001e,
|
|
|
|
0x021b0810, 0x002e0029,
|
|
|
|
0x021b480c, 0x001b002a,
|
|
|
|
0x021b4810, 0x0019002c,
|
|
|
|
0x021b083c, 0x43240334,
|
|
|
|
0x021b0840, 0x0324031a,
|
|
|
|
0x021b483c, 0x43340344,
|
|
|
|
0x021b4840, 0x03280276,
|
|
|
|
0x021b0848, 0x44383A3E,
|
|
|
|
0x021b4848, 0x3C3C3846,
|
|
|
|
0x021b0850, 0x2e303230,
|
|
|
|
0x021b4850, 0x38283E34,
|
|
|
|
0x021b081c, 0x33333333,
|
|
|
|
0x021b0820, 0x33333333,
|
|
|
|
0x021b0824, 0x33333333,
|
|
|
|
0x021b0828, 0x33333333,
|
|
|
|
0x021b481c, 0x33333333,
|
|
|
|
0x021b4820, 0x33333333,
|
|
|
|
0x021b4824, 0x33333333,
|
|
|
|
0x021b4828, 0x33333333,
|
|
|
|
0x021b08c0, 0x24912249,
|
|
|
|
0x021b48c0, 0x24914289,
|
|
|
|
0x021b08b8, 0x00000800,
|
|
|
|
0x021b48b8, 0x00000800,
|
|
|
|
0x021b0004, 0x00020036,
|
|
|
|
0x021b0008, 0x24444040,
|
|
|
|
0x021b000c, 0x555A7955,
|
|
|
|
0x021b0010, 0xFF320F64,
|
|
|
|
0x021b0014, 0x01ff00db,
|
|
|
|
0x021b0018, 0x00001740,
|
|
|
|
0x021b001c, 0x00008000,
|
|
|
|
0x021b002c, 0x000026d2,
|
|
|
|
0x021b0030, 0x005A1023,
|
|
|
|
0x021b0040, 0x00000027,
|
|
|
|
0x021b0400, 0x14420000,
|
|
|
|
0x021b0000, 0x831A0000,
|
|
|
|
0x021b0890, 0x00400C58,
|
|
|
|
0x00bb0008, 0x00000000,
|
|
|
|
0x00bb000c, 0x2891E41A,
|
|
|
|
0x00bb0038, 0x00000564,
|
|
|
|
0x00bb0014, 0x00000040,
|
|
|
|
0x00bb0028, 0x00000020,
|
|
|
|
0x00bb002c, 0x00000020,
|
|
|
|
0x021b001c, 0x04088032,
|
|
|
|
0x021b001c, 0x00008033,
|
|
|
|
0x021b001c, 0x00048031,
|
|
|
|
0x021b001c, 0x09408030,
|
|
|
|
0x021b001c, 0x04008040,
|
|
|
|
0x021b0020, 0x00005800,
|
|
|
|
0x021b0818, 0x00011117,
|
|
|
|
0x021b4818, 0x00011117,
|
|
|
|
0x021b0004, 0x00025576,
|
|
|
|
0x021b0404, 0x00011006,
|
|
|
|
0x021b001c, 0x00000000,
|
|
|
|
};
|
|
|
|
|
2017-05-12 15:45:24 +00:00
|
|
|
static int mx6dl_dcd_table[] = {
|
|
|
|
0x020e0774, 0x000C0000,
|
|
|
|
0x020e0754, 0x00000000,
|
|
|
|
0x020e04ac, 0x00000030,
|
|
|
|
0x020e04b0, 0x00000030,
|
|
|
|
0x020e0464, 0x00000030,
|
|
|
|
0x020e0490, 0x00000030,
|
|
|
|
0x020e074c, 0x00000030,
|
|
|
|
0x020e0494, 0x00000030,
|
|
|
|
0x020e04a0, 0x00000000,
|
|
|
|
0x020e04b4, 0x00000030,
|
|
|
|
0x020e04b8, 0x00000030,
|
|
|
|
0x020e076c, 0x00000030,
|
|
|
|
0x020e0750, 0x00020000,
|
|
|
|
0x020e04bc, 0x00000030,
|
|
|
|
0x020e04c0, 0x00000030,
|
|
|
|
0x020e04c4, 0x00000030,
|
|
|
|
0x020e04c8, 0x00000030,
|
|
|
|
0x020e04cc, 0x00000030,
|
|
|
|
0x020e04d0, 0x00000030,
|
|
|
|
0x020e04d4, 0x00000030,
|
|
|
|
0x020e04d8, 0x00000030,
|
|
|
|
0x020e0760, 0x00020000,
|
|
|
|
0x020e0764, 0x00000030,
|
|
|
|
0x020e0770, 0x00000030,
|
|
|
|
0x020e0778, 0x00000030,
|
|
|
|
0x020e077c, 0x00000030,
|
|
|
|
0x020e0780, 0x00000030,
|
|
|
|
0x020e0784, 0x00000030,
|
|
|
|
0x020e078c, 0x00000030,
|
|
|
|
0x020e0748, 0x00000030,
|
|
|
|
0x020e0470, 0x00000030,
|
|
|
|
0x020e0474, 0x00000030,
|
|
|
|
0x020e0478, 0x00000030,
|
|
|
|
0x020e047c, 0x00000030,
|
|
|
|
0x020e0480, 0x00000030,
|
|
|
|
0x020e0484, 0x00000030,
|
|
|
|
0x020e0488, 0x00000030,
|
|
|
|
0x020e048c, 0x00000030,
|
|
|
|
0x021b0800, 0xa1390003,
|
|
|
|
0x021b080c, 0x001F001F,
|
|
|
|
0x021b0810, 0x001F001F,
|
|
|
|
0x021b480c, 0x001F001F,
|
|
|
|
0x021b4810, 0x001F001F,
|
|
|
|
0x021b083c, 0x4220021F,
|
|
|
|
0x021b0840, 0x0207017E,
|
|
|
|
0x021b483c, 0x4201020C,
|
|
|
|
0x021b4840, 0x01660172,
|
|
|
|
0x021b0848, 0x4A4D4E4D,
|
|
|
|
0x021b4848, 0x4A4F5049,
|
|
|
|
0x021b0850, 0x3F3C3D31,
|
|
|
|
0x021b4850, 0x3238372B,
|
|
|
|
0x021b081c, 0x33333333,
|
|
|
|
0x021b0820, 0x33333333,
|
|
|
|
0x021b0824, 0x33333333,
|
|
|
|
0x021b0828, 0x33333333,
|
|
|
|
0x021b481c, 0x33333333,
|
|
|
|
0x021b4820, 0x33333333,
|
|
|
|
0x021b4824, 0x33333333,
|
|
|
|
0x021b4828, 0x33333333,
|
|
|
|
0x021b08b8, 0x00000800,
|
|
|
|
0x021b48b8, 0x00000800,
|
|
|
|
0x021b0004, 0x0002002D,
|
|
|
|
0x021b0008, 0x00333030,
|
|
|
|
0x021b000c, 0x3F435313,
|
|
|
|
0x021b0010, 0xB66E8B63,
|
|
|
|
0x021b0014, 0x01FF00DB,
|
|
|
|
0x021b0018, 0x00001740,
|
|
|
|
0x021b001c, 0x00008000,
|
|
|
|
0x021b002c, 0x000026d2,
|
|
|
|
0x021b0030, 0x00431023,
|
|
|
|
0x021b0040, 0x00000027,
|
|
|
|
0x021b0000, 0x831A0000,
|
|
|
|
0x021b001c, 0x04008032,
|
|
|
|
0x021b001c, 0x00008033,
|
|
|
|
0x021b001c, 0x00048031,
|
|
|
|
0x021b001c, 0x05208030,
|
|
|
|
0x021b001c, 0x04008040,
|
|
|
|
0x021b0020, 0x00005800,
|
|
|
|
0x021b0818, 0x00011117,
|
|
|
|
0x021b4818, 0x00011117,
|
|
|
|
0x021b0004, 0x0002556D,
|
|
|
|
0x021b0404, 0x00011006,
|
|
|
|
0x021b001c, 0x00000000,
|
|
|
|
};
|
|
|
|
|
2016-09-26 12:14:25 +00:00
|
|
|
static void ddr_init(int *table, int size)
|
2014-11-12 22:27:45 +00:00
|
|
|
{
|
2016-09-26 12:14:25 +00:00
|
|
|
int i;
|
2014-11-12 22:27:45 +00:00
|
|
|
|
2016-09-26 12:14:25 +00:00
|
|
|
for (i = 0; i < size / 2 ; i++)
|
|
|
|
writel(table[2 * i + 1], table[2 * i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void spl_dram_init(void)
|
|
|
|
{
|
|
|
|
if (is_mx6dq())
|
|
|
|
ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
|
|
|
|
else if (is_mx6dqp())
|
|
|
|
ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
|
2017-05-12 15:45:24 +00:00
|
|
|
else if (is_mx6sdl())
|
|
|
|
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
|
2014-11-12 22:27:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void board_init_f(ulong dummy)
|
|
|
|
{
|
2016-09-26 12:14:25 +00:00
|
|
|
/* DDR initialization */
|
|
|
|
spl_dram_init();
|
|
|
|
|
2014-11-12 22:27:45 +00:00
|
|
|
/* setup AIPS and disable watchdog */
|
|
|
|
arch_cpu_init();
|
|
|
|
|
2014-11-14 11:36:59 +00:00
|
|
|
ccgr_init();
|
|
|
|
gpr_init();
|
|
|
|
|
2014-11-12 22:27:45 +00:00
|
|
|
/* iomux and setup of i2c */
|
|
|
|
board_early_init_f();
|
|
|
|
|
|
|
|
/* setup GP timer */
|
|
|
|
timer_init();
|
|
|
|
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
|
|
preloader_console_init();
|
|
|
|
|
|
|
|
/* Clear the BSS. */
|
|
|
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
|
|
|
|
|
/* load/boot image from boot device */
|
|
|
|
board_init_r(NULL, 0);
|
|
|
|
}
|
|
|
|
#endif
|
2019-02-01 16:40:12 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_SPL_LOAD_FIT
|
|
|
|
int board_fit_config_name_match(const char *name)
|
|
|
|
{
|
|
|
|
if (is_mx6dq()) {
|
|
|
|
if (!strcmp(name, "imx6q-sabresd"))
|
|
|
|
return 0;
|
|
|
|
} else if (is_mx6dqp()) {
|
|
|
|
if (!strcmp(name, "imx6qp-sabresd"))
|
|
|
|
return 0;
|
|
|
|
} else if (is_mx6dl()) {
|
|
|
|
if (!strcmp(name, "imx6dl-sabresd"))
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
#endif
|