2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2003-08-29 22:00:43 +00:00
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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2009-05-13 08:54:10 +00:00
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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2003-08-29 22:00:43 +00:00
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*/
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/*
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* CPU specific code
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*/
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#include <common.h>
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#include <command.h>
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2019-11-14 19:57:37 +00:00
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#include <cpu_func.h>
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2019-11-14 19:57:42 +00:00
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#include <irq_func.h>
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2020-05-10 17:39:56 +00:00
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#include <asm/cache.h>
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2009-04-05 11:02:43 +00:00
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#include <asm/system.h>
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2003-08-29 22:00:43 +00:00
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2009-04-05 11:06:31 +00:00
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static void cache_flush(void);
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2003-08-29 22:00:43 +00:00
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2022-01-29 15:23:02 +00:00
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/************************************************************
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* sdelay() - simple spin loop. Will be constant time as
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* its generally used in bypass conditions only. This
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* is necessary until timers are accessible.
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*
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* not inline to increase chances its in cache when called
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*************************************************************/
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void sdelay(unsigned long loops)
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{
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__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0"(loops));
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}
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2003-08-29 22:00:43 +00:00
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int cleanup_before_linux (void)
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{
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/*
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* this function is called just before we call linux
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* it prepares the processor for linux
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*
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* we turn off caches etc ...
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*/
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2019-11-14 19:57:40 +00:00
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disable_interrupts();
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2003-08-29 22:00:43 +00:00
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2009-04-05 11:06:31 +00:00
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/* turn off I/D-cache */
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icache_disable();
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dcache_disable();
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2012-02-06 17:12:10 +00:00
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l2_cache_disable();
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2003-08-29 22:00:43 +00:00
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/* flush I/D-cache */
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2009-04-05 11:06:31 +00:00
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cache_flush();
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2005-09-24 23:48:28 +00:00
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2009-04-05 11:06:31 +00:00
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return 0;
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2003-08-29 22:00:43 +00:00
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}
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2009-04-05 11:06:31 +00:00
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/* flush I/D-cache */
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static void cache_flush (void)
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2008-07-10 14:46:33 +00:00
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{
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2019-05-03 13:41:00 +00:00
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#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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2009-04-05 11:06:31 +00:00
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unsigned long i = 0;
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2008-07-10 14:46:33 +00:00
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2009-04-05 11:06:31 +00:00
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asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
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arm, arm926ejs: make thumb mode compileable
in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c
when enabling CONFIG_SYS_THUMB_BUILD:
{standard input}: Assembler messages:
{standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0'
{standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0'
so, if caches are disabled, do not use this command on arm926ejs.
used on at91 in SPL, to reduce size of SPL.
Signed-off-by: Heiko Schocher <hs@denx.de>
2014-11-18 08:41:56 +00:00
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#endif
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2003-08-29 22:00:43 +00:00
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}
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