u-boot/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * NXP LS1028A-QDS device tree fragment for RCW 7777
 *
 * Copyright 2019-2021 NXP Semiconductors
 */

/*
 * This setup is using a SCH-30841 card with AQR412 10G quad PHY.
 *
 * Switch ports are mapped 1:1 to AQR412 card ports seated in slot 1.
 * Bottom port is port 0.
 * Note that this is only usable for:
 *  - QDS boards WITHOUT lane B rework,
 *  - AQR412 card WITHOUT lane A -> lane C rework
 *
 * The following DTS assumes DIP SW5[1-3] = 000b.
 */
&slot1 {
#include "fsl-sch-30841.dtsi"
};

&enetc2 {
	status = "okay";
};

&mscc_felix {
	status = "okay";
};

&mscc_felix_port0 {
	status = "okay";
	phy-mode = "sgmii-2500";
	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
};

&mscc_felix_port1 {
	status = "okay";
	phy-mode = "sgmii-2500";
	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
};

&mscc_felix_port2 {
	status = "okay";
	phy-mode = "sgmii-2500";
	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};

&mscc_felix_port3 {
	status = "okay";
	phy-mode = "sgmii-2500";
	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};

&mscc_felix_port4 {
	ethernet = <&enetc2>;
	status = "okay";
};