2011-11-08 23:18:08 +00:00
|
|
|
/*
|
2012-08-19 04:58:28 +00:00
|
|
|
* Freescale i.MX23/i.MX28 specific functions
|
2011-11-08 23:18:08 +00:00
|
|
|
*
|
|
|
|
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
|
|
|
* on behalf of DENX Software Engineering GmbH
|
|
|
|
*
|
2013-07-08 07:37:19 +00:00
|
|
|
* SPDX-License-Identifier: GPL-2.0+
|
2011-11-08 23:18:08 +00:00
|
|
|
*/
|
|
|
|
|
2012-08-13 09:53:12 +00:00
|
|
|
#ifndef __SYS_PROTO_H__
|
|
|
|
#define __SYS_PROTO_H__
|
2011-11-08 23:18:08 +00:00
|
|
|
|
2014-10-08 20:57:50 +00:00
|
|
|
#include <asm/imx-common/regs-common.h>
|
|
|
|
|
2012-08-13 09:53:12 +00:00
|
|
|
int mxs_reset_block(struct mxs_register_32 *reg);
|
|
|
|
int mxs_wait_mask_set(struct mxs_register_32 *reg,
|
2012-02-26 12:15:05 +00:00
|
|
|
uint32_t mask,
|
2012-08-22 10:10:11 +00:00
|
|
|
unsigned int timeout);
|
2012-08-13 09:53:12 +00:00
|
|
|
int mxs_wait_mask_clr(struct mxs_register_32 *reg,
|
2012-02-26 12:15:05 +00:00
|
|
|
uint32_t mask,
|
2012-08-22 10:10:11 +00:00
|
|
|
unsigned int timeout);
|
2011-11-08 23:18:08 +00:00
|
|
|
|
2013-01-22 15:01:03 +00:00
|
|
|
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
|
2011-11-08 23:18:09 +00:00
|
|
|
|
2011-12-02 03:47:40 +00:00
|
|
|
#ifdef CONFIG_SPL_BUILD
|
2013-01-11 03:19:05 +00:00
|
|
|
|
|
|
|
#if defined(CONFIG_MX23)
|
|
|
|
#include <asm/arch/iomux-mx23.h>
|
|
|
|
#elif defined(CONFIG_MX28)
|
2011-12-02 03:47:40 +00:00
|
|
|
#include <asm/arch/iomux-mx28.h>
|
2013-01-11 03:19:05 +00:00
|
|
|
#endif
|
|
|
|
|
2013-08-31 13:53:44 +00:00
|
|
|
void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
|
|
|
|
const iomux_cfg_t *iomux_setup,
|
|
|
|
const unsigned int iomux_size);
|
2011-12-02 03:47:40 +00:00
|
|
|
#endif
|
|
|
|
|
2012-08-13 09:53:12 +00:00
|
|
|
struct mxs_pair {
|
2012-05-01 11:09:45 +00:00
|
|
|
uint8_t boot_pads;
|
|
|
|
uint8_t boot_mask;
|
|
|
|
const char *mode;
|
|
|
|
};
|
|
|
|
|
2012-08-13 09:53:12 +00:00
|
|
|
static const struct mxs_pair mxs_boot_modes[] = {
|
2013-01-11 03:19:09 +00:00
|
|
|
#if defined(CONFIG_MX23)
|
|
|
|
{ 0x00, 0x0f, "USB" },
|
|
|
|
{ 0x01, 0x1f, "I2C, master" },
|
|
|
|
{ 0x02, 0x1f, "SSP SPI #1, master, NOR" },
|
|
|
|
{ 0x03, 0x1f, "SSP SPI #2, master, NOR" },
|
|
|
|
{ 0x04, 0x1f, "NAND" },
|
2013-09-19 23:36:44 +00:00
|
|
|
{ 0x06, 0x1f, "JTAG" },
|
2013-01-11 03:19:09 +00:00
|
|
|
{ 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
|
|
|
|
{ 0x09, 0x1f, "SSP SD/MMC #0" },
|
|
|
|
{ 0x0a, 0x1f, "SSP SD/MMC #1" },
|
|
|
|
{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
|
|
|
|
#elif defined(CONFIG_MX28)
|
2012-05-01 11:09:45 +00:00
|
|
|
{ 0x00, 0x0f, "USB #0" },
|
|
|
|
{ 0x01, 0x1f, "I2C #0, master, 3V3" },
|
|
|
|
{ 0x11, 0x1f, "I2C #0, master, 1V8" },
|
|
|
|
{ 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
|
|
|
|
{ 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
|
|
|
|
{ 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
|
|
|
|
{ 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
|
|
|
|
{ 0x04, 0x1f, "NAND, 3V3" },
|
|
|
|
{ 0x14, 0x1f, "NAND, 1V8" },
|
2013-09-19 23:36:44 +00:00
|
|
|
{ 0x06, 0x1f, "JTAG" },
|
2012-05-01 11:09:45 +00:00
|
|
|
{ 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
|
|
|
|
{ 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
|
|
|
|
{ 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
|
|
|
|
{ 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
|
|
|
|
{ 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
|
|
|
|
{ 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
|
|
|
|
{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
|
2013-01-11 03:19:09 +00:00
|
|
|
#endif
|
2012-05-01 11:09:45 +00:00
|
|
|
};
|
|
|
|
|
2015-01-25 01:07:53 +00:00
|
|
|
#define MXS_BM_USB 0x00
|
|
|
|
#define MXS_BM_I2C_MASTER_3V3 0x01
|
|
|
|
#define MXS_BM_I2C_MASTER_1V8 0x11
|
|
|
|
#define MXS_BM_SPI2_MASTER_3V3_NOR 0x02
|
|
|
|
#define MXS_BM_SPI2_MASTER_1V8_NOR 0x12
|
|
|
|
#define MXS_BM_SPI3_MASTER_3V3_NOR 0x03
|
|
|
|
#define MXS_BM_SPI3_MASTER_1V8_NOR 0x13
|
|
|
|
#define MXS_BM_NAND_3V3 0x04
|
|
|
|
#define MXS_BM_NAND_1V8 0x14
|
|
|
|
#define MXS_BM_JTAG 0x06
|
|
|
|
#define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08
|
|
|
|
#define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18
|
|
|
|
#define MXS_BM_SDMMC0_3V3 0x09
|
|
|
|
#define MXS_BM_SDMMC0_1V8 0x19
|
|
|
|
#define MXS_BM_SDMMC1_3V3 0x0a
|
|
|
|
#define MXS_BM_SDMMC1_1V8 0x1a
|
|
|
|
|
2012-08-05 09:05:32 +00:00
|
|
|
struct mxs_spl_data {
|
2012-05-01 11:09:45 +00:00
|
|
|
uint8_t boot_mode_idx;
|
2012-05-01 11:09:44 +00:00
|
|
|
uint32_t mem_dram_size;
|
|
|
|
};
|
|
|
|
|
2012-08-19 04:58:30 +00:00
|
|
|
int mxs_dram_init(void);
|
2011-12-20 05:46:33 +00:00
|
|
|
|
2012-08-13 09:53:12 +00:00
|
|
|
#endif /* __SYS_PROTO_H__ */
|