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u-boot/arch/x86/dts/galileo.dts

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x86: Add basic Intel Galileo board support New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-02 14:35:28 +00:00
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
x86: quark: Call MRC in dram_init() Now that we have added Quark MRC codes, call MRC in dram_init() so that DRAM can be initialized on a Quark based board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-05 15:42:28 +00:00
#include <dt-bindings/mrc/quark.h>
x86: quark: Implement PIRQ routing Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-05-25 14:35:06 +00:00
#include <dt-bindings/interrupt-router/intel-irq.h>
x86: quark: Call MRC in dram_init() Now that we have added Quark MRC codes, call MRC in dram_init() so that DRAM can be initialized on a Quark based board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-05 15:42:28 +00:00
x86: Add basic Intel Galileo board support New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-02 14:35:28 +00:00
/include/ "skeleton.dtsi"
x86: Enable DM RTC support for all x86 boards Add a RTC node in the device tree to enable DM RTC support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> (Squashed in 'x86: Fix RTC build error on ivybridge')
2015-07-15 08:23:39 +00:00
/include/ "rtc.dtsi"
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:22 +00:00
/include/ "tsc_timer.dtsi"
x86: Add basic Intel Galileo board support New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-02 14:35:28 +00:00
/ {
model = "Intel Galileo";
compatible = "intel,galileo", "intel,quark";
x86: Add alias for SPI node in the board dts Since Intel ICH SPI driver has been converted to driver model, we need add an alias for SPI node in the board dts files otherwise SPI flash won't be detected due to 'invalid bus' error. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-04-15 04:00:11 +00:00
aliases {
spi0 = "/spi";
};
x86: Add basic Intel Galileo board support New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-02 14:35:28 +00:00
config {
silent_console = <0>;
};
chosen {
stdout-path = &pciuart0;
};
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:22 +00:00
tsc-timer {
clock-frequency = <400000000>;
};
x86: quark: Call MRC in dram_init() Now that we have added Quark MRC codes, call MRC in dram_init() so that DRAM can be initialized on a Quark based board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-05 15:42:28 +00:00
mrc {
compatible = "intel,quark-mrc";
flags = <MRC_FLAG_SCRAMBLE_EN>;
dram-width = <DRAM_WIDTH_X8>;
dram-speed = <DRAM_FREQ_800>;
dram-type = <DRAM_TYPE_DDR3>;
rank-mask = <DRAM_RANK(0)>;
chan-mask = <DRAM_CHANNEL(0)>;
chan-width = <DRAM_CHANNEL_WIDTH_X16>;
addr-mode = <DRAM_ADDR_MODE0>;
refresh-rate = <DRAM_REFRESH_RATE_785US>;
sr-temp-range = <DRAM_SRT_RANGE_NORMAL>;
ron-value = <DRAM_RON_34OHM>;
rtt-nom-value = <DRAM_RTT_NOM_120OHM>;
rd-odt-value = <DRAM_RD_ODT_OFF>;
dram-density = <DRAM_DENSITY_1G>;
dram-cl = <6>;
dram-ras = <0x0000927c>;
dram-wtr = <0x00002710>;
dram-rrd = <0x00002710>;
dram-faw = <0x00009c40>;
};
x86: Add basic Intel Galileo board support New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-02 14:35:28 +00:00
pci {
#address-cells = <3>;
#size-cells = <2>;
x86: Convert to use driver model pci on quark/galileo Move to driver model pci for Intel quark/galileo. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-09-03 12:37:26 +00:00
compatible = "pci-x86";
u-boot,dm-pre-reloc;
ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000
0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
x86: Add basic Intel Galileo board support New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-02 14:35:28 +00:00
pciuart0: uart@14,5 {
compatible = "pci8086,0936.00",
"pci8086,0936",
"pciclass,070002",
"pciclass,0700",
x86: Fix PCI UART compatible string for crownbay and galileo With recent ns16550 driver changes, we only changed the legacy UART (at I/O port 0x3f8) compatible string, but forgot to change the PCI UART compatible string. Now fix it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-07 13:28:13 +00:00
"ns16550";
x86: Convert to use driver model pci on quark/galileo Move to driver model pci for Intel quark/galileo. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-09-03 12:37:26 +00:00
u-boot,dm-pre-reloc;
x86: Add basic Intel Galileo board support New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-02 14:35:28 +00:00
reg = <0x0000a500 0x0 0x0 0x0 0x0
0x0200a510 0x0 0x0 0x0 0x0>;
reg-shift = <2>;
clock-frequency = <44236800>;
current-speed = <115200>;
};
x86: quark: Implement PIRQ routing Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-05-25 14:35:06 +00:00
dm: x86: spi: Convert ICH SPI driver to driver model PCI API At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:21 +00:00
pch@1f,0 {
x86: quark: Implement PIRQ routing Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-05-25 14:35:06 +00:00
reg = <0x0000f800 0 0 0 0>;
dm: x86: spi: Convert ICH SPI driver to driver model PCI API At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:21 +00:00
compatible = "intel,pch7";
irq-router {
dm: x86: quark: Add an interrupt driver Add a driver for interrupts on quark and move the code currently in cpu_irq_init() into its probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-20 04:32:30 +00:00
compatible = "intel,quark-irq-router";
dm: x86: spi: Convert ICH SPI driver to driver model PCI API At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:21 +00:00
intel,pirq-config = "pci";
intel,pirq-link = <0x60 8>;
intel,pirq-mask = <0xdef8>;
intel,pirq-routing = <
PCI_BDF(0, 20, 0) INTA PIRQE
PCI_BDF(0, 20, 1) INTB PIRQF
PCI_BDF(0, 20, 2) INTC PIRQG
PCI_BDF(0, 20, 3) INTD PIRQH
PCI_BDF(0, 20, 4) INTA PIRQE
PCI_BDF(0, 20, 5) INTB PIRQF
PCI_BDF(0, 20, 6) INTC PIRQG
PCI_BDF(0, 20, 7) INTD PIRQH
PCI_BDF(0, 21, 0) INTA PIRQE
PCI_BDF(0, 21, 1) INTB PIRQF
PCI_BDF(0, 21, 2) INTC PIRQG
PCI_BDF(0, 23, 0) INTA PIRQA
PCI_BDF(0, 23, 1) INTB PIRQB
/* PCIe root ports downstream interrupts */
PCI_BDF(1, 0, 0) INTA PIRQA
PCI_BDF(1, 0, 0) INTB PIRQB
PCI_BDF(1, 0, 0) INTC PIRQC
PCI_BDF(1, 0, 0) INTD PIRQD
PCI_BDF(2, 0, 0) INTA PIRQB
PCI_BDF(2, 0, 0) INTB PIRQC
PCI_BDF(2, 0, 0) INTC PIRQD
PCI_BDF(2, 0, 0) INTD PIRQA
>;
};
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich-spi";
spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
reg = <0>;
compatible = "winbond,w25q64",
"spi-flash";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x00010000 0x00010000>;
};
};
};
x86: quark: Implement PIRQ routing Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-05-25 14:35:06 +00:00
};
x86: Add basic Intel Galileo board support New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-02 14:35:28 +00:00
};
x86: galileo: Add GPIO support Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31), which is just the same one found in other x86 chipset. Since we programmed the GPIO register block base address, we should be able to enable the GPIO support on Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-04 08:26:10 +00:00
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x20>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x20 0x20>;
bank-name = "B";
};
x86: Add basic Intel Galileo board support New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-02-02 14:35:28 +00:00
};
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