Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-07 21:54:45 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/arch/powerpc/cpu/mpc85xx/release.S

499 lines
12 KiB
ArmAsm
Raw Normal View History

SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-31 06:38:14 +00:00
/*
powerpc/mpc8xxx: fix core id for multicore booting For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:26 +00:00
* Copyright 2008-2012 Freescale Semiconductor, Inc.
8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-31 06:38:14 +00:00
* Kumar Gala <kumar.gala@freescale.com>
*/
Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-26 12:34:52 +00:00
#include <asm-offsets.h>
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
#include <config.h>
#include <mpc85xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
/* To boot secondary cpus, we need a place for them to start up.
* Normally, they start at 0xfffffffc, but that's usually the
* firmware, and we don't want to have to run the firmware again.
* Instead, the primary cpu will set the BPTR to point here to
* this page. We then set up the core, and head to
* start_secondary. Note that this means that the code below
* must never exceed 1023 instructions (the branch at the end
* would then be the 1024th).
*/
.globl __secondary_start_page
.align 12
__secondary_start_page:
powerpc: mpc85xx: Improve Work-around for Erratum A005125 Work-around for Erratum A005125 must be applied to all cores. Signed-off-by: Yoshihisa Morizumi <yoshi.morizumi@jp.fujitsu.com> Signed-off-by: Takuma Ueba <ueba.takuma@jp.fujitsu.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-04-23 04:27:33 +00:00
#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
msync
isync
mfspr r3, SPRN_HDBCR0
oris r3, r3, 0x0080
mtspr SPRN_HDBCR0, r3
#endif
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
/* First do some preliminary setup */
lis r3, HID0_EMCP@h /* enable machine check */
85xx: Add basic e500mc core support Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-23 06:47:38 +00:00
#ifndef CONFIG_E500MC
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
ori r3,r3,HID0_TBEN@l /* enable Timebase */
85xx: Add basic e500mc core support Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-23 06:47:38 +00:00
#endif
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
#ifdef CONFIG_PHYS_64BIT
ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
#endif
mtspr SPRN_HID0,r3
85xx: Add basic e500mc core support Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-23 06:47:38 +00:00
#ifndef CONFIG_E500MC
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
85xx: Set HID1[mbdd] on e500v2 rev5.0 or greater The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize the performance of mbar/eieio instructions. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
2010-03-12 05:15:02 +00:00
mfspr r0,PVR
andi. r0,r0,0xff
cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
blt 1f
/* Set MBDD bit also */
ori r3, r3, HID1_MBDD@l
1:
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
mtspr SPRN_HID1,r3
85xx: Add basic e500mc core support Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-23 06:47:38 +00:00
#endif
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
powerpc/85xx: Add workaround for erratum CPU-A003999 Erratum A-003999: Running Floating Point instructions requires special initialization. Impact: Floating point arithmetic operations may result in an incorrect value. Workaround: Perform a read modify write to set bit 7 to a 1 in SPR 977 before executing any floating point arithmetic operation. This bit can be set when setting MSR[FP], and can be cleared when clearing MSR[FP]. Alternatively, the bit can be set once at boot time, and never cleared. There will be no performance degradation due to setting this bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-22 12:51:15 +00:00
#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
powerpc/mpc85xx: Add definitions for HDBCR registers Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:33:10 +00:00
mfspr r3,SPRN_HDBCR1
powerpc/85xx: Add workaround for erratum CPU-A003999 Erratum A-003999: Running Floating Point instructions requires special initialization. Impact: Floating point arithmetic operations may result in an incorrect value. Workaround: Perform a read modify write to set bit 7 to a 1 in SPR 977 before executing any floating point arithmetic operation. This bit can be set when setting MSR[FP], and can be cleared when clearing MSR[FP]. Alternatively, the bit can be set once at boot time, and never cleared. There will be no performance degradation due to setting this bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-22 12:51:15 +00:00
oris r3,r3,0x0100
powerpc/mpc85xx: Add definitions for HDBCR registers Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:33:10 +00:00
mtspr SPRN_HDBCR1,r3
powerpc/85xx: Add workaround for erratum CPU-A003999 Erratum A-003999: Running Floating Point instructions requires special initialization. Impact: Floating point arithmetic operations may result in an incorrect value. Workaround: Perform a read modify write to set bit 7 to a 1 in SPR 977 before executing any floating point arithmetic operation. This bit can be set when setting MSR[FP], and can be cleared when clearing MSR[FP]. Alternatively, the bit can be set once at boot time, and never cleared. There will be no performance degradation due to setting this bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-22 12:51:15 +00:00
#endif
powerpc/fsl-corenet: work around erratum A004510 Erratum A004510 says that under certain load conditions, modified cache lines can be discarded, causing data corruption. To work around this, several CCSR and DCSR register updates need to be made in a careful manner, so that there is no other transaction in corenet when the update is made. The update is made from a locked cacheline, with a delay before to flush any previous activity, and a delay after to flush the CCSR/DCSR update. We can't use a readback because that would be another corenet transaction, which is not allowed. We lock the subsequent cacheline to prevent it from being fetched while we're executing the previous cacheline. It is filled with nops so that a branch doesn't cause us to fetch another cacheline. Ordinarily we are running in a cache-inhibited mapping at this point, so we temporarily change that. We make it guarded so that we should never see a speculative load, and we never do an explicit load. Thus, only the I-cache should ever fill from this mapping, and we flush/unlock it afterward. Thus we should avoid problems from any potential cache aliasing between inhibited and non-inhibited mappings. NOTE that if PAMU is used with this patch, it will need to use a dedicated LAW as described in the erratum. This is the responsibility of the OS that sets up PAMU. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-14 10:14:53 +00:00
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
mfspr r3,SPRN_SVR
rlwinm r3,r3,0,0xff
li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
cmpw r3,r4
beq 1f
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
cmpw r3,r4
beq 1f
#endif
/* Not a supported revision affected by erratum */
b 2f
1: /* Erratum says set bits 55:60 to 001001 */
msync
isync
powerpc/mpc85xx: Add definitions for HDBCR registers Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:33:10 +00:00
mfspr r3,SPRN_HDBCR0
powerpc/fsl-corenet: work around erratum A004510 Erratum A004510 says that under certain load conditions, modified cache lines can be discarded, causing data corruption. To work around this, several CCSR and DCSR register updates need to be made in a careful manner, so that there is no other transaction in corenet when the update is made. The update is made from a locked cacheline, with a delay before to flush any previous activity, and a delay after to flush the CCSR/DCSR update. We can't use a readback because that would be another corenet transaction, which is not allowed. We lock the subsequent cacheline to prevent it from being fetched while we're executing the previous cacheline. It is filled with nops so that a branch doesn't cause us to fetch another cacheline. Ordinarily we are running in a cache-inhibited mapping at this point, so we temporarily change that. We make it guarded so that we should never see a speculative load, and we never do an explicit load. Thus, only the I-cache should ever fill from this mapping, and we flush/unlock it afterward. Thus we should avoid problems from any potential cache aliasing between inhibited and non-inhibited mappings. NOTE that if PAMU is used with this patch, it will need to use a dedicated LAW as described in the erratum. This is the responsibility of the OS that sets up PAMU. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-14 10:14:53 +00:00
li r4,0x48
rlwimi r3,r4,0,0x1f8
powerpc/mpc85xx: Add definitions for HDBCR registers Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:33:10 +00:00
mtspr SPRN_HDBCR0,r3
powerpc/fsl-corenet: work around erratum A004510 Erratum A004510 says that under certain load conditions, modified cache lines can be discarded, causing data corruption. To work around this, several CCSR and DCSR register updates need to be made in a careful manner, so that there is no other transaction in corenet when the update is made. The update is made from a locked cacheline, with a delay before to flush any previous activity, and a delay after to flush the CCSR/DCSR update. We can't use a readback because that would be another corenet transaction, which is not allowed. We lock the subsequent cacheline to prevent it from being fetched while we're executing the previous cacheline. It is filled with nops so that a branch doesn't cause us to fetch another cacheline. Ordinarily we are running in a cache-inhibited mapping at this point, so we temporarily change that. We make it guarded so that we should never see a speculative load, and we never do an explicit load. Thus, only the I-cache should ever fill from this mapping, and we flush/unlock it afterward. Thus we should avoid problems from any potential cache aliasing between inhibited and non-inhibited mappings. NOTE that if PAMU is used with this patch, it will need to use a dedicated LAW as described in the erratum. This is the responsibility of the OS that sets up PAMU. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-14 10:14:53 +00:00
isync
2:
#endif
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
/* Enable branch prediction */
85xx: Add defines for BUCSR bits to make code more readable Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-29 18:50:31 +00:00
lis r3,BUCSR_ENABLE@h
ori r3,r3,BUCSR_ENABLE@l
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
mtspr SPRN_BUCSR,r3
85xx: Ensure timebase is zero on secondary cores The e500um says the timebase is volatile out of reset. To ensure TB sync works we need to make sure its zero. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-09-08 13:51:29 +00:00
/* Ensure TB is 0 */
li r3,0
mttbl r3
mttbu r3
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
/* Enable/invalidate the I-Cache */
85xx: Fix enabling of L1 cache parity on secondary cores Use the same code between primary and secondary cores to init the L1 cache. We were not enabling cache parity on the secondary cores. Also, reworked the L1 cache init code to match the e500mc L2 init code that first invalidates the cache and locks. Than enables the cache and makes sure its enabled before continuing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-26 20:14:43 +00:00
lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
mtspr SPRN_L1CSR1,r2
1:
mfspr r3,SPRN_L1CSR1
and. r1,r3,r2
bne 1b
lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
mtspr SPRN_L1CSR1,r3
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
isync
85xx: Fix enabling of L1 cache parity on secondary cores Use the same code between primary and secondary cores to init the L1 cache. We were not enabling cache parity on the secondary cores. Also, reworked the L1 cache init code to match the e500mc L2 init code that first invalidates the cache and locks. Than enables the cache and makes sure its enabled before continuing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-26 20:14:43 +00:00
2:
mfspr r3,SPRN_L1CSR1
andi. r1,r3,L1CSR1_ICE@l
beq 2b
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
/* Enable/invalidate the D-Cache */
85xx: Fix enabling of L1 cache parity on secondary cores Use the same code between primary and secondary cores to init the L1 cache. We were not enabling cache parity on the secondary cores. Also, reworked the L1 cache init code to match the e500mc L2 init code that first invalidates the cache and locks. Than enables the cache and makes sure its enabled before continuing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-26 20:14:43 +00:00
lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
mtspr SPRN_L1CSR0,r2
1:
mfspr r3,SPRN_L1CSR0
and. r1,r3,r2
bne 1b
lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
mtspr SPRN_L1CSR0,r3
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
isync
85xx: Fix enabling of L1 cache parity on secondary cores Use the same code between primary and secondary cores to init the L1 cache. We were not enabling cache parity on the secondary cores. Also, reworked the L1 cache init code to match the e500mc L2 init code that first invalidates the cache and locks. Than enables the cache and makes sure its enabled before continuing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-26 20:14:43 +00:00
2:
mfspr r3,SPRN_L1CSR0
andi. r1,r3,L1CSR0_DCE@l
beq 2b
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
#define toreset(x) (x - __secondary_start_page + 0xfffff000)
/* get our PIR to figure out our table entry */
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
lis r3,toreset(__spin_table_addr)@h
ori r3,r3,toreset(__spin_table_addr)@l
lwz r3,0(r3)
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
mfspr r0,SPRN_PIR
powerpc/mpc85xx: Fix PIR parsing for chassis2 The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:33:27 +00:00
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
powerpc/mpc8xxx: fix core id for multicore booting For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:26 +00:00
/*
powerpc/mpc85xx: Fix PIR parsing for chassis2 The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:33:27 +00:00
* PIR definition for Chassis 2
powerpc/mpc8xxx: fix core id for multicore booting For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:26 +00:00
* 0-17 Reserved (logic 0s)
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:40:07 +00:00
* 18-19 CHIP_ID, 2'b00 - SoC 1
powerpc/mpc8xxx: fix core id for multicore booting For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:26 +00:00
* all others - reserved
powerpc/mpc85xx: fix Unicode characters in release.S Commit 709389b6 unintentionally used the Unicode version of the apostrophy. Replace it with the normal ASCII version. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 09:48:50 +00:00
* 20-24 CLUSTER_ID 5'b00000 - CCM 1
powerpc/mpc8xxx: fix core id for multicore booting For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:26 +00:00
* all others - reserved
powerpc/mpc85xx: fix Unicode characters in release.S Commit 709389b6 unintentionally used the Unicode version of the apostrophy. Replace it with the normal ASCII version. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 09:48:50 +00:00
* 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
* 2'b01 - cluster 2
* 2'b10 - cluster 3
* 2'b11 - cluster 4
* 27-28 CORE_ID 2'b00 - core 0
* 2'b01 - core 1
* 2'b10 - core 2
* 2'b11 - core 3
* 29-31 THREAD_ID 3'b000 - thread 0
* 3'b001 - thread 1
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:40:07 +00:00
*
* Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
* and clusters by 0x20.
*
* We renumber PIR so that all threads in the system are consecutive.
powerpc/mpc8xxx: fix core id for multicore booting For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:26 +00:00
*/
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:40:07 +00:00
rlwinm r8,r0,29,0x03 /* r8 = core within cluster */
srwi r10,r0,5 /* r10 = cluster */
mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
add r5,r5,r8 /* for spin table index */
mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */
powerpc/mpc8xxx: fix core id for multicore booting For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:26 +00:00
#elif defined(CONFIG_E500MC)
85xx: Add basic e500mc core support Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-23 06:47:38 +00:00
rlwinm r4,r0,27,27,31
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:40:07 +00:00
mr r5,r4
85xx: Add basic e500mc core support Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-23 06:47:38 +00:00
#else
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
mr r4,r0
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:40:07 +00:00
mr r5,r4
85xx: Add basic e500mc core support Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-23 06:47:38 +00:00
#endif
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
powerpc/mpc8xxx: fix core id for multicore booting For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:26 +00:00
/*
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:40:07 +00:00
* r10 has the base address for the entry.
* we cannot access it yet before setting up a new TLB
powerpc/mpc8xxx: fix core id for multicore booting For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:26 +00:00
*/
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-03-25 07:40:07 +00:00
slwi r8,r5,6 /* spin table is padded to 64 byte */
add r10,r3,r8
powerpc/mpc8xxx: fix core id for multicore booting For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-17 08:20:26 +00:00
mtspr SPRN_PIR,r4 /* write to PIR register */
powerpc: mpc85xx: Implement CPU erratum A-007907 for secondary cores Commit 06ad970b53a3 ("powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907") clears L1CSR2 for the boot core, but other cores don't run through the workaround. Add similar code for secondary cores to clear DCSTASHID field in L1CSR2 register. Signed-off-by: York Sun <york.sun@nxp.com>
2017-10-17 15:00:21 +00:00
#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
mfspr r8, L1CSR2
clrrwi r8, r8, 10 /* clear bit [54-63] DCSTASHID */
mtspr L1CSR2, r8
#else
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:08 +00:00
#ifdef CONFIG_SYS_CACHE_STASHING
/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
slwi r8,r4,1
addi r8,r8,32
mtspr L1CSR2,r8
#endif
powerpc: mpc85xx: Implement CPU erratum A-007907 for secondary cores Commit 06ad970b53a3 ("powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907") clears L1CSR2 for the boot core, but other cores don't run through the workaround. Add similar code for secondary cores to clear DCSTASHID field in L1CSR2 register. Signed-off-by: York Sun <york.sun@nxp.com>
2017-10-17 15:00:21 +00:00
#endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:08 +00:00
powerpc/mpc85xx: Workaround for erratum CPU_A011 Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0. It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the same workaround as erratum CPU22. Rearrange registers usage in assembly code to avoid accidental overwriting. Signed-off-by: York Sun <yorksun@freescale.com>
2012-05-07 07:26:47 +00:00
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
*/
powerpc/P4080: Check SVR for CPU22 workaround Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only. Signed-off-by: York Sun <yorksun@freescale.com>
2012-05-07 07:26:45 +00:00
mfspr r3,SPRN_SVR
powerpc/mpc85xx: Workaround for erratum CPU_A011 Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0. It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the same workaround as erratum CPU22. Rearrange registers usage in assembly code to avoid accidental overwriting. Signed-off-by: York Sun <yorksun@freescale.com>
2012-05-07 07:26:47 +00:00
rlwinm r6,r3,24,~0x800 /* clear E bit */
lis r5,SVR_P4080@h
ori r5,r5,SVR_P4080@l
cmpw r6,r5
bne 1f
powerpc/P4080: Check SVR for CPU22 workaround Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only. Signed-off-by: York Sun <yorksun@freescale.com>
2012-05-07 07:26:45 +00:00
rlwinm r3,r3,0,0xf0
powerpc/mpc85xx: Workaround for erratum CPU_A011 Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0. It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the same workaround as erratum CPU22. Rearrange registers usage in assembly code to avoid accidental overwriting. Signed-off-by: York Sun <yorksun@freescale.com>
2012-05-07 07:26:47 +00:00
li r5,0x30
cmpw r3,r5
powerpc/P4080: Check SVR for CPU22 workaround Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only. Signed-off-by: York Sun <yorksun@freescale.com>
2012-05-07 07:26:45 +00:00
bge 2f
powerpc/mpc85xx: Workaround for erratum CPU_A011 Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0. It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the same workaround as erratum CPU22. Rearrange registers usage in assembly code to avoid accidental overwriting. Signed-off-by: York Sun <yorksun@freescale.com>
2012-05-07 07:26:47 +00:00
1:
powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional This erratum applies to the following SoCs: P4080 rev 1.0, 2.0, fixed in rev 3.0 P2041 rev 1.0, 1.1, fixed in rev 2.0 P3041 rev 1.0, 1.1, fixed in rev 2.0. Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround may degrade performance. P4080 erratum CPU22 shares the same workaround. So it is always enabled for P4080. For other SoCs, it can be disabled by hwconfig with syntax: fsl_cpu_a011:disable Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:04:53 +00:00
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
lis r3,toreset(enable_cpu_a011_workaround)@ha
lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
cmpwi r3,0
beq 2f
#endif
powerpc/mpc85xx: Workaround for erratum CPU_A011 Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0. It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the same workaround as erratum CPU22. Rearrange registers usage in assembly code to avoid accidental overwriting. Signed-off-by: York Sun <yorksun@freescale.com>
2012-05-07 07:26:47 +00:00
mfspr r3,L1CSR2
oris r3,r3,(L1CSR2_DCWS)@h
mtspr L1CSR2,r3
powerpc/P4080: Check SVR for CPU22 workaround Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only. Signed-off-by: York Sun <yorksun@freescale.com>
2012-05-07 07:26:45 +00:00
2:
powerpc/p4080: Add workaround for erratum CPU22 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-06 03:35:27 +00:00
#endif
powerpc/mpc85xx: Workaround for A-005812 Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can result in invalid atomic operations. For u-boot, this erratum only impacts SoCs running in write shadow mode. Signed-off-by: York Sun <yorksun@freescale.com>
2013-06-25 18:37:49 +00:00
#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
/*
* A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
* write shadow mode. This code should run after other code setting
* DCWS.
*/
mfspr r3,L1CSR2
andis. r3,r3,(L1CSR2_DCWS)@h
beq 1f
mfspr r3, SPRN_HDBCR0
oris r3, r3, 0x8000
mtspr SPRN_HDBCR0, r3
1:
#endif
85xx: Add support for additional e500mc features * Enable backside L2 * e500mc no longer has timebase enable in HID (moved to CCSR register) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-19 14:16:10 +00:00
#ifdef CONFIG_BACKSIDE_L2_CACHE
powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E The P2040/P2040E have no L2 cache. So we utilize the SVR to determine if we are one of these devices and skip the L2 init code in cpu_init.c and release. For the device tree we skip the updating of the L2 cache properties but we still update the chain of caches so the CPC/L3 node can be properly updated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-21 05:20:21 +00:00
/* skip L2 setup on P2040/P2040E as they have no L2 */
powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E Fix SVR checking for commit acf3f8da. Signed-off-by: York Sun <yorksun@freescale.com>
2012-05-07 07:39:53 +00:00
mfspr r3,SPRN_SVR
rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E The P2040/P2040E have no L2 cache. So we utilize the SVR to determine if we are one of these devices and skip the L2 init code in cpu_init.c and release. For the device tree we skip the updating of the L2 cache properties but we still update the chain of caches so the CPC/L3 node can be properly updated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-21 05:20:21 +00:00
lis r3,SVR_P2040@h
ori r3,r3,SVR_P2040@l
powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E Fix SVR checking for commit acf3f8da. Signed-off-by: York Sun <yorksun@freescale.com>
2012-05-07 07:39:53 +00:00
cmpw r6,r3
powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E The P2040/P2040E have no L2 cache. So we utilize the SVR to determine if we are one of these devices and skip the L2 init code in cpu_init.c and release. For the device tree we skip the updating of the L2 cache properties but we still update the chain of caches so the CPC/L3 node can be properly updated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-21 05:20:21 +00:00
beq 3f
85xx: Add support for additional e500mc features * Enable backside L2 * e500mc no longer has timebase enable in HID (moved to CCSR register) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-19 14:16:10 +00:00
/* Enable/invalidate the L2 cache */
msync
ppc/85xx: Fix misc L2 cache enabling bug We need loop-check the flash clear lock and enable bit for L2 cache. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-30 23:59:55 +00:00
lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
mtspr SPRN_L2CSR0,r2
85xx: Add support for additional e500mc features * Enable backside L2 * e500mc no longer has timebase enable in HID (moved to CCSR register) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-19 14:16:10 +00:00
1:
mfspr r3,SPRN_L2CSR0
ppc/85xx: Fix misc L2 cache enabling bug We need loop-check the flash clear lock and enable bit for L2 cache. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-30 23:59:55 +00:00
and. r1,r3,r2
85xx: Add support for additional e500mc features * Enable backside L2 * e500mc no longer has timebase enable in HID (moved to CCSR register) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-19 14:16:10 +00:00
bne 1b
85xx: Add support for e500mc cache stashing The e500mc core supports the ability to stash into the L1 or L2 cache, however we need to uniquely identify the caches with an id. We use the following equation to set the various stash-ids: 32 + coreID*2 + 0(L1) or 1(L2) The 0 (for L1) or 1 (for L2) matches the CT field used be various cache control instructions. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-19 07:53:01 +00:00
#ifdef CONFIG_SYS_CACHE_STASHING
/* set stash id to (coreID) * 2 + 32 + L2 (1) */
addi r3,r8,1
mtspr SPRN_L2CSR1,r3
#endif
85xx: Add support for additional e500mc features * Enable backside L2 * e500mc no longer has timebase enable in HID (moved to CCSR register) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-19 14:16:10 +00:00
lis r3,CONFIG_SYS_INIT_L2CSR0@h
ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
mtspr SPRN_L2CSR0,r3
isync
ppc/85xx: Fix misc L2 cache enabling bug We need loop-check the flash clear lock and enable bit for L2 cache. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-30 23:59:55 +00:00
2:
mfspr r3,SPRN_L2CSR0
andis. r1,r3,L2CSR0_L2E@h
beq 2b
85xx: Add support for additional e500mc features * Enable backside L2 * e500mc no longer has timebase enable in HID (moved to CCSR register) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-19 14:16:10 +00:00
#endif
powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E The P2040/P2040E have no L2 cache. So we utilize the SVR to determine if we are one of these devices and skip the L2 init code in cpu_init.c and release. For the device tree we skip the updating of the L2 cache properties but we still update the chain of caches so the CPC/L3 node can be properly updated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-21 05:20:21 +00:00
3:
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
/* setup mapping for the spin table, WIMGE=0b00100 */
lis r13,toreset(__spin_table_addr)@h
ori r13,r13,toreset(__spin_table_addr)@l
85xx: MP Boot Page Translation update This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-23 20:55:47 +00:00
lwz r13,0(r13)
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
/* mask by 4K */
rlwinm r13,r13,0,0,19
85xx: MP Boot Page Translation update This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-23 20:55:47 +00:00
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
mtspr SPRN_MAS0,r11
lis r11,(MAS1_VALID|MAS1_IPROT)@h
ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
mtspr SPRN_MAS1,r11
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
oris r11,r13,(MAS2_M|MAS2_G)@h
ori r11,r13,(MAS2_M|MAS2_G)@l
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
mtspr SPRN_MAS2,r11
85xx: MP Boot Page Translation update This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-23 20:55:47 +00:00
oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
mtspr SPRN_MAS3,r11
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
li r11,0
mtspr SPRN_MAS7,r11
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
tlbwe
85xx: MP Boot Page Translation update This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-23 20:55:47 +00:00
/*
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
* __bootpg_addr has the address of __second_half_boot_page
* jump there in AS=1 space with cache enabled
85xx: MP Boot Page Translation update This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-23 20:55:47 +00:00
*/
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
lis r13,toreset(__bootpg_addr)@h
ori r13,r13,toreset(__bootpg_addr)@l
lwz r11,0(r13)
mtspr SPRN_SRR0,r11
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
mfmsr r13
ori r12,r13,MSR_IS|MSR_DS@l
mtspr SPRN_SRR1,r12
rfi
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
/*
* Allocate some space for the SDRAM address of the bootpg.
* This variable has to be in the boot page so that it can
* be accessed by secondary cores when they come out of reset.
*/
.align L1_CACHE_SHIFT
.globl __bootpg_addr
__bootpg_addr:
.long 0
.global __spin_table_addr
__spin_table_addr:
.long 0
/*
* This variable is set by cpu_init_r() after parsing hwconfig
* to enable workaround for erratum NMG_CPU_A011.
*/
.align L1_CACHE_SHIFT
.global enable_cpu_a011_workaround
enable_cpu_a011_workaround:
.long 1
/* Fill in the empty space. The actual reset vector is
* the last word of the page */
__secondary_start_code_end:
.space 4092 - (__secondary_start_code_end - __secondary_start_page)
__secondary_reset_vector:
b __secondary_start_page
/* this is a separated page for the spin table and cacheable boot code */
.align L1_CACHE_SHIFT
.global __second_half_boot_page
__second_half_boot_page:
powerpc/mpc85xx: Temporary fix for spin table backward compatibility Once u-boot sets the spin table to cache-enabled memory, old kernel which uses cache-inhibit mapping without coherence will not work properly. We use this temporary fix until kernel has updated its spin table code. For now this fix is activated by default. To disable this fix for new kernel, set environmental variable "spin_table_compat=no". After kernel has updated spin table code, this default shall be changed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-28 08:12:54 +00:00
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
lis r3,(spin_table_compat - __second_half_boot_page)@h
ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
add r3,r3,r11 /* r11 has the address of __second_half_boot_page */
lwz r14,0(r3)
#endif
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
#define ENTRY_ADDR_UPPER 0
#define ENTRY_ADDR_LOWER 4
#define ENTRY_R3_UPPER 8
#define ENTRY_R3_LOWER 12
#define ENTRY_RESV 16
#define ENTRY_PIR 20
#define ENTRY_SIZE 64
/*
* setup the entry
* r10 has the base address of the spin table.
* spin table is defined as
* struct {
* uint64_t entry_addr;
* uint64_t r3;
* uint32_t rsvd1;
* uint32_t pir;
* };
* we pad this struct to 64 bytes so each entry is in its own cacheline
*/
li r3,0
li r8,1
mfspr r4,SPRN_PIR
stw r3,ENTRY_ADDR_UPPER(r10)
stw r3,ENTRY_R3_UPPER(r10)
stw r4,ENTRY_R3_LOWER(r10)
stw r3,ENTRY_RESV(r10)
stw r4,ENTRY_PIR(r10)
msync
stw r8,ENTRY_ADDR_LOWER(r10)
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
/* spin waiting for addr */
powerpc/mpc85xx: Temporary fix for spin table backward compatibility Once u-boot sets the spin table to cache-enabled memory, old kernel which uses cache-inhibit mapping without coherence will not work properly. We use this temporary fix until kernel has updated its spin table code. For now this fix is activated by default. To disable this fix for new kernel, set environmental variable "spin_table_compat=no". After kernel has updated spin table code, this default shall be changed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-28 08:12:54 +00:00
3:
/*
* To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
* memory. Old OS may not work with this change. A patch is waiting to be
* accepted for Linux kernel. Other OS needs similar fix to spin table.
* For OSes with old spin table code, we can enable this temporary fix by
* setting environmental variable "spin_table_compat". For new OSes, set
* "spin_table_compat=no". After Linux is fixed, we can remove this macro
* and related code. For now, it is enabled by default.
*/
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
cmpwi r14,0
beq 4f
dcbf 0, r10
sync
4:
#endif
lwz r4,ENTRY_ADDR_LOWER(r10)
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
andi. r11,r4,1
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
bne 3b
85xx: Additional fixes and cleanup of MP code * adjust __spin_table alignment to match ePAPR v0.94 spec * loop over all cpus when determing who is up. This fixes an issue if the "boot cpu" isn't core0. The "boot cpu" will already be in the cpu_up_mask so there is no harm * Added some protection in the code to ensure proper behavior. These changes are explicitly needed but don't hurt: - Added eieio to ensure the "hot word" of the table is written after all other table updates have occurred. - Added isync to ensure we don't prefetch loading of table entries until we a released These issues we raised by Dave Liu. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-28 07:24:04 +00:00
isync
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
/* get the upper bits of the addr */
lwz r11,ENTRY_ADDR_UPPER(r10)
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
/* setup branch addr */
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
mtspr SPRN_SRR0,r4
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
/* mark the entry as released */
li r8,3
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
stw r8,ENTRY_ADDR_LOWER(r10)
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
/* mask by ~64M to setup our tlb we will jump to */
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
rlwinm r12,r4,0,0,5
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
/*
* setup r3, r4, r5, r6, r7, r8, r9
* r3 contains the value to put in the r3 register at secondary cpu
* entry. The high 32-bits are ignored on 32-bit chip implementations.
* 64-bit chip implementations however shall load all 64-bits
*/
#ifdef CONFIG_SYS_PPC64
ld r3,ENTRY_R3_UPPER(r10)
#else
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
lwz r3,ENTRY_R3_LOWER(r10)
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
#endif
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
li r4,0
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
li r5,0
powerpc/mpc85xx: Remove R6 from spin table R6 was in ePAPR draft version but was dropped in official spec. Removing it to comply. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:29 +00:00
li r6,0
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
lis r7,(64*1024*1024)@h
li r8,0
li r9,0
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
/* load up the pir */
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
lwz r0,ENTRY_PIR(r10)
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
mtspr SPRN_PIR,r0
mfspr r0,SPRN_PIR
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
stw r0,ENTRY_PIR(r10)
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
Set IVPR to kenrel entry point in second core boot page Assuming the OSes exception vectors start from the base of kernel address, and the kernel physical starting address can be relocated to an non-zero address. This patch enables the second core to have a valid IVPR for debugger before kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid value for second core which runs kernel at different physical address other than 0x0. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-12-03 15:08:19 +00:00
mtspr IVPR,r12
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
/*
* Coming here, we know the cpu has one TLB mapping in TLB1[0]
* which maps 0xfffff000-0xffffffff one-to-one. We set up a
* second mapping that maps addr 1:1 for 64M, and then we jump to
* addr
*/
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
mtspr SPRN_MAS0,r10
lis r10,(MAS1_VALID|MAS1_IPROT)@h
ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
mtspr SPRN_MAS1,r10
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
/* WIMGE = 0b00000 for now */
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
mtspr SPRN_MAS2,r12
ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
mtspr SPRN_MAS3,r12
#ifdef CONFIG_ENABLE_36BIT_PHYS
mtspr SPRN_MAS7,r11
#endif
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
tlbwe
/* Now we have another mapping for this page, so we jump to that
* mapping
*/
85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 13:34:25 +00:00
mtspr SPRN_SRR1,r13
rfi
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
85xx: MP Boot Page Translation update This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-23 20:55:47 +00:00
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
.align 6
85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 22:48:33 +00:00
.globl __spin_table
__spin_table:
8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-31 06:38:14 +00:00
.space CONFIG_MAX_CPUS*ENTRY_SIZE
powerpc/mpc85xx: Temporary fix for spin table backward compatibility Once u-boot sets the spin table to cache-enabled memory, old kernel which uses cache-inhibit mapping without coherence will not work properly. We use this temporary fix until kernel has updated its spin table code. For now this fix is activated by default. To disable this fix for new kernel, set environmental variable "spin_table_compat=no". After kernel has updated spin table code, this default shall be changed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-28 08:12:54 +00:00
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
.align L1_CACHE_SHIFT
.global spin_table_compat
spin_table_compat:
.long 1
#endif
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:30 +00:00
__spin_table_end:
.space 4096 - (__spin_table_end - __spin_table)
Reference in a new issue Copy permalink