mirror of
https://github.com/AsahiLinux/u-boot
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357 lines
11 KiB
C
357 lines
11 KiB
C
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/*
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* Copyright (C) 2003 ETC s.r.o.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Written by Peter Figuli <peposh@etc.sk>, 2003.
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*
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* 2003/13/06 Initial MP10 Support copied from wepep250
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
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#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
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#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
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#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
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#define CONFIG_IMX_SERIAL1
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/*
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* Select serial console configuration
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*/
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/*
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* Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
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* neccessary in include/cmd_confdefs.h file. (Un)comment for getting
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* functionality or size of u-boot code.
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*/
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
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& ~CFG_CMD_LOADS \
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& ~CFG_CMD_CONSOLE \
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& ~CFG_CMD_AUTOSCRIPT \
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| CFG_CMD_NET \
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| CFG_CMD_PING \
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| CFG_CMD_DHCP \
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)
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#include <cmd_confdefs.h>
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/*
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* Boot options. Setting delay to -1 stops autostart count down.
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* NOTE: Sending parameters to kernel depends on kernel version and
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* 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
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* parameters at all! Do not get confused by them so.
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*/
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#define CONFIG_BOOTDELAY -1
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#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
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#define CONFIG_BOOTCOMMAND "bootm 10040000"
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#define CONFIG_SHOW_BOOT_PROGRESS
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#define CONFIG_ETHADDR 80:81:82:83:84:85
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 10.10.10.9
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#define CONFIG_SERVERIP 10.10.10.10
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/*
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* General options for u-boot. Modify to save memory foot print
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*/
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#define CFG_LONGHELP /* undef saves memory */
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#define CFG_PROMPT "scb9328> " /* prompt string */
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#define CFG_CBSIZE 256 /* console I/O buffer */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */
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#define CFG_MAXARGS 16 /* max command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */
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#define CFG_MEMTEST_START 0x08100000 /* memtest test area */
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#define CFG_MEMTEST_END 0x08F00000
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#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */
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#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CFG_CPUSPEED 0x141 /* core clock - register value */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_BAUDRATE 115200
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/*
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* Definitions related to passing arguments to kernel.
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*/
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#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
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#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
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#define CONFIG_INITRD_TAG 1 /* send initrd params */
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#undef CONFIG_VFD /* do not send framebuffer setup */
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/*
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* Malloc pool need to host env + 128 Kb reserve for other allocations.
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) )
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_STACKSIZE (120<<10) /* stack size */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
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#endif
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/* SDRAM Setup Values
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0x910a8300 Precharge Command CAS 3
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0x910a8200 Precharge Command CAS 2
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0xa10a8300 AutoRefresh Command CAS 3
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0xa10a8200 Set AutoRefresh Command CAS 2 */
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#define PRECHARGE_CMD 0x910a8200
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#define AUTOREFRESH_CMD 0xa10a8200
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/*
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* SDRAM Memory Map
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*/
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/* SH FIXME */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
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#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
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#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
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/*
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* Flash Controller settings
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*/
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/*
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* Hardware drivers
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*/
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/*
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* Configuration for FLASH memory for the Synertronixx board
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*/
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/* #define SCB9328_FLASH_32M */
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/* 32MB */
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#ifdef SCB9328_FLASH_32M
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#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
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#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
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#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
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#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
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#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */
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#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
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#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
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#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
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#else
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/* 16MB */
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#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
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#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
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#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
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#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
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#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */
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#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
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#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
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#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
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#endif /* SCB9328_FLASH_32M */
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/* This should be defined if CFI FLASH device is present. Actually benefit
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is not so clear to me. In other words we can provide more informations
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to user, but this expects more complex flash handling we do not provide
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now.*/
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#undef CFG_FLASH_CFI
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#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */
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#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */
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#define CFG_FLASH_BASE SCB9328_FLASH_BASE
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/*
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* This is setting for JFFS2 support in u-boot.
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* Right now there is no gain for user, but later on booting kernel might be
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* possible. Consider using XIP kernel running from flash to save RAM
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* footprint.
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* NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
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*/
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#define CFG_JFFS2_FIRST_BANK 0
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#define CFG_JFFS2_FIRST_SECTOR 5
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#define CFG_JFFS2_NUM_BANKS 1
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/*
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* Environment setup. Definitions of monitor location and size with
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* definition of environment setup ends up in 2 possibilities.
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* 1. Embeded environment - in u-boot code is space for environment
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* 2. Environment is read from predefined sector of flash
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* Right now we support 2. possiblity, but expecting no env placed
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* on mentioned address right now. This also needs to provide whole
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* sector for it - for us 256Kb is really waste of memory. U-boot uses
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* default env. and until kernel parameters could be sent to kernel
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* env. has no sense to us.
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*/
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/* Setup for PA23 which is Reset Default PA23 but has to become
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CS5 */
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#define CFG_GPR_A_VAL 0x00800000
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#define CFG_GIUS_A_VAL 0x0043fffe
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#define CFG_MONITOR_BASE 0x10000000
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#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */
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#define CFG_ENV_SIZE 0x20000
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#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
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/*
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* CSxU_VAL:
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* 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
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* |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
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*
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* CSxL_VAL:
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* 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
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* | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
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*/
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#define CFG_CS0U_VAL 0x000F2000
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#define CFG_CS0L_VAL 0x11110d01
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#define CFG_CS1U_VAL 0x000F0a00
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#define CFG_CS1L_VAL 0x11110601
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#define CFG_CS2U_VAL 0x0
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#define CFG_CS2L_VAL 0x0
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#define CFG_CS3U_VAL 0x000FFFFF
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#define CFG_CS3L_VAL 0x00000303
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#define CFG_CS4U_VAL 0x000F0a00
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#define CFG_CS4L_VAL 0x11110301
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/* CNC == 3 too long
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#define CFG_CS5U_VAL 0x0000C210 */
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/* #define CFG_CS5U_VAL 0x00008400
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mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
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kaum langsamer ist */
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/* #define CFG_CS5U_VAL 0x00009400
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#define CFG_CS5L_VAL 0x11010D03 */
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#define CFG_CS5U_VAL 0x00008400
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#define CFG_CS5L_VAL 0x00000D03
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#define CONFIG_DRIVER_DM9000 1
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#define CONFIG_DRIVER_DM9000 1
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#define CONFIG_DM9000_BASE 0x16000000
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#define DM9000_IO CONFIG_DM9000_BASE
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#define DM9000_DATA (CONFIG_DM9000_BASE+4)
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/* #define CONFIG_DM9000_USE_8BIT */
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#define CONFIG_DM9000_USE_16BIT
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/* #define CONFIG_DM9000_USE_32BIT */
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/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
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f_ref=16,777MHz
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0x002a141f: 191,9944MHz
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0x040b2007: 144MHz
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0x042a141f: 96MHz
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0x0811140d: 64MHz
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0x040e200e: 150MHz
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0x00321431: 200MHz
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0x08001800: 64MHz mit 16er Quarz
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0x04001800: 96MHz mit 16er Quarz
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0x04002400: 144MHz mit 16er Quarz
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31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
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|XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
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#define CPU200
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#ifdef CPU200
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#define CFG_MPCTL0_VAL 0x00321431
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#else
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#define CFG_MPCTL0_VAL 0x040e200e
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#endif
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/* #define BUS64 */
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#define BUS72
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#ifdef BUS72
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#define CFG_SPCTL0_VAL 0x04002400
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#endif
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#ifdef BUS96
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#define CFG_SPCTL0_VAL 0x04001800
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#endif
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#ifdef BUS64
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#define CFG_SPCTL0_VAL 0x08001800
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#endif
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/* Das ist der BCLK Divider, der aus der System PLL
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BCLK und HCLK erzeugt:
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31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
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0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
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0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
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0x2f001003 : 192MHz/5=38,4MHz
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0x2f000003 : 64MHz/1
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Bit 22: SPLL Restart
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Bit 21: MPLL Restart */
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#ifdef BUS64
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#define CFG_CSCR_VAL 0x2f030003
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#endif
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#ifdef BUS72
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#define CFG_CSCR_VAL 0x2f030403
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#endif
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/*
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* Well this has to be defined, but on the other hand it is used differently
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* one may expect. For instance loadb command do not cares :-)
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* So advice is - do not relay on this...
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*/
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#define CFG_LOAD_ADDR 0x08400000
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#define MHZ16QUARZINUSE
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#ifdef MHZ16QUARZINUSE
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#define CONFIG_SYSPLL_CLK_FREQ 16000000
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#else
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#define CONFIG_SYSPLL_CLK_FREQ 16780000
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#endif
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#define CONFIG_SYS_CLK_FREQ 16780000
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/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
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#define CFG_FMCR_VAL 0x00000001
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/* Bit[0:3] contain PERCLK1DIV for UART 1
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0x000b00b ->b<- -> 192MHz/12=16MHz
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0x000b00b ->8<- -> 144MHz/09=16MHz
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0x000b00b ->3<- -> 64MHz/4=16MHz */
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#ifdef BUS96
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#define CFG_PCDR_VAL 0x000b00b5
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#endif
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#ifdef BUS64
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#define CFG_PCDR_VAL 0x000b00b3
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#endif
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#ifdef BUS72
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#define CFG_PCDR_VAL 0x000b00b8
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#endif
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#endif /* __CONFIG_H */
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