2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2011-06-16 23:30:47 +00:00
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/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Aneesh V <aneesh@ti.com>
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*/
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2019-11-14 19:57:39 +00:00
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#include <cpu_func.h>
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2020-05-10 17:39:56 +00:00
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#include <asm/cache.h>
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2011-06-16 23:30:47 +00:00
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#include <linux/types.h>
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/utils.h>
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2016-04-09 11:53:49 +00:00
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#define ARMV7_DCACHE_INVAL_RANGE 1
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#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
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2011-06-16 23:30:47 +00:00
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2019-05-03 13:41:00 +00:00
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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2016-04-09 11:53:48 +00:00
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/* Asm functions from cache_v7_asm.S */
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void v7_flush_dcache_all(void);
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2016-04-09 11:53:49 +00:00
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void v7_invalidate_dcache_all(void);
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2016-04-09 11:53:48 +00:00
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2011-06-16 23:30:47 +00:00
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static u32 get_ccsidr(void)
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{
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u32 ccsidr;
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/* Read current CP15 Cache Size ID Register */
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asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
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return ccsidr;
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}
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2014-08-26 15:34:20 +00:00
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static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
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2011-06-16 23:30:47 +00:00
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{
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u32 mva;
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/* Align start to cache line boundary */
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start &= ~(line_len - 1);
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for (mva = start; mva < stop; mva = mva + line_len) {
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/* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */
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asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
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}
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}
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static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
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{
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u32 mva;
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2016-06-20 01:43:02 +00:00
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if (!check_cache_range(start, stop))
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return;
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2011-06-16 23:30:47 +00:00
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for (mva = start; mva < stop; mva = mva + line_len) {
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/* DCIMVAC - Invalidate data cache by MVA to PoC */
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asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
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}
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}
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static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
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{
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u32 line_len, ccsidr;
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ccsidr = get_ccsidr();
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line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
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CCSIDR_LINE_SIZE_OFFSET) + 2;
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/* Converting from words to bytes */
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line_len += 2;
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/* converting from log2(linelen) to linelen */
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line_len = 1 << line_len;
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switch (range_op) {
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case ARMV7_DCACHE_CLEAN_INVAL_RANGE:
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v7_dcache_clean_inval_range(start, stop, line_len);
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break;
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case ARMV7_DCACHE_INVAL_RANGE:
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v7_dcache_inval_range(start, stop, line_len);
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break;
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}
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2011-08-11 04:35:44 +00:00
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/* DSB to make sure the operation is complete */
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2016-08-01 22:54:53 +00:00
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dsb();
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2011-06-16 23:30:47 +00:00
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}
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/* Invalidate TLB */
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static void v7_inval_tlb(void)
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{
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/* Invalidate entire unified TLB */
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asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
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/* Invalidate entire data TLB */
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asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
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/* Invalidate entire instruction TLB */
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asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
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/* Full system DSB - make sure that the invalidation is complete */
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2016-08-01 22:54:53 +00:00
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dsb();
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2011-06-16 23:30:47 +00:00
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/* Full system ISB - make sure the instruction stream sees it */
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2016-08-01 22:54:53 +00:00
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isb();
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2011-06-16 23:30:47 +00:00
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}
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void invalidate_dcache_all(void)
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{
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2016-04-09 11:53:49 +00:00
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v7_invalidate_dcache_all();
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2011-06-16 23:30:47 +00:00
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v7_outer_cache_inval_all();
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}
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/*
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* Performs a clean & invalidation of the entire data cache
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* at all levels
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*/
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void flush_dcache_all(void)
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{
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2016-04-09 11:53:48 +00:00
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v7_flush_dcache_all();
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2011-06-16 23:30:47 +00:00
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v7_outer_cache_flush_all();
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}
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/*
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* Invalidates range in all levels of D-cache/unified cache used:
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* Affects the range [start, stop - 1]
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*/
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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2015-07-27 20:34:17 +00:00
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check_cache_range(start, stop);
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2011-06-16 23:30:47 +00:00
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v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
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v7_outer_cache_inval_range(start, stop);
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}
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/*
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* Flush range(clean & invalidate) from all levels of D-cache/unified
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* cache used:
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* Affects the range [start, stop - 1]
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*/
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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2015-07-27 20:34:17 +00:00
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check_cache_range(start, stop);
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2011-06-16 23:30:47 +00:00
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v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
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v7_outer_cache_flush_range(start, stop);
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}
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void arm_init_before_mmu(void)
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{
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v7_outer_cache_enable();
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invalidate_dcache_all();
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v7_inval_tlb();
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}
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2012-10-17 13:24:53 +00:00
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void mmu_page_table_flush(unsigned long start, unsigned long stop)
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{
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flush_dcache_range(start, stop);
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v7_inval_tlb();
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}
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2019-05-03 13:41:00 +00:00
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#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
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2011-06-16 23:30:47 +00:00
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void invalidate_dcache_all(void)
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{
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}
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void flush_dcache_all(void)
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{
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}
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2016-06-27 14:19:16 +00:00
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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2011-06-16 23:30:47 +00:00
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void arm_init_before_mmu(void)
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{
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}
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2012-10-17 13:24:53 +00:00
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void mmu_page_table_flush(unsigned long start, unsigned long stop)
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{
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}
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2019-05-03 13:41:00 +00:00
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#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
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2011-06-16 23:30:47 +00:00
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2019-05-03 13:41:00 +00:00
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#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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2011-06-16 23:30:47 +00:00
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/* Invalidate entire I-cache and branch predictor array */
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void invalidate_icache_all(void)
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{
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/*
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* Invalidate all instruction caches to PoU.
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* Also flushes branch target cache.
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*/
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asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
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/* Invalidate entire branch predictor array */
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asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
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/* Full system DSB - make sure that the invalidation is complete */
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2016-08-01 22:54:53 +00:00
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dsb();
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2011-06-16 23:30:47 +00:00
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/* ISB - make sure the instruction stream sees it */
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2016-08-01 22:54:53 +00:00
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isb();
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2011-06-16 23:30:47 +00:00
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}
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#else
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void invalidate_icache_all(void)
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{
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}
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#endif
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2014-06-23 20:07:04 +00:00
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/* Stub implementations for outer cache operations */
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__weak void v7_outer_cache_enable(void) {}
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__weak void v7_outer_cache_disable(void) {}
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__weak void v7_outer_cache_flush_all(void) {}
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__weak void v7_outer_cache_inval_all(void) {}
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__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
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__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}
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