2018-05-06 21:58:06 +00:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
2013-05-12 22:40:54 +00:00
|
|
|
/*
|
|
|
|
* Configuation settings for the SAMA5D3xEK board.
|
|
|
|
*
|
|
|
|
* Copyright (C) 2012 - 2013 Atmel
|
|
|
|
*
|
|
|
|
* based on at91sam9m10g45ek.h by:
|
|
|
|
* Stelian Pop <stelian@popies.net>
|
|
|
|
* Lead Tech Design <www.leadtechdesign.com>
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __CONFIG_H
|
|
|
|
#define __CONFIG_H
|
|
|
|
|
2015-03-30 06:51:19 +00:00
|
|
|
#include "at91-sama5_common.h"
|
2013-05-12 22:40:54 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* This needs to be defined for the OHCI code to work but it is defined as
|
|
|
|
* ATMEL_ID_UHPHS in the CPU specific header files.
|
|
|
|
*/
|
2017-09-14 03:07:42 +00:00
|
|
|
#define ATMEL_ID_UHP 32
|
2013-05-12 22:40:54 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Specify the clock enable bit in the PMC_SCER register.
|
|
|
|
*/
|
2017-09-14 03:07:42 +00:00
|
|
|
#define ATMEL_PMC_UHP (1 << 6)
|
2013-05-12 22:40:54 +00:00
|
|
|
|
2014-07-18 08:43:08 +00:00
|
|
|
/* NOR flash */
|
2017-02-11 13:43:54 +00:00
|
|
|
#ifdef CONFIG_MTD_NOR_FLASH
|
2014-07-18 08:43:08 +00:00
|
|
|
#define CONFIG_SYS_FLASH_BASE 0x10000000
|
|
|
|
#endif
|
2013-05-12 22:40:54 +00:00
|
|
|
|
|
|
|
/* SDRAM */
|
2017-09-14 03:07:42 +00:00
|
|
|
#define CONFIG_SYS_SDRAM_BASE 0x20000000
|
2013-05-12 22:40:54 +00:00
|
|
|
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
|
|
|
|
|
|
|
|
/* SerialFlash */
|
|
|
|
|
|
|
|
/* NAND flash */
|
|
|
|
#ifdef CONFIG_CMD_NAND
|
2022-11-12 22:36:51 +00:00
|
|
|
#define CFG_SYS_NAND_BASE 0x60000000
|
2013-05-12 22:40:54 +00:00
|
|
|
/* our ALE is AD21 */
|
2022-11-12 22:36:51 +00:00
|
|
|
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
|
2013-05-12 22:40:54 +00:00
|
|
|
/* our CLE is AD22 */
|
2022-11-12 22:36:51 +00:00
|
|
|
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
|
2017-07-29 01:31:42 +00:00
|
|
|
#endif
|
2013-05-12 22:40:54 +00:00
|
|
|
|
2013-11-15 03:12:38 +00:00
|
|
|
/* SPL */
|
|
|
|
|
2013-05-12 22:40:54 +00:00
|
|
|
#endif
|